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proof of concept

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tildearrow 2024-10-19 17:52:24 -05:00
parent 4281acc9dc
commit dd9d8dccd1
4 changed files with 38 additions and 15 deletions
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2
src/engine/dispatch.h
View file

@ -383,6 +383,8 @@ struct DivRegWrite {
* - xx is the instance ID
* - data is the sample position
* - 0xffffffff: reset
* - 0xfffffffe: add delay
* - data is the delay
*/
unsigned int addr;
unsigned int val;

6
src/engine/platform/fmsharedbase.h
View file

@ -76,11 +76,11 @@ class DivPlatformFMBase: public DivDispatch {
};
struct QueuedWrite {
unsigned short addr;
unsigned int addr;
unsigned char val;
bool addrOrVal;
QueuedWrite(): addr(0), val(0), addrOrVal(false) {}
QueuedWrite(unsigned short a, unsigned char v): addr(a), val(v), addrOrVal(false) {}
QueuedWrite(unsigned int a, unsigned char v): addr(a), val(v), addrOrVal(false) {}
};
FixedQueue<QueuedWrite,2048> writes;
@ -97,7 +97,7 @@ class DivPlatformFMBase: public DivDispatch {
pendingWrites[a]=v;
}
}
inline void immWrite(unsigned short a, unsigned char v) {
inline void immWrite(unsigned int a, unsigned char v) {
if (!skipRegisterWrites) {
writes.push_back(QueuedWrite(a,v));
if (dumpWrites) {

37
src/engine/platform/genesis.cpp
View file

@ -142,11 +142,16 @@ void DivPlatformGenesis::acquire_nuked(short** buf, size_t len) {
for (size_t h=0; h<len; h++) {
processDAC(rate);
if (delay>0) delay--;
os[0]=0; os[1]=0;
for (int i=0; i<6; i++) {
if (!writes.empty()) {
if (delay<=0 && !writes.empty()) {
QueuedWrite& w=writes.front();
if (w.addrOrVal) {
if (w.addr==0xfffffffe) {
delay=w.val*3;
writes.pop_front();
} else if (w.addrOrVal) {
//logV("%.3x=%.2x",w.addr,w.val);
OPN2_Write(&fm,0x1+((w.addr>>8)<<1),w.val);
regPool[w.addr&0x1ff]=w.val;
@ -224,12 +229,18 @@ void DivPlatformGenesis::acquire_ymfm(short** buf, size_t len) {
for (size_t h=0; h<len; h++) {
processDAC(rate);
if (delay>0) delay--;
os[0]=0; os[1]=0;
if (!writes.empty()) {
if (delay<=0 && !writes.empty()) {
QueuedWrite& w=writes.front();
fm_ymfm->write(0x0+((w.addr>>8)<<1),w.addr);
fm_ymfm->write(0x1+((w.addr>>8)<<1),w.val);
regPool[w.addr&0x1ff]=w.val;
if (w.addr==0xfffffffe) {
delay=w.val;
} else {
fm_ymfm->write(0x0+((w.addr>>8)<<1),w.addr);
fm_ymfm->write(0x1+((w.addr>>8)<<1),w.val);
regPool[w.addr&0x1ff]=w.val;
}
writes.pop_front();
if (dacWrite>=0) {
@ -372,9 +383,14 @@ void DivPlatformGenesis::acquire_nuked276(short** buf, size_t len) {
//lleCycle=0;
if (!writes.empty()) {
if (delay>0) delay--;
if (delay<=0 && !writes.empty()) {
QueuedWrite& w=writes.front();
if (w.addrOrVal) {
if (w.addr==0xfffffffe) {
delay=w.val;
writes.pop_front();
} else if (w.addrOrVal) {
//logV("%.3x=%.2x",w.addr,w.val);
//OPN2_Write(&fm,0x1+((w.addr>>8)<<1),w.val);
was_reg_write=true;
@ -871,9 +887,7 @@ void DivPlatformGenesis::tick(bool sysTick) {
// hard reset handling
if (mustHardReset) {
for (unsigned int i=hardResetElapsed; i<hardResetCycles; i++) {
immWrite(0xf0,i&0xff);
}
immWrite(0xfffffffe,hardResetCycles-hardResetElapsed);
for (int i=0; i<csmChan; i++) {
if (i==2 && extMode) continue;
if ((chan[i].keyOn || chan[i].opMaskChanged) && chan[i].hardReset) {
@ -1712,6 +1726,7 @@ void DivPlatformGenesis::reset() {
dacWrite=-1;
canWriteDAC=true;
interruptSim=0;
delay=0;
if (softPCM) {
chan[5].dacMode=true;

8
src/engine/vgmOps.cpp
View file

@ -2686,9 +2686,15 @@ SafeWriter* DivEngine::saveVGM(bool* sysToExport, bool loop, int version, bool p
// get register dumps and put them into delayed writes
int writeNum=0;
for (int i=0; i<song.systemLen; i++) {
int curDelay=0;
std::vector<DivRegWrite>& writes=disCont[i].dispatch->getRegisterWrites();
for (DivRegWrite& j: writes) {
sortedWrites.push_back(std::pair<int,DivDelayedWrite>(i,DivDelayedWrite(0,writeNum++,j.addr,j.val)));
if (j.addr==0xfffffffe) { // delay
curDelay+=(double)j.val*(44100.0/(double)disCont[i].dispatch->rate);
if (curDelay>totalWait) curDelay=totalWait-1;
} else {
sortedWrites.push_back(std::pair<int,DivDelayedWrite>(i,DivDelayedWrite(curDelay,writeNum++,j.addr,j.val)));
}
}
writes.clear();
}