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OPL: partially enable VGM export

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it works except for fake reset
This commit is contained in:
tildearrow 2022-03-30 03:36:16 -05:00
parent f1ee04393b
commit cc152bc3d0
2 changed files with 79 additions and 0 deletions
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6
src/engine/sysDef.cpp
View file

@ -1695,6 +1695,12 @@ bool DivEngine::isVGMExportable(DivSystem which) {
case DIV_SYSTEM_VRC7: case DIV_SYSTEM_VRC7:
case DIV_SYSTEM_X1_010: case DIV_SYSTEM_X1_010:
case DIV_SYSTEM_SWAN: case DIV_SYSTEM_SWAN:
case DIV_SYSTEM_OPL:
case DIV_SYSTEM_OPL_DRUMS:
case DIV_SYSTEM_OPL2:
case DIV_SYSTEM_OPL2_DRUMS:
case DIV_SYSTEM_OPL3:
case DIV_SYSTEM_OPL3_DRUMS:
return true; return true;
default: default:
return false; return false;

73
src/engine/vgmOps.cpp
View file

@ -317,6 +317,16 @@ void DivEngine::performVGMWrite(SafeWriter* w, DivSystem sys, DivRegWrite& write
w->writeC(0xd6+i); w->writeC(0xd6+i);
} }
break; break;
// TODO: it's 3:35am
case DIV_SYSTEM_OPL:
case DIV_SYSTEM_OPL_DRUMS:
break;
case DIV_SYSTEM_OPL2:
case DIV_SYSTEM_OPL2_DRUMS:
break;
case DIV_SYSTEM_OPL3:
case DIV_SYSTEM_OPL3_DRUMS:
break;
default: default:
break; break;
} }
@ -467,6 +477,33 @@ void DivEngine::performVGMWrite(SafeWriter* w, DivSystem sys, DivRegWrite& write
w->writeC(write.val&0xff); w->writeC(write.val&0xff);
} }
break; break;
case DIV_SYSTEM_OPL:
case DIV_SYSTEM_OPL_DRUMS:
w->writeC(0x0b|baseAddr1);
w->writeC(write.addr&0xff);
w->writeC(write.val);
break;
case DIV_SYSTEM_OPL2:
case DIV_SYSTEM_OPL2_DRUMS:
w->writeC(0x0a|baseAddr1);
w->writeC(write.addr&0xff);
w->writeC(write.val);
break;
case DIV_SYSTEM_OPL3:
case DIV_SYSTEM_OPL3_DRUMS:
switch (write.addr>>8) {
case 0: // port 0
w->writeC(0x0e|baseAddr1);
w->writeC(write.addr&0xff);
w->writeC(write.val);
break;
case 1: // port 1
w->writeC(0x0f|baseAddr1);
w->writeC(write.addr&0xff);
w->writeC(write.val);
break;
}
break;
default: default:
logW("write not handled!\n"); logW("write not handled!\n");
break; break;
@ -798,6 +835,42 @@ SafeWriter* DivEngine::saveVGM(bool* sysToExport, bool loop) {
howManyChips++; howManyChips++;
} }
break; break;
case DIV_SYSTEM_OPL:
case DIV_SYSTEM_OPL_DRUMS:
if (!hasOPL) {
hasOPL=disCont[i].dispatch->chipClock;
willExport[i]=true;
} else if (!(hasOPL&0x40000000)) {
isSecond[i]=true;
willExport[i]=true;
hasOPL|=0x40000000;
howManyChips++;
}
break;
case DIV_SYSTEM_OPL2:
case DIV_SYSTEM_OPL2_DRUMS:
if (!hasOPL2) {
hasOPL2=disCont[i].dispatch->chipClock;
willExport[i]=true;
} else if (!(hasOPL2&0x40000000)) {
isSecond[i]=true;
willExport[i]=true;
hasOPL2|=0x40000000;
howManyChips++;
}
break;
case DIV_SYSTEM_OPL3:
case DIV_SYSTEM_OPL3_DRUMS:
if (!hasOPL3) {
hasOPL3=disCont[i].dispatch->chipClock;
willExport[i]=true;
} else if (!(hasOPL3&0x40000000)) {
isSecond[i]=true;
willExport[i]=true;
hasOPL3|=0x40000000;
howManyChips++;
}
break;
default: default:
break; break;
} }