From cc152bc3d039cfdb1b09bb24cf51613e997f4950 Mon Sep 17 00:00:00 2001
From: tildearrow <tildearrow@protonmail.com>
Date: Wed, 30 Mar 2022 03:36:16 -0500
Subject: [PATCH] OPL: partially enable VGM export

it works except for fake reset
---
 src/engine/sysDef.cpp |  6 ++++
 src/engine/vgmOps.cpp | 73 +++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 79 insertions(+)

diff --git a/src/engine/sysDef.cpp b/src/engine/sysDef.cpp
index bcfbf1c6..dfcbb1fc 100644
--- a/src/engine/sysDef.cpp
+++ b/src/engine/sysDef.cpp
@@ -1695,6 +1695,12 @@ bool DivEngine::isVGMExportable(DivSystem which) {
     case DIV_SYSTEM_VRC7:
     case DIV_SYSTEM_X1_010:
     case DIV_SYSTEM_SWAN:
+    case DIV_SYSTEM_OPL:
+    case DIV_SYSTEM_OPL_DRUMS:
+    case DIV_SYSTEM_OPL2:
+    case DIV_SYSTEM_OPL2_DRUMS:
+    case DIV_SYSTEM_OPL3:
+    case DIV_SYSTEM_OPL3_DRUMS:
       return true;
     default:
       return false;
diff --git a/src/engine/vgmOps.cpp b/src/engine/vgmOps.cpp
index c2356dbc..4365b55a 100644
--- a/src/engine/vgmOps.cpp
+++ b/src/engine/vgmOps.cpp
@@ -317,6 +317,16 @@ void DivEngine::performVGMWrite(SafeWriter* w, DivSystem sys, DivRegWrite& write
           w->writeC(0xd6+i);
         }
         break;
+      // TODO: it's 3:35am
+      case DIV_SYSTEM_OPL:
+      case DIV_SYSTEM_OPL_DRUMS:
+        break;
+      case DIV_SYSTEM_OPL2:
+      case DIV_SYSTEM_OPL2_DRUMS:
+        break;
+      case DIV_SYSTEM_OPL3:
+      case DIV_SYSTEM_OPL3_DRUMS:
+        break;
       default:
         break;
     }
@@ -467,6 +477,33 @@ void DivEngine::performVGMWrite(SafeWriter* w, DivSystem sys, DivRegWrite& write
         w->writeC(write.val&0xff);
       }
       break;
+    case DIV_SYSTEM_OPL:
+    case DIV_SYSTEM_OPL_DRUMS:
+      w->writeC(0x0b|baseAddr1);
+      w->writeC(write.addr&0xff);
+      w->writeC(write.val);
+      break;
+    case DIV_SYSTEM_OPL2:
+    case DIV_SYSTEM_OPL2_DRUMS:
+      w->writeC(0x0a|baseAddr1);
+      w->writeC(write.addr&0xff);
+      w->writeC(write.val);
+      break;
+    case DIV_SYSTEM_OPL3:
+    case DIV_SYSTEM_OPL3_DRUMS:
+      switch (write.addr>>8) {
+        case 0: // port 0
+          w->writeC(0x0e|baseAddr1);
+          w->writeC(write.addr&0xff);
+          w->writeC(write.val);
+          break;
+        case 1: // port 1
+          w->writeC(0x0f|baseAddr1);
+          w->writeC(write.addr&0xff);
+          w->writeC(write.val);
+          break;
+      }
+      break;
     default:
       logW("write not handled!\n");
       break;
@@ -798,6 +835,42 @@ SafeWriter* DivEngine::saveVGM(bool* sysToExport, bool loop) {
           howManyChips++;
         }
         break;
+      case DIV_SYSTEM_OPL:
+      case DIV_SYSTEM_OPL_DRUMS:
+        if (!hasOPL) {
+          hasOPL=disCont[i].dispatch->chipClock;
+          willExport[i]=true;
+        } else if (!(hasOPL&0x40000000)) {
+          isSecond[i]=true;
+          willExport[i]=true;
+          hasOPL|=0x40000000;
+          howManyChips++;
+        }
+        break;
+      case DIV_SYSTEM_OPL2:
+      case DIV_SYSTEM_OPL2_DRUMS:
+        if (!hasOPL2) {
+          hasOPL2=disCont[i].dispatch->chipClock;
+          willExport[i]=true;
+        } else if (!(hasOPL2&0x40000000)) {
+          isSecond[i]=true;
+          willExport[i]=true;
+          hasOPL2|=0x40000000;
+          howManyChips++;
+        }
+        break;
+      case DIV_SYSTEM_OPL3:
+      case DIV_SYSTEM_OPL3_DRUMS:
+        if (!hasOPL3) {
+          hasOPL3=disCont[i].dispatch->chipClock;
+          willExport[i]=true;
+        } else if (!(hasOPL3&0x40000000)) {
+          isSecond[i]=true;
+          willExport[i]=true;
+          hasOPL3|=0x40000000;
+          howManyChips++;
+        }
+        break;
       default:
         break;
     }