dev167 - fix TL macro

previously, 127 mapped to TL 0
but now 127 maps to TL 127

yeah, the graph will look inverted I know...

src/engine/engine.h

@@ -56,8 +56,8 @@
 
 #define DIV_UNSTABLE
 
-#define DIV_VERSION "dev166"
+#define DIV_VERSION "dev167"
-#define DIV_ENGINE_VERSION 166
+#define DIV_ENGINE_VERSION 167
 // for imports
 #define DIV_VERSION_MOD 0xff01
 #define DIV_VERSION_FC 0xff02

src/engine/instrument.cpp

@@ -2261,6 +2261,13 @@ void DivInstrument::readFeatureOx(SafeReader& reader, int op, short version) {
         }
         break;
     }
+
+    // <167 TL macro compat
+    if (macroCode==6 && version<167) {
+      for (int i=0; i<target->len; i++) {
+        target->val[i]^=0x7f;
+      }
+    }
   }
 
   READ_FEAT_END;
@@ -3319,6 +3326,15 @@ DivDataErrors DivInstrument::readInsDataOld(SafeReader &reader, short version) {
     }
   }
 
+  // <167 TL macro compat
+  if (version<167) {
+    for (int i=0; i<4; i++) {
+      for (int j=0; j<std.opMacros[i].tlMacro.len; j++) {
+        std.opMacros[i].tlMacro.val[j]^=0x7f;
+      }
+    }
+  }
+
   return DIV_DATA_SUCCESS;
 }
 

src/engine/platform/arcade.cpp

@@ -299,7 +299,7 @@ void DivPlatformArcade::tick(bool sysTick) {
         rWrite(baseAddr+ADDR_SL_RR,(op.rr&15)|(op.sl<<4));
       }
       if (m.tl.had) {
-        op.tl=127-m.tl.val;
+        op.tl=m.tl.val;
         if (!op.enable) {
           rWrite(baseAddr+ADDR_TL,127);
         } else if (KVS(i,j)) {

src/engine/platform/genesis.cpp

@@ -473,7 +473,7 @@ void DivPlatformGenesis::tick(bool sysTick) {
         rWrite(baseAddr+ADDR_SL_RR,(op.rr&15)|(op.sl<<4));
       }
       if (m.tl.had) {
-        op.tl=127-m.tl.val;
+        op.tl=m.tl.val;
         if (isMuted[i] || !op.enable) {
           rWrite(baseAddr+ADDR_TL,127);
         } else {

src/engine/platform/genesisext.cpp

@@ -599,7 +599,7 @@ void DivPlatformGenesisExt::tick(bool sysTick) {
       rWrite(baseAddr+ADDR_SL_RR,(op.rr&15)|(op.sl<<4));
     }
     if (m.tl.had) {
-      op.tl=127-m.tl.val;
+      op.tl=m.tl.val;
       if (isOpMuted[i]) {
         rWrite(baseAddr+ADDR_TL,127);
       } else {

src/engine/platform/opl.cpp

@@ -436,7 +436,7 @@ void DivPlatformOPL::tick(bool sysTick) {
       }
 
       if (m.tl.had) {
-        op.tl=63-m.tl.val;
+        op.tl=m.tl.val&63;
       }
       if (m.ksl.had) {
         op.ksl=m.ksl.val;

src/engine/platform/opll.cpp

@@ -195,7 +195,7 @@ void DivPlatformOPLL::tick(bool sysTick) {
           rWrite(0x06+j,(op.sl<<4)|(op.rr));
         }
         if (m.tl.had) {
-          op.tl=((j==1)?15:63)-m.tl.val;
+          op.tl=m.tl.val&((j==1)?15:63);
           if (j==1) {
             if (i<9) {
               rWrite(0x30+i,((15-VOL_SCALE_LOG_BROKEN(chan[i].outVol,15-chan[i].state.op[1].tl,15))&15)|(chan[i].state.opllPreset<<4));

src/engine/platform/tx81z.cpp

@@ -262,7 +262,7 @@ void DivPlatformTX81Z::tick(bool sysTick) {
         rWrite(baseAddr+ADDR_SL_RR,(op.rr&15)|(op.sl<<4));
       }
       if (m.tl.had) {
-        op.tl=127-m.tl.val;
+        op.tl=m.tl.val;
         if (isMuted[i] || !op.enable) {
           rWrite(baseAddr+ADDR_TL,127);
         } else {

src/engine/platform/ym2203.cpp

@@ -402,7 +402,7 @@ void DivPlatformYM2203::tick(bool sysTick) {
         rWrite(baseAddr+ADDR_SL_RR,(op.rr&15)|(op.sl<<4));
       }
       if (m.tl.had) {
-        op.tl=127-m.tl.val;
+        op.tl=m.tl.val;
         if (isMuted[i] || !op.enable) {
           rWrite(baseAddr+ADDR_TL,127);
         } else {

src/engine/platform/ym2203ext.cpp

@@ -502,7 +502,7 @@ void DivPlatformYM2203Ext::tick(bool sysTick) {
       rWrite(baseAddr+ADDR_SL_RR,(op.rr&15)|(op.sl<<4));
     }
     if (m.tl.had) {
-      op.tl=127-m.tl.val;
+      op.tl=m.tl.val;
       if (isOpMuted[i]) {
         rWrite(baseAddr+ADDR_TL,127);
       } else {

src/engine/platform/ym2608.cpp

@@ -606,7 +606,7 @@ void DivPlatformYM2608::tick(bool sysTick) {
         rWrite(baseAddr+ADDR_SL_RR,(op.rr&15)|(op.sl<<4));
       }
       if (m.tl.had) {
-        op.tl=127-m.tl.val;
+        op.tl=m.tl.val;
         if (isMuted[i] || !op.enable) {
           rWrite(baseAddr+ADDR_TL,127);
         } else {

src/engine/platform/ym2608ext.cpp

@@ -549,7 +549,7 @@ void DivPlatformYM2608Ext::tick(bool sysTick) {
       rWrite(baseAddr+ADDR_SL_RR,(op.rr&15)|(op.sl<<4));
     }
     if (m.tl.had) {
-      op.tl=127-m.tl.val;
+      op.tl=m.tl.val;
       if (isOpMuted[i]) {
         rWrite(baseAddr+ADDR_TL,127);
       } else {

src/engine/platform/ym2610.cpp

@@ -539,7 +539,7 @@ void DivPlatformYM2610::tick(bool sysTick) {
         rWrite(baseAddr+ADDR_SL_RR,(op.rr&15)|(op.sl<<4));
       }
       if (m.tl.had) {
-        op.tl=127-m.tl.val;
+        op.tl=m.tl.val;
         if (isMuted[i] || !op.enable) {
           rWrite(baseAddr+ADDR_TL,127);
         } else {

src/engine/platform/ym2610b.cpp

@@ -606,7 +606,7 @@ void DivPlatformYM2610B::tick(bool sysTick) {
         rWrite(baseAddr+ADDR_SL_RR,(op.rr&15)|(op.sl<<4));
       }
       if (m.tl.had) {
-        op.tl=127-m.tl.val;
+        op.tl=m.tl.val;
         if (isMuted[i] || !op.enable) {
           rWrite(baseAddr+ADDR_TL,127);
         } else {

src/engine/platform/ym2610bext.cpp

@@ -544,7 +544,7 @@ void DivPlatformYM2610BExt::tick(bool sysTick) {
       rWrite(baseAddr+ADDR_SL_RR,(op.rr&15)|(op.sl<<4));
     }
     if (m.tl.had) {
-      op.tl=127-m.tl.val;
+      op.tl=m.tl.val;
       if (isOpMuted[i]) {
         rWrite(baseAddr+ADDR_TL,127);
       } else {

src/engine/platform/ym2610ext.cpp

@@ -544,7 +544,7 @@ void DivPlatformYM2610Ext::tick(bool sysTick) {
       rWrite(baseAddr+ADDR_SL_RR,(op.rr&15)|(op.sl<<4));
     }
     if (m.tl.had) {
-      op.tl=127-m.tl.val;
+      op.tl=m.tl.val;
       if (isOpMuted[i]) {
         rWrite(baseAddr+ADDR_TL,127);
       } else {