597 lines
18 KiB
C++
597 lines
18 KiB
C++
// Copyright 2018 yuzu Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#pragma once
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#include <bitset>
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#include <cstring>
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#include <map>
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#include <string>
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#include <vector>
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#include <boost/optional.hpp>
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#include "common/bit_field.h"
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#include "common/common_types.h"
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namespace Tegra {
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namespace Shader {
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struct Register {
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/// Number of registers
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static constexpr size_t NumRegisters = 256;
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/// Register 255 is special cased to always be 0
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static constexpr size_t ZeroIndex = 255;
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enum class Size : u64 {
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Byte = 0,
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Short = 1,
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Word = 2,
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Long = 3,
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};
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constexpr Register() = default;
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constexpr Register(u64 value) : value(value) {}
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constexpr operator u64() const {
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return value;
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}
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template <typename T>
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constexpr u64 operator-(const T& oth) const {
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return value - oth;
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}
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template <typename T>
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constexpr u64 operator&(const T& oth) const {
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return value & oth;
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}
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constexpr u64 operator&(const Register& oth) const {
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return value & oth.value;
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}
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constexpr u64 operator~() const {
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return ~value;
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}
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u64 GetSwizzledIndex(u64 elem) const {
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elem = (value + elem) & 3;
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return (value & ~3) + elem;
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}
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private:
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u64 value{};
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};
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union Attribute {
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Attribute() = default;
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constexpr explicit Attribute(u64 value) : value(value) {}
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enum class Index : u64 {
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Position = 7,
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Attribute_0 = 8,
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// This attribute contains a tuple of (~, ~, InstanceId, VertexId) when inside a vertex
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// shader, and a tuple of (TessCoord.x, TessCoord.y, TessCoord.z, ~) when inside a Tess Eval
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// shader.
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TessCoordInstanceIDVertexID = 47,
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};
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union {
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BitField<22, 2, u64> element;
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BitField<24, 6, Index> index;
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BitField<47, 3, u64> size;
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} fmt20;
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union {
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BitField<30, 2, u64> element;
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BitField<32, 6, Index> index;
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} fmt28;
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BitField<39, 8, u64> reg;
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u64 value{};
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};
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union Sampler {
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Sampler() = default;
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constexpr explicit Sampler(u64 value) : value(value) {}
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enum class Index : u64 {
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Sampler_0 = 8,
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};
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BitField<36, 13, Index> index;
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u64 value{};
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};
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union Uniform {
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BitField<20, 14, u64> offset;
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BitField<34, 5, u64> index;
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};
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} // namespace Shader
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} // namespace Tegra
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namespace std {
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// TODO(bunnei): The below is forbidden by the C++ standard, but works fine. See #330.
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template <>
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struct make_unsigned<Tegra::Shader::Attribute> {
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using type = Tegra::Shader::Attribute;
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};
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template <>
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struct make_unsigned<Tegra::Shader::Register> {
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using type = Tegra::Shader::Register;
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};
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} // namespace std
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namespace Tegra {
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namespace Shader {
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enum class Pred : u64 {
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UnusedIndex = 0x7,
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NeverExecute = 0xF,
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};
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enum class PredCondition : u64 {
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LessThan = 1,
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Equal = 2,
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LessEqual = 3,
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GreaterThan = 4,
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NotEqual = 5,
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GreaterEqual = 6,
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// TODO(Subv): Other condition types
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};
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enum class PredOperation : u64 {
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And = 0,
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Or = 1,
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Xor = 2,
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};
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enum class LogicOperation : u64 {
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And = 0,
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Or = 1,
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Xor = 2,
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PassB = 3,
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};
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enum class SubOp : u64 {
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Cos = 0x0,
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Sin = 0x1,
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Ex2 = 0x2,
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Lg2 = 0x3,
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Rcp = 0x4,
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Rsq = 0x5,
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Min = 0x8,
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};
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enum class FloatRoundingOp : u64 {
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None = 0,
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Floor = 1,
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Ceil = 2,
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Trunc = 3,
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};
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union Instruction {
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Instruction& operator=(const Instruction& instr) {
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value = instr.value;
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return *this;
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}
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constexpr Instruction(u64 value) : value{value} {}
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BitField<0, 8, Register> gpr0;
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BitField<8, 8, Register> gpr8;
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union {
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BitField<16, 4, Pred> full_pred;
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BitField<16, 3, u64> pred_index;
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} pred;
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BitField<19, 1, u64> negate_pred;
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BitField<20, 8, Register> gpr20;
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BitField<20, 7, SubOp> sub_op;
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BitField<28, 8, Register> gpr28;
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BitField<39, 8, Register> gpr39;
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BitField<48, 16, u64> opcode;
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union {
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BitField<20, 19, u64> imm20_19;
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BitField<20, 32, u64> imm20_32;
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BitField<45, 1, u64> negate_b;
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BitField<46, 1, u64> abs_a;
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BitField<48, 1, u64> negate_a;
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BitField<49, 1, u64> abs_b;
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BitField<50, 1, u64> abs_d;
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BitField<56, 1, u64> negate_imm;
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union {
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BitField<39, 3, u64> pred;
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BitField<42, 1, u64> negate_pred;
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} fmnmx;
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union {
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BitField<53, 2, LogicOperation> operation;
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BitField<55, 1, u64> invert_a;
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BitField<56, 1, u64> invert_b;
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} lop;
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float GetImm20_19() const {
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float result{};
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u32 imm{static_cast<u32>(imm20_19)};
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imm <<= 12;
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imm |= negate_imm ? 0x80000000 : 0;
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std::memcpy(&result, &imm, sizeof(imm));
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return result;
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}
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float GetImm20_32() const {
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float result{};
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u32 imm{static_cast<u32>(imm20_32)};
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std::memcpy(&result, &imm, sizeof(imm));
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return result;
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}
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} alu;
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union {
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BitField<48, 1, u64> negate_b;
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BitField<49, 1, u64> negate_c;
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} ffma;
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union {
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BitField<0, 3, u64> pred0;
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BitField<3, 3, u64> pred3;
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BitField<7, 1, u64> abs_a;
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BitField<39, 3, u64> pred39;
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BitField<42, 1, u64> neg_pred;
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BitField<43, 1, u64> neg_a;
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BitField<44, 1, u64> abs_b;
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BitField<45, 2, PredOperation> op;
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BitField<47, 1, u64> ftz;
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BitField<48, 4, PredCondition> cond;
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BitField<56, 1, u64> neg_b;
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} fsetp;
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union {
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BitField<0, 3, u64> pred0;
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BitField<3, 3, u64> pred3;
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BitField<39, 3, u64> pred39;
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BitField<42, 1, u64> neg_pred;
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BitField<45, 2, PredOperation> op;
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BitField<48, 1, u64> is_signed;
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BitField<49, 3, PredCondition> cond;
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} isetp;
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union {
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BitField<39, 3, u64> pred39;
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BitField<42, 1, u64> neg_pred;
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BitField<43, 1, u64> neg_a;
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BitField<44, 1, u64> abs_b;
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BitField<45, 2, PredOperation> op;
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BitField<48, 4, PredCondition> cond;
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BitField<52, 1, u64> bf;
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BitField<53, 1, u64> neg_b;
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BitField<54, 1, u64> abs_a;
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BitField<55, 1, u64> ftz;
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BitField<56, 1, u64> neg_imm;
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} fset;
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union {
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BitField<10, 2, Register::Size> size;
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BitField<12, 1, u64> is_output_signed;
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BitField<13, 1, u64> is_input_signed;
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BitField<41, 2, u64> selector;
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BitField<45, 1, u64> negate_a;
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BitField<49, 1, u64> abs_a;
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BitField<50, 1, u64> saturate_a;
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union {
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BitField<39, 2, FloatRoundingOp> rounding;
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} f2i;
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union {
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BitField<39, 4, u64> rounding;
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} f2f;
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} conversion;
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union {
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BitField<31, 4, u64> component_mask;
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bool IsComponentEnabled(size_t component) const {
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return ((1 << component) & component_mask) != 0;
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}
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} tex;
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union {
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BitField<50, 3, u64> component_mask_selector;
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BitField<28, 8, Register> gpr28;
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bool HasTwoDestinations() const {
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return gpr28.Value() != Register::ZeroIndex;
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}
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bool IsComponentEnabled(size_t component) const {
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static constexpr std::array<size_t, 5> one_dest_mask{0x1, 0x2, 0x4, 0x8, 0x3};
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static constexpr std::array<size_t, 5> two_dest_mask{0x7, 0xb, 0xd, 0xe, 0xf};
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const auto& mask{HasTwoDestinations() ? two_dest_mask : one_dest_mask};
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ASSERT(component_mask_selector < mask.size());
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return ((1 << component) & mask[component_mask_selector]) != 0;
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}
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} texs;
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union {
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BitField<20, 5, u64> target;
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BitField<5, 1, u64> constant_buffer;
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s32 GetBranchTarget() const {
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// Sign extend the branch target offset
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u32 mask = 1U << (5 - 1);
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u32 value = static_cast<u32>(target);
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// The branch offset is relative to the next instruction, so add 1 to it.
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return static_cast<s32>((value ^ mask) - mask) + 1;
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}
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} bra;
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BitField<61, 1, u64> is_b_imm;
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BitField<60, 1, u64> is_b_gpr;
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BitField<59, 1, u64> is_c_gpr;
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Attribute attribute;
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Uniform uniform;
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Sampler sampler;
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u64 value;
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};
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static_assert(sizeof(Instruction) == 0x8, "Incorrect structure size");
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static_assert(std::is_standard_layout<Instruction>::value,
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"Structure does not have standard layout");
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class OpCode {
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public:
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enum class Id {
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KIL,
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BRA,
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LD_A,
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ST_A,
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TEX,
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TEXQ, // Texture Query
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TEXS, // Texture Fetch with scalar/non-vec4 source/destinations
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TLDS, // Texture Load with scalar/non-vec4 source/destinations
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EXIT,
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IPA,
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FFMA_IMM, // Fused Multiply and Add
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FFMA_CR,
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FFMA_RC,
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FFMA_RR,
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FADD_C,
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FADD_R,
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FADD_IMM,
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FMUL_C,
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FMUL_R,
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FMUL_IMM,
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FMUL32_IMM,
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MUFU, // Multi-Function Operator
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RRO_C, // Range Reduction Operator
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RRO_R,
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RRO_IMM,
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F2F_C,
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F2F_R,
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F2F_IMM,
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F2I_C,
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F2I_R,
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F2I_IMM,
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I2F_C,
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I2F_R,
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I2F_IMM,
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I2I_C,
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I2I_R,
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I2I_IMM,
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LOP32I,
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MOV_C,
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MOV_R,
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MOV_IMM,
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MOV32_IMM,
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SHR_C,
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SHR_R,
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SHR_IMM,
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FMNMX_C,
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FMNMX_R,
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FMNMX_IMM,
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FSETP_C, // Set Predicate
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FSETP_R,
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FSETP_IMM,
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FSET_C,
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FSET_R,
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FSET_IMM,
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ISETP_C,
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ISETP_IMM,
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ISETP_R,
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PSETP,
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};
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enum class Type {
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Trivial,
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Arithmetic,
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Logic,
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Ffma,
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Flow,
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Memory,
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FloatSet,
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FloatSetPredicate,
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IntegerSetPredicate,
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PredicateSetPredicate,
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Conversion,
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Unknown,
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};
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class Matcher {
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public:
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Matcher(const char* const name, u16 mask, u16 expected, OpCode::Id id, OpCode::Type type)
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: name{name}, mask{mask}, expected{expected}, id{id}, type{type} {}
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const char* GetName() const {
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return name;
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}
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u16 GetMask() const {
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return mask;
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}
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Id GetId() const {
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return id;
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}
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Type GetType() const {
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return type;
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}
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/**
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* Tests to see if the given instruction is the instruction this matcher represents.
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* @param instruction The instruction to test
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* @returns true if the given instruction matches.
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*/
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bool Matches(u16 instruction) const {
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return (instruction & mask) == expected;
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}
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private:
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const char* name;
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u16 mask;
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u16 expected;
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Id id;
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Type type;
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};
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static boost::optional<const Matcher&> Decode(Instruction instr) {
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static const auto table{GetDecodeTable()};
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const auto matches_instruction = [instr](const auto& matcher) {
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return matcher.Matches(static_cast<u16>(instr.opcode));
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};
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auto iter = std::find_if(table.begin(), table.end(), matches_instruction);
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return iter != table.end() ? boost::optional<const Matcher&>(*iter) : boost::none;
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}
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private:
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struct Detail {
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private:
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static constexpr size_t opcode_bitsize = 16;
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/**
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* Generates the mask and the expected value after masking from a given bitstring.
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* A '0' in a bitstring indicates that a zero must be present at that bit position.
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* A '1' in a bitstring indicates that a one must be present at that bit position.
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*/
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static auto GetMaskAndExpect(const char* const bitstring) {
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u16 mask = 0, expect = 0;
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for (size_t i = 0; i < opcode_bitsize; i++) {
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const size_t bit_position = opcode_bitsize - i - 1;
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switch (bitstring[i]) {
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case '0':
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mask |= 1 << bit_position;
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break;
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case '1':
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expect |= 1 << bit_position;
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mask |= 1 << bit_position;
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break;
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default:
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// Ignore
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break;
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}
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}
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return std::make_tuple(mask, expect);
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}
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public:
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/// Creates a matcher that can match and parse instructions based on bitstring.
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static auto GetMatcher(const char* const bitstring, OpCode::Id op, OpCode::Type type,
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const char* const name) {
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const auto mask_expect = GetMaskAndExpect(bitstring);
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return Matcher(name, std::get<0>(mask_expect), std::get<1>(mask_expect), op, type);
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}
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};
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static std::vector<Matcher> GetDecodeTable() {
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std::vector<Matcher> table = {
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#define INST(bitstring, op, type, name) Detail::GetMatcher(bitstring, op, type, name)
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INST("111000110011----", Id::KIL, Type::Flow, "KIL"),
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INST("111000100100----", Id::BRA, Type::Flow, "BRA"),
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INST("1110111111011---", Id::LD_A, Type::Memory, "LD_A"),
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INST("1110111111110---", Id::ST_A, Type::Memory, "ST_A"),
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INST("1100000000111---", Id::TEX, Type::Memory, "TEX"),
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INST("1101111101001---", Id::TEXQ, Type::Memory, "TEXQ"),
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INST("1101100---------", Id::TEXS, Type::Memory, "TEXS"),
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INST("1101101---------", Id::TLDS, Type::Memory, "TLDS"),
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INST("111000110000----", Id::EXIT, Type::Trivial, "EXIT"),
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INST("11100000--------", Id::IPA, Type::Trivial, "IPA"),
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INST("001100101-------", Id::FFMA_IMM, Type::Ffma, "FFMA_IMM"),
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INST("010010011-------", Id::FFMA_CR, Type::Ffma, "FFMA_CR"),
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INST("010100011-------", Id::FFMA_RC, Type::Ffma, "FFMA_RC"),
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INST("010110011-------", Id::FFMA_RR, Type::Ffma, "FFMA_RR"),
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INST("0100110001011---", Id::FADD_C, Type::Arithmetic, "FADD_C"),
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INST("0101110001011---", Id::FADD_R, Type::Arithmetic, "FADD_R"),
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INST("0011100-01011---", Id::FADD_IMM, Type::Arithmetic, "FADD_IMM"),
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INST("0100110001101---", Id::FMUL_C, Type::Arithmetic, "FMUL_C"),
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INST("0101110001101---", Id::FMUL_R, Type::Arithmetic, "FMUL_R"),
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INST("0011100-01101---", Id::FMUL_IMM, Type::Arithmetic, "FMUL_IMM"),
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INST("00011110--------", Id::FMUL32_IMM, Type::Arithmetic, "FMUL32_IMM"),
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INST("0101000010000---", Id::MUFU, Type::Arithmetic, "MUFU"),
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INST("0100110010010---", Id::RRO_C, Type::Arithmetic, "RRO_C"),
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INST("0101110010010---", Id::RRO_R, Type::Arithmetic, "RRO_R"),
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INST("0011100-10010---", Id::RRO_IMM, Type::Arithmetic, "RRO_IMM"),
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INST("0100110010101---", Id::F2F_C, Type::Conversion, "F2F_C"),
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INST("0101110010101---", Id::F2F_R, Type::Conversion, "F2F_R"),
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INST("0011100-10101---", Id::F2F_IMM, Type::Conversion, "F2F_IMM"),
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INST("0100110010110---", Id::F2I_C, Type::Conversion, "F2I_C"),
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INST("0101110010110---", Id::F2I_R, Type::Conversion, "F2I_R"),
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INST("0011100-10110---", Id::F2I_IMM, Type::Conversion, "F2I_IMM"),
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INST("0100110010011---", Id::MOV_C, Type::Arithmetic, "MOV_C"),
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INST("0101110010011---", Id::MOV_R, Type::Arithmetic, "MOV_R"),
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INST("0011100-10011---", Id::MOV_IMM, Type::Arithmetic, "MOV_IMM"),
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INST("000000010000----", Id::MOV32_IMM, Type::Arithmetic, "MOV32_IMM"),
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|
INST("0100110000101---", Id::SHR_C, Type::Arithmetic, "SHR_C"),
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INST("0101110000101---", Id::SHR_R, Type::Arithmetic, "SHR_R"),
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|
INST("0011100-00101---", Id::SHR_IMM, Type::Arithmetic, "SHR_IMM"),
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|
INST("0100110001100---", Id::FMNMX_C, Type::Arithmetic, "FMNMX_C"),
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|
INST("0101110001100---", Id::FMNMX_R, Type::Arithmetic, "FMNMX_R"),
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|
INST("0011100-01100---", Id::FMNMX_IMM, Type::Arithmetic, "FMNMX_IMM"),
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|
INST("000001----------", Id::LOP32I, Type::Logic, "LOP32I"),
|
|
INST("0100110011100---", Id::I2I_C, Type::Conversion, "I2I_C"),
|
|
INST("0101110011100---", Id::I2I_R, Type::Conversion, "I2I_R"),
|
|
INST("01110001-1000---", Id::I2I_IMM, Type::Conversion, "I2I_IMM"),
|
|
INST("0100110010111---", Id::I2F_C, Type::Conversion, "I2F_C"),
|
|
INST("0101110010111---", Id::I2F_R, Type::Conversion, "I2F_R"),
|
|
INST("0011100-10111---", Id::I2F_IMM, Type::Conversion, "I2F_IMM"),
|
|
INST("01011000--------", Id::FSET_R, Type::FloatSet, "FSET_R"),
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|
INST("0100100---------", Id::FSET_C, Type::FloatSet, "FSET_C"),
|
|
INST("0011000---------", Id::FSET_IMM, Type::FloatSet, "FSET_IMM"),
|
|
INST("010010111011----", Id::FSETP_C, Type::FloatSetPredicate, "FSETP_C"),
|
|
INST("010110111011----", Id::FSETP_R, Type::FloatSetPredicate, "FSETP_R"),
|
|
INST("0011011-1011----", Id::FSETP_IMM, Type::FloatSetPredicate, "FSETP_IMM"),
|
|
INST("010010110110----", Id::ISETP_C, Type::IntegerSetPredicate, "ISETP_C"),
|
|
INST("010110110110----", Id::ISETP_R, Type::IntegerSetPredicate, "ISETP_R"),
|
|
INST("0011011-0110----", Id::ISETP_IMM, Type::IntegerSetPredicate, "ISETP_IMM"),
|
|
INST("0101000010010---", Id::PSETP, Type::PredicateSetPredicate, "PSETP"),
|
|
};
|
|
#undef INST
|
|
std::stable_sort(table.begin(), table.end(), [](const auto& a, const auto& b) {
|
|
// If a matcher has more bits in its mask it is more specific, so it
|
|
// should come first.
|
|
return std::bitset<16>(a.GetMask()).count() > std::bitset<16>(b.GetMask()).count();
|
|
});
|
|
|
|
return table;
|
|
}
|
|
};
|
|
|
|
} // namespace Shader
|
|
} // namespace Tegra
|