mirror of
https://github.com/tildearrow/furnace.git
synced 2024-11-18 02:25:11 +00:00
390 lines
12 KiB
C
390 lines
12 KiB
C
/*
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* Copyright (c) 2003, 2007-14 Matteo Frigo
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* Copyright (c) 2003, 2007-14 Massachusetts Institute of Technology
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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*
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*/
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/* This file was automatically generated --- DO NOT EDIT */
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/* Generated on Tue Sep 14 10:45:58 EDT 2021 */
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#include "dft/codelet-dft.h"
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#if defined(ARCH_PREFERS_FMA) || defined(ISA_EXTENSION_PREFERS_FMA)
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/* Generated by: ../../../genfft/gen_twiddle.native -fma -simd -compact -variables 4 -pipeline-latency 8 -n 8 -name t1sv_8 -include dft/simd/ts.h */
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/*
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* This function contains 66 FP additions, 36 FP multiplications,
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* (or, 44 additions, 14 multiplications, 22 fused multiply/add),
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* 34 stack variables, 1 constants, and 32 memory accesses
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*/
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#include "dft/simd/ts.h"
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static void t1sv_8(R *ri, R *ii, const R *W, stride rs, INT mb, INT me, INT ms)
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{
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DVK(KP707106781, +0.707106781186547524400844362104849039284835938);
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{
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INT m;
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for (m = mb, W = W + (mb * 14); m < me; m = m + (2 * VL), ri = ri + ((2 * VL) * ms), ii = ii + ((2 * VL) * ms), W = W + ((2 * VL) * 14), MAKE_VOLATILE_STRIDE(16, rs)) {
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V T1, T1m, T7, T1l, Tk, TS, Te, TQ, TF, T14, TL, T16, T12, T17, Ts;
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V TX, Ty, TZ, TV, T10;
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T1 = LD(&(ri[0]), ms, &(ri[0]));
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T1m = LD(&(ii[0]), ms, &(ii[0]));
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{
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V T3, T6, T4, T1k, T2, T5;
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T3 = LD(&(ri[WS(rs, 4)]), ms, &(ri[0]));
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T6 = LD(&(ii[WS(rs, 4)]), ms, &(ii[0]));
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T2 = LDW(&(W[TWVL * 6]));
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T4 = VMUL(T2, T3);
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T1k = VMUL(T2, T6);
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T5 = LDW(&(W[TWVL * 7]));
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T7 = VFMA(T5, T6, T4);
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T1l = VFNMS(T5, T3, T1k);
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}
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{
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V Tg, Tj, Th, TR, Tf, Ti;
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Tg = LD(&(ri[WS(rs, 6)]), ms, &(ri[0]));
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Tj = LD(&(ii[WS(rs, 6)]), ms, &(ii[0]));
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Tf = LDW(&(W[TWVL * 10]));
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Th = VMUL(Tf, Tg);
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TR = VMUL(Tf, Tj);
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Ti = LDW(&(W[TWVL * 11]));
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Tk = VFMA(Ti, Tj, Th);
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TS = VFNMS(Ti, Tg, TR);
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}
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{
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V Ta, Td, Tb, TP, T9, Tc;
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Ta = LD(&(ri[WS(rs, 2)]), ms, &(ri[0]));
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Td = LD(&(ii[WS(rs, 2)]), ms, &(ii[0]));
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T9 = LDW(&(W[TWVL * 2]));
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Tb = VMUL(T9, Ta);
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TP = VMUL(T9, Td);
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Tc = LDW(&(W[TWVL * 3]));
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Te = VFMA(Tc, Td, Tb);
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TQ = VFNMS(Tc, Ta, TP);
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}
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{
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V TB, TE, TC, T13, TH, TK, TI, T15, TA, TG, TD, TJ;
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TB = LD(&(ri[WS(rs, 7)]), ms, &(ri[WS(rs, 1)]));
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TE = LD(&(ii[WS(rs, 7)]), ms, &(ii[WS(rs, 1)]));
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TA = LDW(&(W[TWVL * 12]));
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TC = VMUL(TA, TB);
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T13 = VMUL(TA, TE);
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TH = LD(&(ri[WS(rs, 3)]), ms, &(ri[WS(rs, 1)]));
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TK = LD(&(ii[WS(rs, 3)]), ms, &(ii[WS(rs, 1)]));
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TG = LDW(&(W[TWVL * 4]));
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TI = VMUL(TG, TH);
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T15 = VMUL(TG, TK);
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TD = LDW(&(W[TWVL * 13]));
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TF = VFMA(TD, TE, TC);
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T14 = VFNMS(TD, TB, T13);
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TJ = LDW(&(W[TWVL * 5]));
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TL = VFMA(TJ, TK, TI);
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T16 = VFNMS(TJ, TH, T15);
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T12 = VSUB(TF, TL);
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T17 = VSUB(T14, T16);
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}
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{
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V To, Tr, Tp, TW, Tu, Tx, Tv, TY, Tn, Tt, Tq, Tw;
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To = LD(&(ri[WS(rs, 1)]), ms, &(ri[WS(rs, 1)]));
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Tr = LD(&(ii[WS(rs, 1)]), ms, &(ii[WS(rs, 1)]));
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Tn = LDW(&(W[0]));
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Tp = VMUL(Tn, To);
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TW = VMUL(Tn, Tr);
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Tu = LD(&(ri[WS(rs, 5)]), ms, &(ri[WS(rs, 1)]));
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Tx = LD(&(ii[WS(rs, 5)]), ms, &(ii[WS(rs, 1)]));
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Tt = LDW(&(W[TWVL * 8]));
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Tv = VMUL(Tt, Tu);
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TY = VMUL(Tt, Tx);
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Tq = LDW(&(W[TWVL * 1]));
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Ts = VFMA(Tq, Tr, Tp);
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TX = VFNMS(Tq, To, TW);
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Tw = LDW(&(W[TWVL * 9]));
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Ty = VFMA(Tw, Tx, Tv);
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TZ = VFNMS(Tw, Tu, TY);
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TV = VSUB(Ts, Ty);
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T10 = VSUB(TX, TZ);
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}
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{
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V TU, T1a, T1t, T1v, T19, T1w, T1d, T1u;
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{
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V TO, TT, T1r, T1s;
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TO = VSUB(T1, T7);
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TT = VSUB(TQ, TS);
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TU = VADD(TO, TT);
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T1a = VSUB(TO, TT);
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T1r = VSUB(T1m, T1l);
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T1s = VSUB(Te, Tk);
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T1t = VSUB(T1r, T1s);
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T1v = VADD(T1s, T1r);
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}
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{
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V T11, T18, T1b, T1c;
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T11 = VADD(TV, T10);
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T18 = VSUB(T12, T17);
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T19 = VADD(T11, T18);
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T1w = VSUB(T18, T11);
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T1b = VSUB(T10, TV);
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T1c = VADD(T12, T17);
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T1d = VSUB(T1b, T1c);
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T1u = VADD(T1b, T1c);
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}
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ST(&(ri[WS(rs, 5)]), VFNMS(LDK(KP707106781), T19, TU), ms, &(ri[WS(rs, 1)]));
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ST(&(ii[WS(rs, 5)]), VFNMS(LDK(KP707106781), T1u, T1t), ms, &(ii[WS(rs, 1)]));
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ST(&(ri[WS(rs, 1)]), VFMA(LDK(KP707106781), T19, TU), ms, &(ri[WS(rs, 1)]));
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ST(&(ii[WS(rs, 1)]), VFMA(LDK(KP707106781), T1u, T1t), ms, &(ii[WS(rs, 1)]));
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ST(&(ri[WS(rs, 7)]), VFNMS(LDK(KP707106781), T1d, T1a), ms, &(ri[WS(rs, 1)]));
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ST(&(ii[WS(rs, 7)]), VFNMS(LDK(KP707106781), T1w, T1v), ms, &(ii[WS(rs, 1)]));
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ST(&(ri[WS(rs, 3)]), VFMA(LDK(KP707106781), T1d, T1a), ms, &(ri[WS(rs, 1)]));
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ST(&(ii[WS(rs, 3)]), VFMA(LDK(KP707106781), T1w, T1v), ms, &(ii[WS(rs, 1)]));
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}
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{
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V Tm, T1e, T1o, T1q, TN, T1p, T1h, T1i;
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{
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V T8, Tl, T1j, T1n;
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T8 = VADD(T1, T7);
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Tl = VADD(Te, Tk);
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Tm = VADD(T8, Tl);
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T1e = VSUB(T8, Tl);
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T1j = VADD(TQ, TS);
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T1n = VADD(T1l, T1m);
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T1o = VADD(T1j, T1n);
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T1q = VSUB(T1n, T1j);
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}
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{
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V Tz, TM, T1f, T1g;
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Tz = VADD(Ts, Ty);
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TM = VADD(TF, TL);
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TN = VADD(Tz, TM);
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T1p = VSUB(TM, Tz);
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T1f = VADD(TX, TZ);
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T1g = VADD(T14, T16);
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T1h = VSUB(T1f, T1g);
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T1i = VADD(T1f, T1g);
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}
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ST(&(ri[WS(rs, 4)]), VSUB(Tm, TN), ms, &(ri[0]));
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ST(&(ii[WS(rs, 4)]), VSUB(T1o, T1i), ms, &(ii[0]));
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ST(&(ri[0]), VADD(Tm, TN), ms, &(ri[0]));
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ST(&(ii[0]), VADD(T1i, T1o), ms, &(ii[0]));
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ST(&(ri[WS(rs, 6)]), VSUB(T1e, T1h), ms, &(ri[0]));
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ST(&(ii[WS(rs, 6)]), VSUB(T1q, T1p), ms, &(ii[0]));
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ST(&(ri[WS(rs, 2)]), VADD(T1e, T1h), ms, &(ri[0]));
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ST(&(ii[WS(rs, 2)]), VADD(T1p, T1q), ms, &(ii[0]));
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}
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}
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}
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VLEAVE();
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}
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static const tw_instr twinstr[] = {
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VTW(0, 1),
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VTW(0, 2),
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VTW(0, 3),
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VTW(0, 4),
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VTW(0, 5),
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VTW(0, 6),
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VTW(0, 7),
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{ TW_NEXT, (2 * VL), 0 }
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};
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static const ct_desc desc = { 8, XSIMD_STRING("t1sv_8"), twinstr, &GENUS, { 44, 14, 22, 0 }, 0, 0, 0 };
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void XSIMD(codelet_t1sv_8) (planner *p) {
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X(kdft_dit_register) (p, t1sv_8, &desc);
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}
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#else
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/* Generated by: ../../../genfft/gen_twiddle.native -simd -compact -variables 4 -pipeline-latency 8 -n 8 -name t1sv_8 -include dft/simd/ts.h */
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/*
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* This function contains 66 FP additions, 32 FP multiplications,
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* (or, 52 additions, 18 multiplications, 14 fused multiply/add),
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* 28 stack variables, 1 constants, and 32 memory accesses
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*/
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#include "dft/simd/ts.h"
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static void t1sv_8(R *ri, R *ii, const R *W, stride rs, INT mb, INT me, INT ms)
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{
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DVK(KP707106781, +0.707106781186547524400844362104849039284835938);
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{
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INT m;
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for (m = mb, W = W + (mb * 14); m < me; m = m + (2 * VL), ri = ri + ((2 * VL) * ms), ii = ii + ((2 * VL) * ms), W = W + ((2 * VL) * 14), MAKE_VOLATILE_STRIDE(16, rs)) {
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V T7, T1e, TH, T19, TF, T13, TR, TU, Ti, T1f, TK, T16, Tu, T12, TM;
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V TP;
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{
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V T1, T18, T6, T17;
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T1 = LD(&(ri[0]), ms, &(ri[0]));
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T18 = LD(&(ii[0]), ms, &(ii[0]));
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{
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V T3, T5, T2, T4;
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T3 = LD(&(ri[WS(rs, 4)]), ms, &(ri[0]));
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T5 = LD(&(ii[WS(rs, 4)]), ms, &(ii[0]));
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T2 = LDW(&(W[TWVL * 6]));
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T4 = LDW(&(W[TWVL * 7]));
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T6 = VFMA(T2, T3, VMUL(T4, T5));
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T17 = VFNMS(T4, T3, VMUL(T2, T5));
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}
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T7 = VADD(T1, T6);
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T1e = VSUB(T18, T17);
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TH = VSUB(T1, T6);
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T19 = VADD(T17, T18);
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}
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{
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V Tz, TS, TE, TT;
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{
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V Tw, Ty, Tv, Tx;
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Tw = LD(&(ri[WS(rs, 7)]), ms, &(ri[WS(rs, 1)]));
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Ty = LD(&(ii[WS(rs, 7)]), ms, &(ii[WS(rs, 1)]));
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Tv = LDW(&(W[TWVL * 12]));
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Tx = LDW(&(W[TWVL * 13]));
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Tz = VFMA(Tv, Tw, VMUL(Tx, Ty));
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TS = VFNMS(Tx, Tw, VMUL(Tv, Ty));
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}
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{
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V TB, TD, TA, TC;
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TB = LD(&(ri[WS(rs, 3)]), ms, &(ri[WS(rs, 1)]));
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TD = LD(&(ii[WS(rs, 3)]), ms, &(ii[WS(rs, 1)]));
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TA = LDW(&(W[TWVL * 4]));
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TC = LDW(&(W[TWVL * 5]));
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TE = VFMA(TA, TB, VMUL(TC, TD));
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TT = VFNMS(TC, TB, VMUL(TA, TD));
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}
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TF = VADD(Tz, TE);
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T13 = VADD(TS, TT);
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TR = VSUB(Tz, TE);
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TU = VSUB(TS, TT);
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}
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{
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V Tc, TI, Th, TJ;
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{
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V T9, Tb, T8, Ta;
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T9 = LD(&(ri[WS(rs, 2)]), ms, &(ri[0]));
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Tb = LD(&(ii[WS(rs, 2)]), ms, &(ii[0]));
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T8 = LDW(&(W[TWVL * 2]));
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Ta = LDW(&(W[TWVL * 3]));
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Tc = VFMA(T8, T9, VMUL(Ta, Tb));
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TI = VFNMS(Ta, T9, VMUL(T8, Tb));
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}
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{
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V Te, Tg, Td, Tf;
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Te = LD(&(ri[WS(rs, 6)]), ms, &(ri[0]));
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Tg = LD(&(ii[WS(rs, 6)]), ms, &(ii[0]));
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Td = LDW(&(W[TWVL * 10]));
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Tf = LDW(&(W[TWVL * 11]));
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Th = VFMA(Td, Te, VMUL(Tf, Tg));
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TJ = VFNMS(Tf, Te, VMUL(Td, Tg));
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}
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Ti = VADD(Tc, Th);
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T1f = VSUB(Tc, Th);
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TK = VSUB(TI, TJ);
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T16 = VADD(TI, TJ);
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}
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{
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V To, TN, Tt, TO;
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{
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V Tl, Tn, Tk, Tm;
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Tl = LD(&(ri[WS(rs, 1)]), ms, &(ri[WS(rs, 1)]));
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Tn = LD(&(ii[WS(rs, 1)]), ms, &(ii[WS(rs, 1)]));
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Tk = LDW(&(W[0]));
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Tm = LDW(&(W[TWVL * 1]));
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To = VFMA(Tk, Tl, VMUL(Tm, Tn));
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TN = VFNMS(Tm, Tl, VMUL(Tk, Tn));
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}
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{
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V Tq, Ts, Tp, Tr;
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Tq = LD(&(ri[WS(rs, 5)]), ms, &(ri[WS(rs, 1)]));
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Ts = LD(&(ii[WS(rs, 5)]), ms, &(ii[WS(rs, 1)]));
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Tp = LDW(&(W[TWVL * 8]));
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Tr = LDW(&(W[TWVL * 9]));
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Tt = VFMA(Tp, Tq, VMUL(Tr, Ts));
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TO = VFNMS(Tr, Tq, VMUL(Tp, Ts));
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}
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Tu = VADD(To, Tt);
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T12 = VADD(TN, TO);
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TM = VSUB(To, Tt);
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TP = VSUB(TN, TO);
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}
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{
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V Tj, TG, T1b, T1c;
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Tj = VADD(T7, Ti);
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TG = VADD(Tu, TF);
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ST(&(ri[WS(rs, 4)]), VSUB(Tj, TG), ms, &(ri[0]));
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ST(&(ri[0]), VADD(Tj, TG), ms, &(ri[0]));
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{
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V T15, T1a, T11, T14;
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T15 = VADD(T12, T13);
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T1a = VADD(T16, T19);
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ST(&(ii[0]), VADD(T15, T1a), ms, &(ii[0]));
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ST(&(ii[WS(rs, 4)]), VSUB(T1a, T15), ms, &(ii[0]));
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T11 = VSUB(T7, Ti);
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T14 = VSUB(T12, T13);
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ST(&(ri[WS(rs, 6)]), VSUB(T11, T14), ms, &(ri[0]));
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ST(&(ri[WS(rs, 2)]), VADD(T11, T14), ms, &(ri[0]));
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}
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T1b = VSUB(TF, Tu);
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T1c = VSUB(T19, T16);
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ST(&(ii[WS(rs, 2)]), VADD(T1b, T1c), ms, &(ii[0]));
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ST(&(ii[WS(rs, 6)]), VSUB(T1c, T1b), ms, &(ii[0]));
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{
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V TX, T1g, T10, T1d, TY, TZ;
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TX = VSUB(TH, TK);
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T1g = VSUB(T1e, T1f);
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TY = VSUB(TP, TM);
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TZ = VADD(TR, TU);
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T10 = VMUL(LDK(KP707106781), VSUB(TY, TZ));
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T1d = VMUL(LDK(KP707106781), VADD(TY, TZ));
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ST(&(ri[WS(rs, 7)]), VSUB(TX, T10), ms, &(ri[WS(rs, 1)]));
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ST(&(ii[WS(rs, 5)]), VSUB(T1g, T1d), ms, &(ii[WS(rs, 1)]));
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ST(&(ri[WS(rs, 3)]), VADD(TX, T10), ms, &(ri[WS(rs, 1)]));
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ST(&(ii[WS(rs, 1)]), VADD(T1d, T1g), ms, &(ii[WS(rs, 1)]));
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}
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{
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V TL, T1i, TW, T1h, TQ, TV;
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TL = VADD(TH, TK);
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T1i = VADD(T1f, T1e);
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TQ = VADD(TM, TP);
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TV = VSUB(TR, TU);
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TW = VMUL(LDK(KP707106781), VADD(TQ, TV));
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T1h = VMUL(LDK(KP707106781), VSUB(TV, TQ));
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ST(&(ri[WS(rs, 5)]), VSUB(TL, TW), ms, &(ri[WS(rs, 1)]));
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ST(&(ii[WS(rs, 7)]), VSUB(T1i, T1h), ms, &(ii[WS(rs, 1)]));
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ST(&(ri[WS(rs, 1)]), VADD(TL, TW), ms, &(ri[WS(rs, 1)]));
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ST(&(ii[WS(rs, 3)]), VADD(T1h, T1i), ms, &(ii[WS(rs, 1)]));
|
|
}
|
|
}
|
|
}
|
|
}
|
|
VLEAVE();
|
|
}
|
|
|
|
static const tw_instr twinstr[] = {
|
|
VTW(0, 1),
|
|
VTW(0, 2),
|
|
VTW(0, 3),
|
|
VTW(0, 4),
|
|
VTW(0, 5),
|
|
VTW(0, 6),
|
|
VTW(0, 7),
|
|
{ TW_NEXT, (2 * VL), 0 }
|
|
};
|
|
|
|
static const ct_desc desc = { 8, XSIMD_STRING("t1sv_8"), twinstr, &GENUS, { 52, 18, 14, 0 }, 0, 0, 0 };
|
|
|
|
void XSIMD(codelet_t1sv_8) (planner *p) {
|
|
X(kdft_dit_register) (p, t1sv_8, &desc);
|
|
}
|
|
#endif
|