mirror of
https://github.com/tildearrow/furnace.git
synced 2024-11-16 09:45:06 +00:00
54e93db207
not reliable yet
172 lines
5.6 KiB
C
172 lines
5.6 KiB
C
/*
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* Copyright (c) 2003, 2007-14 Matteo Frigo
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* Copyright (c) 2003, 2007-14 Massachusetts Institute of Technology
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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*
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*/
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/* This file was automatically generated --- DO NOT EDIT */
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/* Generated on Tue Sep 14 10:45:23 EDT 2021 */
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#include "dft/codelet-dft.h"
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#if defined(ARCH_PREFERS_FMA) || defined(ISA_EXTENSION_PREFERS_FMA)
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/* Generated by: ../../../genfft/gen_notw.native -fma -simd -compact -variables 4 -pipeline-latency 8 -n 4 -name n2sv_4 -with-ostride 1 -include dft/simd/n2s.h -store-multiple 4 */
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/*
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* This function contains 16 FP additions, 0 FP multiplications,
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* (or, 16 additions, 0 multiplications, 0 fused multiply/add),
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* 17 stack variables, 0 constants, and 18 memory accesses
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*/
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#include "dft/simd/n2s.h"
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static void n2sv_4(const R *ri, const R *ii, R *ro, R *io, stride is, stride os, INT v, INT ivs, INT ovs)
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{
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{
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INT i;
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for (i = v; i > 0; i = i - (2 * VL), ri = ri + ((2 * VL) * ivs), ii = ii + ((2 * VL) * ivs), ro = ro + ((2 * VL) * ovs), io = io + ((2 * VL) * ovs), MAKE_VOLATILE_STRIDE(16, is), MAKE_VOLATILE_STRIDE(16, os)) {
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V T3, Tb, T9, Tf, T6, Ta, Te, Tg;
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{
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V T1, T2, T7, T8;
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T1 = LD(&(ri[0]), ivs, &(ri[0]));
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T2 = LD(&(ri[WS(is, 2)]), ivs, &(ri[0]));
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T3 = VADD(T1, T2);
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Tb = VSUB(T1, T2);
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T7 = LD(&(ii[0]), ivs, &(ii[0]));
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T8 = LD(&(ii[WS(is, 2)]), ivs, &(ii[0]));
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T9 = VSUB(T7, T8);
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Tf = VADD(T7, T8);
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}
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{
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V T4, T5, Tc, Td;
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T4 = LD(&(ri[WS(is, 1)]), ivs, &(ri[WS(is, 1)]));
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T5 = LD(&(ri[WS(is, 3)]), ivs, &(ri[WS(is, 1)]));
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T6 = VADD(T4, T5);
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Ta = VSUB(T4, T5);
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Tc = LD(&(ii[WS(is, 1)]), ivs, &(ii[WS(is, 1)]));
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Td = LD(&(ii[WS(is, 3)]), ivs, &(ii[WS(is, 1)]));
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Te = VSUB(Tc, Td);
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Tg = VADD(Tc, Td);
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}
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{
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V Th, Ti, Tj, Tk;
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Th = VSUB(T3, T6);
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STM4(&(ro[2]), Th, ovs, &(ro[0]));
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Ti = VSUB(Tf, Tg);
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STM4(&(io[2]), Ti, ovs, &(io[0]));
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Tj = VADD(T3, T6);
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STM4(&(ro[0]), Tj, ovs, &(ro[0]));
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Tk = VADD(Tf, Tg);
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STM4(&(io[0]), Tk, ovs, &(io[0]));
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{
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V Tl, Tm, Tn, To;
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Tl = VSUB(T9, Ta);
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STM4(&(io[1]), Tl, ovs, &(io[1]));
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Tm = VADD(Tb, Te);
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STM4(&(ro[1]), Tm, ovs, &(ro[1]));
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Tn = VADD(Ta, T9);
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STM4(&(io[3]), Tn, ovs, &(io[1]));
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STN4(&(io[0]), Tk, Tl, Ti, Tn, ovs);
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To = VSUB(Tb, Te);
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STM4(&(ro[3]), To, ovs, &(ro[1]));
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STN4(&(ro[0]), Tj, Tm, Th, To, ovs);
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}
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}
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}
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}
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VLEAVE();
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}
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static const kdft_desc desc = { 4, XSIMD_STRING("n2sv_4"), { 16, 0, 0, 0 }, &GENUS, 0, 1, 0, 0 };
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void XSIMD(codelet_n2sv_4) (planner *p) { X(kdft_register) (p, n2sv_4, &desc);
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}
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#else
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/* Generated by: ../../../genfft/gen_notw.native -simd -compact -variables 4 -pipeline-latency 8 -n 4 -name n2sv_4 -with-ostride 1 -include dft/simd/n2s.h -store-multiple 4 */
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/*
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* This function contains 16 FP additions, 0 FP multiplications,
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* (or, 16 additions, 0 multiplications, 0 fused multiply/add),
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* 17 stack variables, 0 constants, and 18 memory accesses
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*/
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#include "dft/simd/n2s.h"
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static void n2sv_4(const R *ri, const R *ii, R *ro, R *io, stride is, stride os, INT v, INT ivs, INT ovs)
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{
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{
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INT i;
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for (i = v; i > 0; i = i - (2 * VL), ri = ri + ((2 * VL) * ivs), ii = ii + ((2 * VL) * ivs), ro = ro + ((2 * VL) * ovs), io = io + ((2 * VL) * ovs), MAKE_VOLATILE_STRIDE(16, is), MAKE_VOLATILE_STRIDE(16, os)) {
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V T3, Tb, T9, Tf, T6, Ta, Te, Tg;
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{
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V T1, T2, T7, T8;
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T1 = LD(&(ri[0]), ivs, &(ri[0]));
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T2 = LD(&(ri[WS(is, 2)]), ivs, &(ri[0]));
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T3 = VADD(T1, T2);
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Tb = VSUB(T1, T2);
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T7 = LD(&(ii[0]), ivs, &(ii[0]));
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T8 = LD(&(ii[WS(is, 2)]), ivs, &(ii[0]));
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T9 = VSUB(T7, T8);
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Tf = VADD(T7, T8);
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}
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{
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V T4, T5, Tc, Td;
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T4 = LD(&(ri[WS(is, 1)]), ivs, &(ri[WS(is, 1)]));
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T5 = LD(&(ri[WS(is, 3)]), ivs, &(ri[WS(is, 1)]));
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T6 = VADD(T4, T5);
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Ta = VSUB(T4, T5);
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Tc = LD(&(ii[WS(is, 1)]), ivs, &(ii[WS(is, 1)]));
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Td = LD(&(ii[WS(is, 3)]), ivs, &(ii[WS(is, 1)]));
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Te = VSUB(Tc, Td);
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Tg = VADD(Tc, Td);
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}
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{
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V Th, Ti, Tj, Tk;
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Th = VSUB(T3, T6);
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STM4(&(ro[2]), Th, ovs, &(ro[0]));
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Ti = VSUB(Tf, Tg);
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STM4(&(io[2]), Ti, ovs, &(io[0]));
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Tj = VADD(T3, T6);
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STM4(&(ro[0]), Tj, ovs, &(ro[0]));
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Tk = VADD(Tf, Tg);
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STM4(&(io[0]), Tk, ovs, &(io[0]));
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{
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V Tl, Tm, Tn, To;
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Tl = VSUB(T9, Ta);
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STM4(&(io[1]), Tl, ovs, &(io[1]));
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Tm = VADD(Tb, Te);
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STM4(&(ro[1]), Tm, ovs, &(ro[1]));
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Tn = VADD(Ta, T9);
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STM4(&(io[3]), Tn, ovs, &(io[1]));
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STN4(&(io[0]), Tk, Tl, Ti, Tn, ovs);
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To = VSUB(Tb, Te);
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STM4(&(ro[3]), To, ovs, &(ro[1]));
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STN4(&(ro[0]), Tj, Tm, Th, To, ovs);
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}
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}
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}
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}
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VLEAVE();
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}
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static const kdft_desc desc = { 4, XSIMD_STRING("n2sv_4"), { 16, 0, 0, 0 }, &GENUS, 0, 1, 0, 0 };
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void XSIMD(codelet_n2sv_4) (planner *p) { X(kdft_register) (p, n2sv_4, &desc);
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}
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#endif
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