mirror of
https://github.com/tildearrow/furnace.git
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998 lines
29 KiB
C++
998 lines
29 KiB
C++
/**
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* Furnace Tracker - multi-system chiptune tracker
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* Copyright (C) 2021-2022 tildearrow and contributors
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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*/
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#include "ym2203.h"
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#include "sound/ymfm/ymfm.h"
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#include "../engine.h"
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#include <string.h>
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#include <math.h>
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#define CHIP_FREQBASE fmFreqBase
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#define CHIP_DIVIDER fmDivBase
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const char* regCheatSheetYM2203[]={
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// SSG
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"SSG_FreqL_A", "000",
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"SSG_FreqH_A", "001",
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"SSG_FreqL_B", "002",
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"SSG_FreqH_B", "003",
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"SSG_FreqL_C", "004",
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"SSG_FreqH_C", "005",
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"SSG_FreqNoise", "006",
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"SSG_Enable", "007",
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"SSG_Volume_A", "008",
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"SSG_Volume_B", "009",
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"SSG_Volume_C", "00A",
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"SSG_FreqL_Env", "00B",
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"SSG_FreqH_Env", "00C",
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"SSG_Control_Env", "00D",
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// FM (Common)
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"FM_Test", "021",
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"ClockA1", "024",
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"ClockA2", "025",
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"ClockB", "026",
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"FM_Control", "027",
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"FM_NoteCtl", "028",
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// FM (Channel 1-3)
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"FM1_Op1_DT_MULT", "030",
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"FM2_Op1_DT_MULT", "031",
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"FM3_Op1_DT_MULT", "032",
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"FM1_Op2_DT_MULT", "034",
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"FM2_Op2_DT_MULT", "035",
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"FM3_Op2_DT_MULT", "036",
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"FM1_Op3_DT_MULT", "038",
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"FM2_Op3_DT_MULT", "039",
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"FM3_Op3_DT_MULT", "03A",
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"FM1_Op4_DT_MULT", "03C",
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"FM2_Op4_DT_MULT", "03D",
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"FM3_Op4_DT_MULT", "03E",
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"FM1_Op1_TL", "040",
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"FM2_Op1_TL", "041",
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"FM3_Op1_TL", "042",
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"FM1_Op2_TL", "044",
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"FM2_Op2_TL", "045",
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"FM3_Op2_TL", "046",
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"FM1_Op3_TL", "048",
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"FM2_Op3_TL", "049",
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"FM3_Op3_TL", "04A",
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"FM1_Op4_TL", "04C",
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"FM2_Op4_TL", "04D",
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"FM3_Op4_TL", "04E",
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"FM1_Op1_KS_AR", "050",
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"FM2_Op1_KS_AR", "051",
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"FM3_Op1_KS_AR", "052",
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"FM1_Op2_KS_AR", "054",
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"FM2_Op2_KS_AR", "055",
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"FM3_Op2_KS_AR", "056",
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"FM1_Op3_KS_AR", "058",
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"FM2_Op3_KS_AR", "059",
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"FM3_Op3_KS_AR", "05A",
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"FM1_Op4_KS_AR", "05C",
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"FM2_Op4_KS_AR", "05D",
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"FM3_Op4_KS_AR", "05E",
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"FM1_Op1_AM_DR", "060",
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"FM2_Op1_AM_DR", "061",
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"FM3_Op1_AM_DR", "062",
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"FM1_Op2_AM_DR", "064",
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"FM2_Op2_AM_DR", "065",
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"FM3_Op2_AM_DR", "066",
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"FM1_Op3_AM_DR", "068",
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"FM2_Op3_AM_DR", "069",
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"FM3_Op3_AM_DR", "06A",
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"FM1_Op4_AM_DR", "06C",
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"FM2_Op4_AM_DR", "06D",
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"FM3_Op4_AM_DR", "06E",
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"FM1_Op1_SR", "070",
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"FM2_Op1_SR", "071",
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"FM3_Op1_SR", "072",
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"FM1_Op2_SR", "074",
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"FM2_Op2_SR", "075",
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"FM3_Op2_SR", "076",
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"FM1_Op3_SR", "078",
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"FM2_Op3_SR", "079",
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"FM3_Op3_SR", "07A",
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"FM1_Op4_SR", "07C",
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"FM2_Op4_SR", "07D",
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"FM3_Op4_SR", "07E",
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"FM1_Op1_SL_RR", "080",
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"FM2_Op1_SL_RR", "081",
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"FM3_Op1_SL_RR", "082",
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"FM1_Op2_SL_RR", "084",
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"FM2_Op2_SL_RR", "085",
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"FM3_Op2_SL_RR", "086",
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"FM1_Op3_SL_RR", "088",
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"FM2_Op3_SL_RR", "089",
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"FM3_Op3_SL_RR", "08A",
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"FM1_Op4_SL_RR", "08C",
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"FM2_Op4_SL_RR", "08D",
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"FM3_Op4_SL_RR", "08E",
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"FM1_Op1_SSG_EG", "090",
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"FM2_Op1_SSG_EG", "091",
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"FM3_Op1_SSG_EG", "092",
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"FM1_Op2_SSG_EG", "094",
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"FM2_Op2_SSG_EG", "095",
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"FM3_Op2_SSG_EG", "096",
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"FM1_Op3_SSG_EG", "098",
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"FM2_Op3_SSG_EG", "099",
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"FM3_Op3_SSG_EG", "09A",
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"FM1_Op4_SSG_EG", "09C",
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"FM2_Op4_SSG_EG", "09D",
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"FM3_Op4_SSG_EG", "09E",
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"FM1_FNum1", "0A0",
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"FM2_FNum1", "0A1",
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"FM3_(Op1)FNum1", "0A2",
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"FM1_FNum2", "0A4",
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"FM2_FNum2", "0A5",
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"FM3_(Op1)FNum2", "0A6",
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"FM3_Op2_FNum1", "0A8",
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"FM3_Op3_FNum1", "0A9",
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"FM3_Op4_FNum1", "0AA",
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"FM3_Op2_FNum2", "0AC",
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"FM3_Op3_FNum2", "0AD",
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"FM3_Op4_FNum2", "0AE",
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"FM1_FB_ALG", "0B0",
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"FM2_FB_ALG", "0B1",
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"FM3_FB_ALG", "0B2",
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NULL
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};
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const char** DivPlatformYM2203::getRegisterSheet() {
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return regCheatSheetYM2203;
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}
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void DivPlatformYM2203::acquire(short* bufL, short* bufR, size_t start, size_t len) {
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static int os;
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ymfm::ym2203::fm_engine* fme=fm->debug_fm_engine();
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ymfm::fm_channel<ymfm::opn_registers_base<false>>* fmChan[3];
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for (int i=0; i<3; i++) {
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fmChan[i]=fme->debug_channel(i);
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}
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for (size_t h=start; h<start+len; h++) {
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os=0;
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if (!writes.empty()) {
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if (--delay<1) {
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QueuedWrite& w=writes.front();
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fm->write(0x0,w.addr);
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fm->write(0x1,w.val);
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regPool[w.addr&0xff]=w.val;
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writes.pop_front();
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delay=6;
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}
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}
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fm->generate(&fmout);
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os=fmout.data[0]+((fmout.data[1]+fmout.data[2]+fmout.data[3])>>1);
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if (os<-32768) os=-32768;
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if (os>32767) os=32767;
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bufL[h]=os;
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for (int i=0; i<3; i++) {
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oscBuf[i]->data[oscBuf[i]->needle++]=(fmChan[i]->debug_output(0)+fmChan[i]->debug_output(1));
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}
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for (int i=3; i<6; i++) {
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oscBuf[i]->data[oscBuf[i]->needle++]=fmout.data[i-2];
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}
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}
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}
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void DivPlatformYM2203::tick(bool sysTick) {
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// PSG
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ay->tick(sysTick);
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ay->flushWrites();
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for (DivRegWrite& i: ay->getRegisterWrites()) {
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if (i.addr>15) continue;
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immWrite(i.addr&15,i.val);
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}
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ay->getRegisterWrites().clear();
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// FM
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for (int i=0; i<3; i++) {
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if (i==2 && extMode) continue;
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chan[i].std.next();
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if (chan[i].std.vol.had) {
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chan[i].outVol=VOL_SCALE_LOG_BROKEN(chan[i].vol,MIN(127,chan[i].std.vol.val),127);
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for (int j=0; j<4; j++) {
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unsigned short baseAddr=chanOffs[i]|opOffs[j];
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DivInstrumentFM::Operator& op=chan[i].state.op[j];
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if (isMuted[i]) {
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rWrite(baseAddr+ADDR_TL,127);
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} else {
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if (KVS(i,j)) {
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rWrite(baseAddr+ADDR_TL,127-VOL_SCALE_LOG_BROKEN(127-op.tl,chan[i].outVol&0x7f,127));
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} else {
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rWrite(baseAddr+ADDR_TL,op.tl);
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}
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}
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}
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}
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if (chan[i].std.arp.had) {
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if (!chan[i].inPorta) {
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chan[i].baseFreq=NOTE_FNUM_BLOCK(parent->calcArp(chan[i].note,chan[i].std.arp.val),11);
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}
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chan[i].freqChanged=true;
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}
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if (chan[i].std.pitch.had) {
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if (chan[i].std.pitch.mode) {
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chan[i].pitch2+=chan[i].std.pitch.val;
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CLAMP_VAR(chan[i].pitch2,-32768,32767);
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} else {
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chan[i].pitch2=chan[i].std.pitch.val;
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}
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chan[i].freqChanged=true;
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}
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if (chan[i].std.phaseReset.had) {
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if (chan[i].std.phaseReset.val==1 && chan[i].active) {
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chan[i].keyOn=true;
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}
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}
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if (chan[i].std.alg.had) {
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chan[i].state.alg=chan[i].std.alg.val;
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rWrite(chanOffs[i]+ADDR_FB_ALG,(chan[i].state.alg&7)|(chan[i].state.fb<<3));
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if (!parent->song.algMacroBehavior) for (int j=0; j<4; j++) {
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unsigned short baseAddr=chanOffs[i]|opOffs[j];
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DivInstrumentFM::Operator& op=chan[i].state.op[j];
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if (isMuted[i]) {
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rWrite(baseAddr+ADDR_TL,127);
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} else {
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if (KVS(i,j)) {
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rWrite(baseAddr+ADDR_TL,127-VOL_SCALE_LOG_BROKEN(127-op.tl,chan[i].outVol&0x7f,127));
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} else {
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rWrite(baseAddr+ADDR_TL,op.tl);
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}
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}
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}
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}
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if (chan[i].std.fb.had) {
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chan[i].state.fb=chan[i].std.fb.val;
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rWrite(chanOffs[i]+ADDR_FB_ALG,(chan[i].state.alg&7)|(chan[i].state.fb<<3));
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}
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if (chan[i].std.ex4.had && chan[i].active) {
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chan[i].opMask=chan[i].std.ex4.val&15;
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chan[i].opMaskChanged=true;
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}
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for (int j=0; j<4; j++) {
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unsigned short baseAddr=chanOffs[i]|opOffs[j];
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DivInstrumentFM::Operator& op=chan[i].state.op[j];
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DivMacroInt::IntOp& m=chan[i].std.op[j];
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if (m.am.had) {
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op.am=m.am.val;
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rWrite(baseAddr+ADDR_AM_DR,(op.dr&31)|(op.am<<7));
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}
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if (m.ar.had) {
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op.ar=m.ar.val;
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rWrite(baseAddr+ADDR_RS_AR,(op.ar&31)|(op.rs<<6));
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}
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if (m.dr.had) {
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op.dr=m.dr.val;
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rWrite(baseAddr+ADDR_AM_DR,(op.dr&31)|(op.am<<7));
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}
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if (m.mult.had) {
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op.mult=m.mult.val;
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rWrite(baseAddr+ADDR_MULT_DT,(op.mult&15)|(dtTable[op.dt&7]<<4));
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}
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if (m.rr.had) {
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op.rr=m.rr.val;
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rWrite(baseAddr+ADDR_SL_RR,(op.rr&15)|(op.sl<<4));
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}
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if (m.sl.had) {
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op.sl=m.sl.val;
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rWrite(baseAddr+ADDR_SL_RR,(op.rr&15)|(op.sl<<4));
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}
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if (m.tl.had) {
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op.tl=127-m.tl.val;
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if (isMuted[i]) {
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rWrite(baseAddr+ADDR_TL,127);
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} else {
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if (KVS(i,j)) {
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rWrite(baseAddr+ADDR_TL,127-VOL_SCALE_LOG_BROKEN(127-op.tl,chan[i].outVol&0x7f,127));
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} else {
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rWrite(baseAddr+ADDR_TL,op.tl);
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}
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}
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}
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if (m.rs.had) {
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op.rs=m.rs.val;
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rWrite(baseAddr+ADDR_RS_AR,(op.ar&31)|(op.rs<<6));
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}
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if (m.dt.had) {
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op.dt=m.dt.val;
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rWrite(baseAddr+ADDR_MULT_DT,(op.mult&15)|(dtTable[op.dt&7]<<4));
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}
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if (m.d2r.had) {
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op.d2r=m.d2r.val;
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rWrite(baseAddr+ADDR_DT2_D2R,op.d2r&31);
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}
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if (m.ssg.had) {
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op.ssgEnv=m.ssg.val;
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rWrite(baseAddr+ADDR_SSG,op.ssgEnv&15);
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}
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}
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if (chan[i].keyOn || chan[i].keyOff) {
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if (chan[i].hardReset && chan[i].keyOn) {
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for (int j=0; j<4; j++) {
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unsigned short baseAddr=chanOffs[i]|opOffs[j];
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immWrite(baseAddr+ADDR_SL_RR,0x0f);
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immWrite(baseAddr+ADDR_TL,0x7f);
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oldWrites[baseAddr+ADDR_SL_RR]=-1;
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oldWrites[baseAddr+ADDR_TL]=-1;
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//rWrite(baseAddr+ADDR_SL_RR,(op.rr&15)|(op.sl<<4));
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}
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}
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immWrite(0x28,0x00|konOffs[i]);
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if (chan[i].hardReset && chan[i].keyOn) {
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for (int j=0; j<4; j++) {
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unsigned short baseAddr=chanOffs[i]|opOffs[j];
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for (int k=0; k<100; k++) {
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immWrite(baseAddr+ADDR_SL_RR,0x0f);
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}
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}
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}
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chan[i].keyOff=false;
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}
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}
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for (int i=16; i<256; i++) {
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if (pendingWrites[i]!=oldWrites[i]) {
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immWrite(i,pendingWrites[i]&0xff);
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oldWrites[i]=pendingWrites[i];
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}
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}
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for (int i=0; i<3; i++) {
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if (i==2 && extMode) continue;
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if (chan[i].freqChanged) {
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if (parent->song.linearPitch==2) {
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chan[i].freq=parent->calcFreq(chan[i].baseFreq,chan[i].pitch,false,4,chan[i].pitch2,chipClock,CHIP_FREQBASE,11);
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} else {
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int fNum=parent->calcFreq(chan[i].baseFreq&0x7ff,chan[i].pitch,false,4,chan[i].pitch2);
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int block=(chan[i].baseFreq&0xf800)>>11;
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if (fNum<0) fNum=0;
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if (fNum>2047) {
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while (block<7) {
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fNum>>=1;
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block++;
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}
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if (fNum>2047) fNum=2047;
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}
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chan[i].freq=(block<<11)|fNum;
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}
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if (chan[i].freq>0x3fff) chan[i].freq=0x3fff;
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immWrite(chanOffs[i]+ADDR_FREQH,chan[i].freq>>8);
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immWrite(chanOffs[i]+ADDR_FREQ,chan[i].freq&0xff);
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chan[i].freqChanged=false;
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}
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if (chan[i].keyOn || chan[i].opMaskChanged) {
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immWrite(0x28,(chan[i].opMask<<4)|konOffs[i]);
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chan[i].opMaskChanged=false;
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chan[i].keyOn=false;
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}
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}
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}
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int DivPlatformYM2203::dispatch(DivCommand c) {
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if (c.chan>2) {
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c.chan-=3;
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return ay->dispatch(c);
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}
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switch (c.cmd) {
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case DIV_CMD_NOTE_ON: {
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DivInstrument* ins=parent->getIns(chan[c.chan].ins,DIV_INS_FM);
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chan[c.chan].macroInit(ins);
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if (c.chan<3) {
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if (!chan[c.chan].std.vol.will) {
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chan[c.chan].outVol=chan[c.chan].vol;
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}
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}
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if (chan[c.chan].insChanged) {
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chan[c.chan].state=ins->fm;
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chan[c.chan].opMask=
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(chan[c.chan].state.op[0].enable?1:0)|
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(chan[c.chan].state.op[2].enable?2:0)|
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(chan[c.chan].state.op[1].enable?4:0)|
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(chan[c.chan].state.op[3].enable?8:0);
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}
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for (int i=0; i<4; i++) {
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unsigned short baseAddr=chanOffs[c.chan]|opOffs[i];
|
|
DivInstrumentFM::Operator& op=chan[c.chan].state.op[i];
|
|
if (isMuted[c.chan]) {
|
|
rWrite(baseAddr+ADDR_TL,127);
|
|
} else {
|
|
if (KVS(c.chan,i)) {
|
|
if (!chan[c.chan].active || chan[c.chan].insChanged) {
|
|
rWrite(baseAddr+ADDR_TL,127-VOL_SCALE_LOG_BROKEN(127-op.tl,chan[c.chan].outVol&0x7f,127));
|
|
}
|
|
} else {
|
|
if (chan[c.chan].insChanged) {
|
|
rWrite(baseAddr+ADDR_TL,op.tl);
|
|
}
|
|
}
|
|
}
|
|
if (chan[c.chan].insChanged) {
|
|
rWrite(baseAddr+ADDR_MULT_DT,(op.mult&15)|(dtTable[op.dt&7]<<4));
|
|
rWrite(baseAddr+ADDR_RS_AR,(op.ar&31)|(op.rs<<6));
|
|
rWrite(baseAddr+ADDR_AM_DR,(op.dr&31)|(op.am<<7));
|
|
rWrite(baseAddr+ADDR_DT2_D2R,op.d2r&31);
|
|
rWrite(baseAddr+ADDR_SL_RR,(op.rr&15)|(op.sl<<4));
|
|
rWrite(baseAddr+ADDR_SSG,op.ssgEnv&15);
|
|
}
|
|
}
|
|
if (chan[c.chan].insChanged) {
|
|
rWrite(chanOffs[c.chan]+ADDR_FB_ALG,(chan[c.chan].state.alg&7)|(chan[c.chan].state.fb<<3));
|
|
}
|
|
chan[c.chan].insChanged=false;
|
|
|
|
if (c.value!=DIV_NOTE_NULL) {
|
|
chan[c.chan].baseFreq=NOTE_FNUM_BLOCK(c.value,11);
|
|
chan[c.chan].portaPause=false;
|
|
chan[c.chan].freqChanged=true;
|
|
chan[c.chan].note=c.value;
|
|
}
|
|
chan[c.chan].keyOn=true;
|
|
chan[c.chan].active=true;
|
|
break;
|
|
}
|
|
case DIV_CMD_NOTE_OFF:
|
|
chan[c.chan].keyOff=true;
|
|
chan[c.chan].keyOn=false;
|
|
chan[c.chan].active=false;
|
|
chan[c.chan].macroInit(NULL);
|
|
break;
|
|
case DIV_CMD_NOTE_OFF_ENV:
|
|
chan[c.chan].keyOff=true;
|
|
chan[c.chan].keyOn=false;
|
|
chan[c.chan].active=false;
|
|
chan[c.chan].std.release();
|
|
break;
|
|
case DIV_CMD_ENV_RELEASE:
|
|
chan[c.chan].std.release();
|
|
break;
|
|
case DIV_CMD_VOLUME: {
|
|
chan[c.chan].vol=c.value;
|
|
if (!chan[c.chan].std.vol.has) {
|
|
chan[c.chan].outVol=c.value;
|
|
}
|
|
for (int i=0; i<4; i++) {
|
|
unsigned short baseAddr=chanOffs[c.chan]|opOffs[i];
|
|
DivInstrumentFM::Operator& op=chan[c.chan].state.op[i];
|
|
if (isMuted[c.chan]) {
|
|
rWrite(baseAddr+ADDR_TL,127);
|
|
} else {
|
|
if (KVS(c.chan,i)) {
|
|
rWrite(baseAddr+ADDR_TL,127-VOL_SCALE_LOG_BROKEN(127-op.tl,chan[c.chan].outVol&0x7f,127));
|
|
} else {
|
|
rWrite(baseAddr+ADDR_TL,op.tl);
|
|
}
|
|
}
|
|
}
|
|
break;
|
|
}
|
|
case DIV_CMD_GET_VOLUME: {
|
|
return chan[c.chan].vol;
|
|
break;
|
|
}
|
|
case DIV_CMD_INSTRUMENT:
|
|
if (chan[c.chan].ins!=c.value || c.value2==1) {
|
|
chan[c.chan].insChanged=true;
|
|
}
|
|
chan[c.chan].ins=c.value;
|
|
break;
|
|
case DIV_CMD_PITCH: {
|
|
chan[c.chan].pitch=c.value;
|
|
chan[c.chan].freqChanged=true;
|
|
break;
|
|
}
|
|
case DIV_CMD_NOTE_PORTA: {
|
|
if (c.chan>2 || parent->song.linearPitch==2) { // PSG
|
|
int destFreq=NOTE_FNUM_BLOCK(c.value2,11);
|
|
bool return2=false;
|
|
if (destFreq>chan[c.chan].baseFreq) {
|
|
chan[c.chan].baseFreq+=c.value;
|
|
if (chan[c.chan].baseFreq>=destFreq) {
|
|
chan[c.chan].baseFreq=destFreq;
|
|
return2=true;
|
|
}
|
|
} else {
|
|
chan[c.chan].baseFreq-=c.value;
|
|
if (chan[c.chan].baseFreq<=destFreq) {
|
|
chan[c.chan].baseFreq=destFreq;
|
|
return2=true;
|
|
}
|
|
}
|
|
chan[c.chan].freqChanged=true;
|
|
if (return2) {
|
|
chan[c.chan].inPorta=false;
|
|
return 2;
|
|
}
|
|
break;
|
|
}
|
|
PLEASE_HELP_ME(chan[c.chan]);
|
|
break;
|
|
}
|
|
case DIV_CMD_LEGATO: {
|
|
chan[c.chan].baseFreq=NOTE_FNUM_BLOCK(c.value,11);
|
|
chan[c.chan].freqChanged=true;
|
|
break;
|
|
}
|
|
case DIV_CMD_FM_EXTCH: {
|
|
if (extSys) {
|
|
extMode=c.value;
|
|
immWrite(0x27,extMode?0x40:0);
|
|
}
|
|
break;
|
|
}
|
|
case DIV_CMD_FM_FB: {
|
|
if (c.chan>2) break;
|
|
chan[c.chan].state.fb=c.value&7;
|
|
rWrite(chanOffs[c.chan]+ADDR_FB_ALG,(chan[c.chan].state.alg&7)|(chan[c.chan].state.fb<<3));
|
|
break;
|
|
}
|
|
case DIV_CMD_FM_MULT: {
|
|
if (c.chan>2) break;
|
|
unsigned short baseAddr=chanOffs[c.chan]|opOffs[orderedOps[c.value]];
|
|
DivInstrumentFM::Operator& op=chan[c.chan].state.op[orderedOps[c.value]];
|
|
op.mult=c.value2&15;
|
|
rWrite(baseAddr+ADDR_MULT_DT,(op.mult&15)|(dtTable[op.dt&7]<<4));
|
|
break;
|
|
}
|
|
case DIV_CMD_FM_TL: {
|
|
if (c.chan>2) break;
|
|
unsigned short baseAddr=chanOffs[c.chan]|opOffs[orderedOps[c.value]];
|
|
DivInstrumentFM::Operator& op=chan[c.chan].state.op[orderedOps[c.value]];
|
|
op.tl=c.value2;
|
|
if (isMuted[c.chan]) {
|
|
rWrite(baseAddr+ADDR_TL,127);
|
|
} else {
|
|
if (KVS(c.chan,c.value)) {
|
|
rWrite(baseAddr+ADDR_TL,127-VOL_SCALE_LOG_BROKEN(127-op.tl,chan[c.chan].outVol&0x7f,127));
|
|
} else {
|
|
rWrite(baseAddr+ADDR_TL,op.tl);
|
|
}
|
|
}
|
|
break;
|
|
}
|
|
case DIV_CMD_FM_AR: {
|
|
if (c.chan>2) break;
|
|
if (c.value<0) {
|
|
for (int i=0; i<4; i++) {
|
|
DivInstrumentFM::Operator& op=chan[c.chan].state.op[i];
|
|
op.ar=c.value2&31;
|
|
unsigned short baseAddr=chanOffs[c.chan]|opOffs[i];
|
|
rWrite(baseAddr+ADDR_RS_AR,(op.ar&31)|(op.rs<<6));
|
|
}
|
|
} else {
|
|
DivInstrumentFM::Operator& op=chan[c.chan].state.op[orderedOps[c.value]];
|
|
op.ar=c.value2&31;
|
|
unsigned short baseAddr=chanOffs[c.chan]|opOffs[orderedOps[c.value]];
|
|
rWrite(baseAddr+ADDR_RS_AR,(op.ar&31)|(op.rs<<6));
|
|
}
|
|
break;
|
|
}
|
|
case DIV_CMD_FM_RS: {
|
|
if (c.value<0) {
|
|
for (int i=0; i<4; i++) {
|
|
DivInstrumentFM::Operator& op=chan[c.chan].state.op[i];
|
|
op.rs=c.value2&3;
|
|
unsigned short baseAddr=chanOffs[c.chan]|opOffs[i];
|
|
rWrite(baseAddr+ADDR_RS_AR,(op.ar&31)|(op.rs<<6));
|
|
}
|
|
} else if (c.value<4) {
|
|
DivInstrumentFM::Operator& op=chan[c.chan].state.op[orderedOps[c.value]];
|
|
op.rs=c.value2&3;
|
|
unsigned short baseAddr=chanOffs[c.chan]|opOffs[orderedOps[c.value]];
|
|
rWrite(baseAddr+ADDR_RS_AR,(op.ar&31)|(op.rs<<6));
|
|
}
|
|
break;
|
|
}
|
|
case DIV_CMD_FM_AM: {
|
|
if (c.value<0) {
|
|
for (int i=0; i<4; i++) {
|
|
DivInstrumentFM::Operator& op=chan[c.chan].state.op[i];
|
|
op.am=c.value2&1;
|
|
unsigned short baseAddr=chanOffs[c.chan]|opOffs[i];
|
|
rWrite(baseAddr+ADDR_AM_DR,(op.dr&31)|(op.am<<7));
|
|
}
|
|
} else if (c.value<4) {
|
|
DivInstrumentFM::Operator& op=chan[c.chan].state.op[orderedOps[c.value]];
|
|
op.am=c.value2&1;
|
|
unsigned short baseAddr=chanOffs[c.chan]|opOffs[orderedOps[c.value]];
|
|
rWrite(baseAddr+ADDR_AM_DR,(op.dr&31)|(op.am<<7));
|
|
}
|
|
break;
|
|
}
|
|
case DIV_CMD_FM_DR: {
|
|
if (c.value<0) {
|
|
for (int i=0; i<4; i++) {
|
|
DivInstrumentFM::Operator& op=chan[c.chan].state.op[i];
|
|
op.dr=c.value2&31;
|
|
unsigned short baseAddr=chanOffs[c.chan]|opOffs[i];
|
|
rWrite(baseAddr+ADDR_AM_DR,(op.dr&31)|(op.am<<7));
|
|
}
|
|
} else if (c.value<4) {
|
|
DivInstrumentFM::Operator& op=chan[c.chan].state.op[orderedOps[c.value]];
|
|
op.dr=c.value2&31;
|
|
unsigned short baseAddr=chanOffs[c.chan]|opOffs[orderedOps[c.value]];
|
|
rWrite(baseAddr+ADDR_AM_DR,(op.dr&31)|(op.am<<7));
|
|
}
|
|
break;
|
|
}
|
|
case DIV_CMD_FM_SL: {
|
|
if (c.value<0) {
|
|
for (int i=0; i<4; i++) {
|
|
DivInstrumentFM::Operator& op=chan[c.chan].state.op[i];
|
|
op.sl=c.value2&15;
|
|
unsigned short baseAddr=chanOffs[c.chan]|opOffs[i];
|
|
rWrite(baseAddr+ADDR_SL_RR,(op.rr&15)|(op.sl<<4));
|
|
}
|
|
} else if (c.value<4) {
|
|
DivInstrumentFM::Operator& op=chan[c.chan].state.op[orderedOps[c.value]];
|
|
op.sl=c.value2&15;
|
|
unsigned short baseAddr=chanOffs[c.chan]|opOffs[orderedOps[c.value]];
|
|
rWrite(baseAddr+ADDR_SL_RR,(op.rr&15)|(op.sl<<4));
|
|
}
|
|
break;
|
|
}
|
|
case DIV_CMD_FM_RR: {
|
|
if (c.value<0) {
|
|
for (int i=0; i<4; i++) {
|
|
DivInstrumentFM::Operator& op=chan[c.chan].state.op[i];
|
|
op.rr=c.value2&15;
|
|
unsigned short baseAddr=chanOffs[c.chan]|opOffs[i];
|
|
rWrite(baseAddr+ADDR_SL_RR,(op.rr&15)|(op.sl<<4));
|
|
}
|
|
} else if (c.value<4) {
|
|
DivInstrumentFM::Operator& op=chan[c.chan].state.op[orderedOps[c.value]];
|
|
op.rr=c.value2&15;
|
|
unsigned short baseAddr=chanOffs[c.chan]|opOffs[orderedOps[c.value]];
|
|
rWrite(baseAddr+ADDR_SL_RR,(op.rr&15)|(op.sl<<4));
|
|
}
|
|
break;
|
|
}
|
|
case DIV_CMD_FM_D2R: {
|
|
if (c.value<0) {
|
|
for (int i=0; i<4; i++) {
|
|
DivInstrumentFM::Operator& op=chan[c.chan].state.op[i];
|
|
op.d2r=c.value2&31;
|
|
unsigned short baseAddr=chanOffs[c.chan]|opOffs[i];
|
|
rWrite(baseAddr+ADDR_DT2_D2R,op.d2r&31);
|
|
}
|
|
} else if (c.value<4) {
|
|
DivInstrumentFM::Operator& op=chan[c.chan].state.op[orderedOps[c.value]];
|
|
op.d2r=c.value2&31;
|
|
unsigned short baseAddr=chanOffs[c.chan]|opOffs[orderedOps[c.value]];
|
|
rWrite(baseAddr+ADDR_DT2_D2R,op.d2r&31);
|
|
}
|
|
break;
|
|
}
|
|
case DIV_CMD_FM_DT: {
|
|
if (c.value<0) {
|
|
for (int i=0; i<4; i++) {
|
|
DivInstrumentFM::Operator& op=chan[c.chan].state.op[i];
|
|
op.dt=c.value&7;
|
|
unsigned short baseAddr=chanOffs[c.chan]|opOffs[i];
|
|
rWrite(baseAddr+ADDR_MULT_DT,(op.mult&15)|(dtTable[op.dt&7]<<4));
|
|
}
|
|
} else if (c.value<4) {
|
|
DivInstrumentFM::Operator& op=chan[c.chan].state.op[orderedOps[c.value]];
|
|
op.dt=c.value2&7;
|
|
unsigned short baseAddr=chanOffs[c.chan]|opOffs[orderedOps[c.value]];
|
|
rWrite(baseAddr+ADDR_MULT_DT,(op.mult&15)|(dtTable[op.dt&7]<<4));
|
|
}
|
|
break;
|
|
}
|
|
case DIV_CMD_FM_SSG: {
|
|
if (c.value<0) {
|
|
for (int i=0; i<4; i++) {
|
|
DivInstrumentFM::Operator& op=chan[c.chan].state.op[i];
|
|
op.ssgEnv=8^(c.value2&15);
|
|
unsigned short baseAddr=chanOffs[c.chan]|opOffs[i];
|
|
rWrite(baseAddr+ADDR_SSG,op.ssgEnv&15);
|
|
}
|
|
} else if (c.value<4) {
|
|
DivInstrumentFM::Operator& op=chan[c.chan].state.op[orderedOps[c.value]];
|
|
op.ssgEnv=8^(c.value2&15);
|
|
unsigned short baseAddr=chanOffs[c.chan]|opOffs[orderedOps[c.value]];
|
|
rWrite(baseAddr+ADDR_SSG,op.ssgEnv&15);
|
|
}
|
|
break;
|
|
}
|
|
case DIV_CMD_FM_HARD_RESET:
|
|
chan[c.chan].hardReset=c.value;
|
|
break;
|
|
case DIV_ALWAYS_SET_VOLUME:
|
|
return 0;
|
|
break;
|
|
case DIV_CMD_GET_VOLMAX:
|
|
if (c.chan>2) return 15;
|
|
return 127;
|
|
break;
|
|
case DIV_CMD_PRE_PORTA:
|
|
if (c.chan>2) {
|
|
if (chan[c.chan].active && c.value2) {
|
|
if (parent->song.resetMacroOnPorta) chan[c.chan].macroInit(parent->getIns(chan[c.chan].ins,DIV_INS_FM));
|
|
}
|
|
}
|
|
chan[c.chan].inPorta=c.value;
|
|
break;
|
|
case DIV_CMD_PRE_NOTE:
|
|
break;
|
|
default:
|
|
//printf("WARNING: unimplemented command %d\n",c.cmd);
|
|
break;
|
|
}
|
|
return 1;
|
|
}
|
|
|
|
void DivPlatformYM2203::muteChannel(int ch, bool mute) {
|
|
isMuted[ch]=mute;
|
|
if (ch>2) { // PSG
|
|
ay->muteChannel(ch-3,mute);
|
|
return;
|
|
}
|
|
for (int j=0; j<4; j++) {
|
|
unsigned short baseAddr=chanOffs[ch]|opOffs[j];
|
|
DivInstrumentFM::Operator& op=chan[ch].state.op[j];
|
|
if (isMuted[ch]) {
|
|
rWrite(baseAddr+ADDR_TL,127);
|
|
} else {
|
|
if (KVS(ch,j)) {
|
|
rWrite(baseAddr+ADDR_TL,127-VOL_SCALE_LOG_BROKEN(127-op.tl,chan[ch].outVol&0x7f,127));
|
|
} else {
|
|
rWrite(baseAddr+ADDR_TL,op.tl);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
void DivPlatformYM2203::forceIns() {
|
|
for (int i=0; i<3; i++) {
|
|
for (int j=0; j<4; j++) {
|
|
unsigned short baseAddr=chanOffs[i]|opOffs[j];
|
|
DivInstrumentFM::Operator& op=chan[i].state.op[j];
|
|
if (isMuted[i]) {
|
|
rWrite(baseAddr+ADDR_TL,127);
|
|
} else {
|
|
if (KVS(i,j)) {
|
|
rWrite(baseAddr+ADDR_TL,127-VOL_SCALE_LOG_BROKEN(127-op.tl,chan[i].outVol&0x7f,127));
|
|
} else {
|
|
rWrite(baseAddr+ADDR_TL,op.tl);
|
|
}
|
|
}
|
|
rWrite(baseAddr+ADDR_MULT_DT,(op.mult&15)|(dtTable[op.dt&7]<<4));
|
|
rWrite(baseAddr+ADDR_RS_AR,(op.ar&31)|(op.rs<<6));
|
|
rWrite(baseAddr+ADDR_AM_DR,(op.dr&31)|(op.am<<7));
|
|
rWrite(baseAddr+ADDR_DT2_D2R,op.d2r&31);
|
|
rWrite(baseAddr+ADDR_SL_RR,(op.rr&15)|(op.sl<<4));
|
|
rWrite(baseAddr+ADDR_SSG,op.ssgEnv&15);
|
|
}
|
|
rWrite(chanOffs[i]+ADDR_FB_ALG,(chan[i].state.alg&7)|(chan[i].state.fb<<3));
|
|
if (chan[i].active) {
|
|
chan[i].keyOn=true;
|
|
chan[i].freqChanged=true;
|
|
}
|
|
}
|
|
for (int i=3; i<6; i++) {
|
|
chan[i].insChanged=true;
|
|
}
|
|
|
|
ay->forceIns();
|
|
ay->flushWrites();
|
|
for (DivRegWrite& i: ay->getRegisterWrites()) {
|
|
if (i.addr>15) continue;
|
|
immWrite(i.addr&15,i.val);
|
|
}
|
|
ay->getRegisterWrites().clear();
|
|
}
|
|
|
|
void* DivPlatformYM2203::getChanState(int ch) {
|
|
return &chan[ch];
|
|
}
|
|
|
|
DivMacroInt* DivPlatformYM2203::getChanMacroInt(int ch) {
|
|
if (ch>=3) return ay->getChanMacroInt(ch-3);
|
|
return &chan[ch].std;
|
|
}
|
|
|
|
DivDispatchOscBuffer* DivPlatformYM2203::getOscBuffer(int ch) {
|
|
return oscBuf[ch];
|
|
}
|
|
|
|
unsigned char* DivPlatformYM2203::getRegisterPool() {
|
|
return regPool;
|
|
}
|
|
|
|
int DivPlatformYM2203::getRegisterPoolSize() {
|
|
return 256;
|
|
}
|
|
|
|
void DivPlatformYM2203::poke(unsigned int addr, unsigned short val) {
|
|
immWrite(addr,val);
|
|
}
|
|
|
|
void DivPlatformYM2203::poke(std::vector<DivRegWrite>& wlist) {
|
|
for (DivRegWrite& i: wlist) immWrite(i.addr,i.val);
|
|
}
|
|
|
|
void DivPlatformYM2203::reset() {
|
|
while (!writes.empty()) writes.pop_front();
|
|
memset(regPool,0,256);
|
|
if (dumpWrites) {
|
|
addWrite(0xffffffff,0);
|
|
}
|
|
fm->reset();
|
|
for (int i=0; i<6; i++) {
|
|
chan[i]=DivPlatformOPN::OPNChannel();
|
|
chan[i].std.setEngine(parent);
|
|
}
|
|
for (int i=0; i<3; i++) {
|
|
chan[i].vol=0x7f;
|
|
chan[i].outVol=0x7f;
|
|
}
|
|
for (int i=3; i<6; i++) {
|
|
chan[i].vol=0x0f;
|
|
}
|
|
|
|
for (int i=0; i<256; i++) {
|
|
oldWrites[i]=-1;
|
|
pendingWrites[i]=-1;
|
|
}
|
|
|
|
lastBusy=60;
|
|
sampleBank=0;
|
|
|
|
delay=0;
|
|
|
|
extMode=false;
|
|
|
|
// set prescaler
|
|
immWrite(0x2d,0xff);
|
|
immWrite(prescale,0xff);
|
|
|
|
ay->reset();
|
|
ay->getRegisterWrites().clear();
|
|
ay->flushWrites();
|
|
}
|
|
|
|
bool DivPlatformYM2203::isStereo() {
|
|
return false;
|
|
}
|
|
|
|
bool DivPlatformYM2203::keyOffAffectsArp(int ch) {
|
|
return (ch>2);
|
|
}
|
|
|
|
void DivPlatformYM2203::notifyInsChange(int ins) {
|
|
for (int i=0; i<6; i++) {
|
|
if (chan[i].ins==ins) {
|
|
chan[i].insChanged=true;
|
|
}
|
|
}
|
|
ay->notifyInsChange(ins);
|
|
}
|
|
|
|
void DivPlatformYM2203::notifyInsDeletion(void* ins) {
|
|
ay->notifyInsDeletion(ins);
|
|
}
|
|
|
|
void DivPlatformYM2203::setSkipRegisterWrites(bool value) {
|
|
DivDispatch::setSkipRegisterWrites(value);
|
|
ay->setSkipRegisterWrites(value);
|
|
}
|
|
|
|
void DivPlatformYM2203::setFlags(const DivConfig& flags) {
|
|
// Clock flags
|
|
switch (flags.getInt("clockSel",0)) {
|
|
case 0x01:
|
|
chipClock=COLOR_PAL*4.0/5.0;
|
|
break;
|
|
case 0x02:
|
|
chipClock=4000000.0;
|
|
break;
|
|
case 0x03:
|
|
chipClock=3000000.0;
|
|
break;
|
|
case 0x04:
|
|
chipClock=38400*13*8; // 31948800/8
|
|
break;
|
|
case 0x05:
|
|
chipClock=3000000.0/2.0;
|
|
break;
|
|
default:
|
|
chipClock=COLOR_NTSC;
|
|
break;
|
|
}
|
|
// Prescaler flags
|
|
switch (flags.getInt("prescale",0)) {
|
|
case 0x01: // /3
|
|
prescale=0x2e;
|
|
fmFreqBase=4720270.0/2.0,
|
|
fmDivBase=18,
|
|
ayDiv=8;
|
|
break;
|
|
case 0x02: // /2
|
|
prescale=0x2f;
|
|
fmFreqBase=4720270.0/3.0,
|
|
fmDivBase=12,
|
|
ayDiv=4;
|
|
break;
|
|
default: // /6
|
|
prescale=0x2d;
|
|
fmFreqBase=4720270.0,
|
|
fmDivBase=36,
|
|
ayDiv=16;
|
|
break;
|
|
}
|
|
CHECK_CUSTOM_CLOCK;
|
|
noExtMacros=flags.getBool("noExtMacros",false);
|
|
rate=fm->sample_rate(chipClock);
|
|
for (int i=0; i<6; i++) {
|
|
oscBuf[i]->rate=rate;
|
|
}
|
|
immWrite(0x2d,0xff);
|
|
immWrite(prescale,0xff);
|
|
ay->setExtClockDiv(chipClock,ayDiv);
|
|
ay->setFlags(ayFlags);
|
|
}
|
|
|
|
int DivPlatformYM2203::init(DivEngine* p, int channels, int sugRate, const DivConfig& flags) {
|
|
ayFlags.set("chipType",1);
|
|
parent=p;
|
|
dumpWrites=false;
|
|
skipRegisterWrites=false;
|
|
for (int i=0; i<6; i++) {
|
|
isMuted[i]=false;
|
|
oscBuf[i]=new DivDispatchOscBuffer;
|
|
}
|
|
fm=new ymfm::ym2203(iface);
|
|
fm->set_fidelity(ymfm::OPN_FIDELITY_MIN);
|
|
// YM2149, 2MHz
|
|
ay=new DivPlatformAY8910(true,chipClock,ayDiv);
|
|
ay->init(p,3,sugRate,ayFlags);
|
|
ay->toggleRegisterDump(true);
|
|
setFlags(flags);
|
|
|
|
reset();
|
|
return 6;
|
|
}
|
|
|
|
void DivPlatformYM2203::quit() {
|
|
for (int i=0; i<6; i++) {
|
|
delete oscBuf[i];
|
|
}
|
|
ay->quit();
|
|
delete ay;
|
|
delete fm;
|
|
}
|
|
|
|
DivPlatformYM2203::~DivPlatformYM2203() {
|
|
}
|