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T6W28: correct clock rate
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parent
f8896ed64c
commit
ea0b573402
1 changed files with 10 additions and 4 deletions
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@ -25,7 +25,7 @@
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//#define rWrite(a,v) pendingWrites[a]=v;
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//#define rWrite(a,v) pendingWrites[a]=v;
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#define rWrite(a,v) if (!skipRegisterWrites) {writes.emplace(a,v); if (dumpWrites) {addWrite(a,v);} }
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#define rWrite(a,v) if (!skipRegisterWrites) {writes.emplace(a,v); if (dumpWrites) {addWrite(a,v);} }
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#define CHIP_DIVIDER 64
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#define CHIP_DIVIDER 16
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const char* regCheatSheetT6W28[]={
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const char* regCheatSheetT6W28[]={
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"Data0", "0",
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"Data0", "0",
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@ -113,8 +113,14 @@ void DivPlatformT6W28::tick(bool sysTick) {
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//DivInstrument* ins=parent->getIns(chan[i].ins,DIV_INS_PCE);
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//DivInstrument* ins=parent->getIns(chan[i].ins,DIV_INS_PCE);
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chan[i].freq=parent->calcFreq(chan[i].baseFreq,chan[i].pitch,true,0,chan[i].pitch2,chipClock,CHIP_DIVIDER);
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chan[i].freq=parent->calcFreq(chan[i].baseFreq,chan[i].pitch,true,0,chan[i].pitch2,chipClock,CHIP_DIVIDER);
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if (chan[i].freq>1023) chan[i].freq=1023;
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if (chan[i].freq>1023) chan[i].freq=1023;
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if (i==3) {
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rWrite(1,0xe7);
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rWrite(1,0x80|(2<<5)|(chan[3].freq&15));
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rWrite(1,chan[3].freq>>4);
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} else {
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rWrite(0,0x80|i<<5|(chan[i].freq&15));
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rWrite(0,0x80|i<<5|(chan[i].freq&15));
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rWrite(0,chan[i].freq>>4);
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rWrite(0,chan[i].freq>>4);
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}
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if (chan[i].keyOn) chan[i].keyOn=false;
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if (chan[i].keyOn) chan[i].keyOn=false;
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if (chan[i].keyOff) chan[i].keyOff=false;
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if (chan[i].keyOff) chan[i].keyOff=false;
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chan[i].freqChanged=false;
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chan[i].freqChanged=false;
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@ -298,7 +304,7 @@ void DivPlatformT6W28::notifyInsDeletion(void* ins) {
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}
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}
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void DivPlatformT6W28::setFlags(const DivConfig& flags) {
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void DivPlatformT6W28::setFlags(const DivConfig& flags) {
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chipClock=4000000.0;
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chipClock=3072000.0;
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rate=chipClock/16;
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rate=chipClock/16;
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for (int i=0; i<4; i++) {
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for (int i=0; i<4; i++) {
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oscBuf[i]->rate=rate;
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oscBuf[i]->rate=rate;
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