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VERA: Run noise generation in each channel update
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parent
fc489239c2
commit
e2449d91f1
1 changed files with 14 additions and 10 deletions
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@ -20,8 +20,8 @@ void
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psg_reset(struct VERA_PSG* psg)
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psg_reset(struct VERA_PSG* psg)
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{
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{
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memset(psg->channels, 0, sizeof(psg->channels));
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memset(psg->channels, 0, sizeof(psg->channels));
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psg->noiseState=1;
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psg->noiseOut = 0;
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psg->noiseOut = 0;
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psg->noiseState = 1;
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}
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}
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void
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void
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@ -54,10 +54,14 @@ render(struct VERA_PSG* psg, int16_t *left, int16_t *right)
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{
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{
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int l = 0;
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int l = 0;
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int r = 0;
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int r = 0;
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for (int i = 0; i < 16; i++) {
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// In FPGA implementation, noise values are generated every system clock and
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// the channel update is run sequentially. So, even if both two channels are
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// fetching a noise value in the same sample, they should have different values
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psg->noiseOut = ((psg->noiseOut << 1) | (psg->noiseState & 1)) & 63;
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psg->noiseOut = ((psg->noiseOut << 1) | (psg->noiseState & 1)) & 63;
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psg->noiseState = (psg->noiseState << 1) | (((psg->noiseState >> 1) ^ (psg->noiseState >> 2) ^ (psg->noiseState >> 4) ^ (psg->noiseState >> 15)) & 1);
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psg->noiseState = (psg->noiseState << 1) | (((psg->noiseState >> 1) ^ (psg->noiseState >> 2) ^ (psg->noiseState >> 4) ^ (psg->noiseState >> 15)) & 1);
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for (int i = 0; i < 16; i++) {
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struct VERAChannel *ch = &psg->channels[i];
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struct VERAChannel *ch = &psg->channels[i];
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unsigned new_phase = (ch->phase + ch->freq) & 0x1FFFF;
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unsigned new_phase = (ch->phase + ch->freq) & 0x1FFFF;
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