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it works
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parent
b39b1c0a25
commit
cd2854d027
1 changed files with 20 additions and 3 deletions
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@ -128,7 +128,7 @@ void DivPlatformGenesis::tick() {
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rWrite(baseAddr+ADDR_SL_RR,(op.rr&15)|(op.sl<<4));
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}
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if (m.hadTl) {
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op.tl=m.tl;
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op.tl=127-m.tl;
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if (isOutput[chan[i].state.alg][j]) {
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rWrite(baseAddr+ADDR_TL,127-(((127-op.tl)*(chan[i].vol&0x7f))/127));
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} else {
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@ -318,6 +318,7 @@ int DivPlatformGenesis::dispatch(DivCommand c) {
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}
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chan[c.chan].keyOn=true;
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chan[c.chan].active=true;
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chan[c.chan].std.init(ins);
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break;
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}
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case DIV_CMD_NOTE_OFF:
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@ -472,8 +473,24 @@ int DivPlatformGenesis::dispatch(DivCommand c) {
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}
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void DivPlatformGenesis::forceIns() {
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for (int i=0; i<10; i++) {
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chan[i].insChanged=true;
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for (int i=0; i<6; i++) {
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for (int j=0; j<4; j++) {
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unsigned short baseAddr=chanOffs[i]|opOffs[j];
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DivInstrumentFM::Operator& op=chan[i].state.op[j];
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if (isOutput[chan[i].state.alg][j]) {
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rWrite(baseAddr+ADDR_TL,127-(((127-op.tl)*(chan[i].vol&0x7f))/127));
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} else {
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rWrite(baseAddr+ADDR_TL,op.tl);
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}
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rWrite(baseAddr+ADDR_MULT_DT,(op.mult&15)|(dtTable[op.dt&7]<<4));
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rWrite(baseAddr+ADDR_RS_AR,(op.ar&31)|(op.rs<<6));
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rWrite(baseAddr+ADDR_AM_DR,(op.dr&31)|(op.am<<7));
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rWrite(baseAddr+ADDR_DT2_D2R,op.d2r&31);
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rWrite(baseAddr+ADDR_SL_RR,(op.rr&15)|(op.sl<<4));
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rWrite(baseAddr+ADDR_SSG,op.ssgEnv&15);
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}
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rWrite(chanOffs[i]+ADDR_FB_ALG,(chan[i].state.alg&7)|(chan[i].state.fb<<3));
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rWrite(chanOffs[i]+ADDR_LRAF,(isMuted[i]?0:(chan[i].pan<<6))|(chan[i].state.fms&7)|((chan[i].state.ams&3)<<4));
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}
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if (dacMode) {
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rWrite(0x2b,0x80);
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