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OPL: implement VGM export fake reset
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1 changed files with 82 additions and 0 deletions
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@ -320,12 +320,94 @@ void DivEngine::performVGMWrite(SafeWriter* w, DivSystem sys, DivRegWrite& write
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// TODO: it's 3:35am
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case DIV_SYSTEM_OPL:
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case DIV_SYSTEM_OPL_DRUMS:
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// disable envelope
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for (int i=0; i<6; i++) {
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w->writeC(0x0b|baseAddr1);
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w->writeC(0x80+i);
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w->writeC(0x0f);
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w->writeC(0x0b|baseAddr1);
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w->writeC(0x88+i);
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w->writeC(0x0f);
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w->writeC(0x0b|baseAddr1);
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w->writeC(0x90+i);
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w->writeC(0x0f);
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}
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// key off + freq reset
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for (int i=0; i<9; i++) {
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w->writeC(0x0b|baseAddr1);
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w->writeC(0xa0+i);
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w->writeC(0);
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w->writeC(0x0b|baseAddr1);
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w->writeC(0xb0+i);
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w->writeC(0);
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}
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break;
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case DIV_SYSTEM_OPL2:
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case DIV_SYSTEM_OPL2_DRUMS:
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// disable envelope
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for (int i=0; i<6; i++) {
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w->writeC(0x0a|baseAddr1);
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w->writeC(0x80+i);
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w->writeC(0x0f);
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w->writeC(0x0a|baseAddr1);
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w->writeC(0x88+i);
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w->writeC(0x0f);
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w->writeC(0x0a|baseAddr1);
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w->writeC(0x90+i);
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w->writeC(0x0f);
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}
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// key off + freq reset
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for (int i=0; i<9; i++) {
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w->writeC(0x0a|baseAddr1);
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w->writeC(0xa0+i);
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w->writeC(0);
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w->writeC(0x0a|baseAddr1);
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w->writeC(0xb0+i);
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w->writeC(0);
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}
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break;
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case DIV_SYSTEM_OPL3:
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case DIV_SYSTEM_OPL3_DRUMS:
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// disable envelope
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for (int i=0; i<6; i++) {
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w->writeC(0x0e|baseAddr1);
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w->writeC(0x80+i);
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w->writeC(0x0f);
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w->writeC(0x0e|baseAddr1);
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w->writeC(0x88+i);
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w->writeC(0x0f);
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w->writeC(0x0e|baseAddr1);
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w->writeC(0x90+i);
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w->writeC(0x0f);
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w->writeC(0x0f|baseAddr1);
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w->writeC(0x80+i);
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w->writeC(0x0f);
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w->writeC(0x0f|baseAddr1);
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w->writeC(0x88+i);
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w->writeC(0x0f);
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w->writeC(0x0f|baseAddr1);
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w->writeC(0x90+i);
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w->writeC(0x0f);
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}
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// key off + freq reset
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for (int i=0; i<9; i++) {
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w->writeC(0x0e|baseAddr1);
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w->writeC(0xa0+i);
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w->writeC(0);
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w->writeC(0x0e|baseAddr1);
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w->writeC(0xb0+i);
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w->writeC(0);
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w->writeC(0x0f|baseAddr1);
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w->writeC(0xa0+i);
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w->writeC(0);
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w->writeC(0x0f|baseAddr1);
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w->writeC(0xb0+i);
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w->writeC(0);
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}
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// reset 4-op
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w->writeC(0x0f|baseAddr1);
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w->writeC(0x04);
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w->writeC(0x00);
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break;
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default:
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break;
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