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OPL: implement VGM export fake reset

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tildearrow 2022-03-30 04:27:11 -05:00
parent cc152bc3d0
commit cccf90d417
1 changed files with 82 additions and 0 deletions
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82
src/engine/vgmOps.cpp
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@ -320,12 +320,94 @@ void DivEngine::performVGMWrite(SafeWriter* w, DivSystem sys, DivRegWrite& write
// TODO: it's 3:35am // TODO: it's 3:35am
case DIV_SYSTEM_OPL: case DIV_SYSTEM_OPL:
case DIV_SYSTEM_OPL_DRUMS: case DIV_SYSTEM_OPL_DRUMS:
// disable envelope
for (int i=0; i<6; i++) {
w->writeC(0x0b|baseAddr1);
w->writeC(0x80+i);
w->writeC(0x0f);
w->writeC(0x0b|baseAddr1);
w->writeC(0x88+i);
w->writeC(0x0f);
w->writeC(0x0b|baseAddr1);
w->writeC(0x90+i);
w->writeC(0x0f);
}
// key off + freq reset
for (int i=0; i<9; i++) {
w->writeC(0x0b|baseAddr1);
w->writeC(0xa0+i);
w->writeC(0);
w->writeC(0x0b|baseAddr1);
w->writeC(0xb0+i);
w->writeC(0);
}
break; break;
case DIV_SYSTEM_OPL2: case DIV_SYSTEM_OPL2:
case DIV_SYSTEM_OPL2_DRUMS: case DIV_SYSTEM_OPL2_DRUMS:
// disable envelope
for (int i=0; i<6; i++) {
w->writeC(0x0a|baseAddr1);
w->writeC(0x80+i);
w->writeC(0x0f);
w->writeC(0x0a|baseAddr1);
w->writeC(0x88+i);
w->writeC(0x0f);
w->writeC(0x0a|baseAddr1);
w->writeC(0x90+i);
w->writeC(0x0f);
}
// key off + freq reset
for (int i=0; i<9; i++) {
w->writeC(0x0a|baseAddr1);
w->writeC(0xa0+i);
w->writeC(0);
w->writeC(0x0a|baseAddr1);
w->writeC(0xb0+i);
w->writeC(0);
}
break; break;
case DIV_SYSTEM_OPL3: case DIV_SYSTEM_OPL3:
case DIV_SYSTEM_OPL3_DRUMS: case DIV_SYSTEM_OPL3_DRUMS:
// disable envelope
for (int i=0; i<6; i++) {
w->writeC(0x0e|baseAddr1);
w->writeC(0x80+i);
w->writeC(0x0f);
w->writeC(0x0e|baseAddr1);
w->writeC(0x88+i);
w->writeC(0x0f);
w->writeC(0x0e|baseAddr1);
w->writeC(0x90+i);
w->writeC(0x0f);
w->writeC(0x0f|baseAddr1);
w->writeC(0x80+i);
w->writeC(0x0f);
w->writeC(0x0f|baseAddr1);
w->writeC(0x88+i);
w->writeC(0x0f);
w->writeC(0x0f|baseAddr1);
w->writeC(0x90+i);
w->writeC(0x0f);
}
// key off + freq reset
for (int i=0; i<9; i++) {
w->writeC(0x0e|baseAddr1);
w->writeC(0xa0+i);
w->writeC(0);
w->writeC(0x0e|baseAddr1);
w->writeC(0xb0+i);
w->writeC(0);
w->writeC(0x0f|baseAddr1);
w->writeC(0xa0+i);
w->writeC(0);
w->writeC(0x0f|baseAddr1);
w->writeC(0xb0+i);
w->writeC(0);
}
// reset 4-op
w->writeC(0x0f|baseAddr1);
w->writeC(0x04);
w->writeC(0x00);
break; break;
default: default:
break; break;