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prepare to add register cheat sheets

This commit is contained in:
tildearrow 2022-02-02 02:14:42 -05:00
parent ed15f01697
commit cbf66b1e62
11 changed files with 253 additions and 0 deletions
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35
src/engine/platform/amiga.cpp
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@ -5,6 +5,41 @@
#define AMIGA_DIVIDER 8 #define AMIGA_DIVIDER 8
#define CHIP_DIVIDER 16 #define CHIP_DIVIDER 16
const char* regCheatSheetAmiga[]={
"DMACON", "96",
"INTENA", "9A",
"ADKCON", "9E",
"AUD0LCH", "A0",
"AUD0LCL", "A2",
"AUD0LEN", "A4",
"AUD0PER", "A6",
"AUD0VOL", "A8",
"AUD0DAT", "AA",
"AUD1LCH", "B0",
"AUD1LCL", "B2",
"AUD1LEN", "B4",
"AUD1PER", "B6",
"AUD1VOL", "B8",
"AUD1DAT", "BA",
"AUD2LCH", "C0",
"AUD2LCL", "C2",
"AUD2LEN", "C4",
"AUD2PER", "C6",
"AUD2VOL", "C8",
"AUD2DAT", "CA",
"AUD3LCH", "D0",
"AUD3LCL", "D2",
"AUD3LEN", "D4",
"AUD3PER", "D6",
"AUD3VOL", "D8",
"AUD3DAT", "DA",
NULL
};
void DivPlatformAmiga::acquire(short* bufL, short* bufR, size_t start, size_t len) { void DivPlatformAmiga::acquire(short* bufL, short* bufR, size_t start, size_t len) {
for (size_t h=start; h<start+len; h++) { for (size_t h=start; h<start+len; h++) {
bufL[h]=0; bufL[h]=0;

24
src/engine/platform/arcade.cpp
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@ -33,6 +33,30 @@ static int orderedOps[4]={
#define rWrite(a,v) if (!skipRegisterWrites) {pendingWrites[a]=v;} #define rWrite(a,v) if (!skipRegisterWrites) {pendingWrites[a]=v;}
#define immWrite(a,v) if (!skipRegisterWrites) {writes.emplace(a,v); if (dumpWrites) {addWrite(a,v);} } #define immWrite(a,v) if (!skipRegisterWrites) {writes.emplace(a,v); if (dumpWrites) {addWrite(a,v);} }
const char* regCheatSheetOPM[]={
"Test", "00",
"NoteCtl", "08",
"NoiseCtl", "0F",
"ClockA1", "10",
"ClockA2", "11",
"ClockB", "12",
"Control", "14",
"LFOFreq", "18",
"AMD_PMD", "19",
"LFOWave", "1B",
"L_R_FB_ALG", "20",
"KC", "28",
"KF", "30",
"PMS_AMS", "38",
"DT_MULT", "40",
"TL", "60",
"KS_AR", "80",
"AM_DR", "A0",
"DT2_SR", "C0",
"SL_RR", "E0",
NULL
};
void DivPlatformArcade::acquire_nuked(short* bufL, short* bufR, size_t start, size_t len) { void DivPlatformArcade::acquire_nuked(short* bufL, short* bufR, size_t start, size_t len) {
static int o[2]; static int o[2];

20
src/engine/platform/ay.cpp
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@ -9,6 +9,26 @@
#define CHIP_DIVIDER 8 #define CHIP_DIVIDER 8
const char* regCheatSheetAY[]={
"FreqL_A", "0",
"FreqH_A", "1",
"FreqL_B", "2",
"FreqH_B", "3",
"FreqL_C", "4",
"FreqH_C", "5",
"FreqNoise", "6",
"Enable", "7",
"Volume_A", "8",
"Volume_B", "9",
"Volume_C", "A",
"FreqL_Env", "B",
"FreqH_Env", "C",
"Control_Env", "D",
"PortA", "E",
"PortB", "F",
NULL
};
void DivPlatformAY8910::acquire(short* bufL, short* bufR, size_t start, size_t len) { void DivPlatformAY8910::acquire(short* bufL, short* bufR, size_t start, size_t len) {
if (ayBufLen<len) { if (ayBufLen<len) {
ayBufLen=len; ayBufLen=len;

32
src/engine/platform/ay8930.cpp
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@ -9,6 +9,38 @@
#define CHIP_DIVIDER 8 #define CHIP_DIVIDER 8
const char* regCheatSheetAY8930[]={
"FreqL_A", "00",
"FreqH_A", "01",
"FreqL_B", "02",
"FreqH_B", "03",
"FreqL_C", "04",
"FreqH_C", "05",
"FreqNoise", "06",
"Enable", "07",
"Volume_A", "08",
"Volume_B", "09",
"Volume_C", "0A",
"FreqL_EnvA", "0B",
"FreqH_EnvA", "0C",
"Control_EnvA", "0D",
"PortA", "0E",
"PortB", "0F",
"FreqL_EnvB", "10",
"FreqH_EnvB", "11",
"FreqL_EnvC", "12",
"FreqH_EnvC", "13",
"Control_EnvB", "14",
"Control_EnvC", "15",
"Duty_A", "16",
"Duty_B", "17",
"Duty_C", "18",
"NoiseAND", "19",
"NoiseOR", "1A",
"TEST", "1F",
NULL
};
void DivPlatformAY8930::acquire(short* bufL, short* bufR, size_t start, size_t len) { void DivPlatformAY8930::acquire(short* bufL, short* bufR, size_t start, size_t len) {
if (ayBufLen<len) { if (ayBufLen<len) {
ayBufLen=len; ayBufLen=len;

33
src/engine/platform/c64.cpp
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@ -6,6 +6,39 @@
#define CHIP_FREQBASE 524288 #define CHIP_FREQBASE 524288
const char* regCheatSheetSID[]={
"FreqL0", "00",
"FreqH0", "01",
"PWL0", "02",
"PWH0", "03",
"Control0", "04",
"AtkDcy0", "05",
"StnRis0", "06",
"FreqL1", "07",
"FreqH1", "08",
"PWL1", "09",
"PWH1", "0A",
"Control1", "0B",
"AtkDcy1", "0C",
"StnRis1", "0D",
"FreqL2", "0E",
"FreqH2", "0F",
"PWL2", "10",
"PWH2", "11",
"Control2", "12",
"AtkDcy2", "13",
"StnRis2", "14",
"FCL", "15",
"FCH", "16",
"FilterRes", "17",
"FilterMode", "18",
"PotX", "19",
"PotY", "1A",
"Osc3", "1B",
"Env3", "1C",
NULL
};
void DivPlatformC64::acquire(short* bufL, short* bufR, size_t start, size_t len) { void DivPlatformC64::acquire(short* bufL, short* bufR, size_t start, size_t len) {
for (size_t i=start; i<start+len; i++) { for (size_t i=start; i<start+len; i++) {
sid.clock(); sid.clock();

31
src/engine/platform/gb.cpp
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@ -7,6 +7,37 @@
#define CHIP_DIVIDER 16 #define CHIP_DIVIDER 16
const char* regCheatSheetGB[]={
"NR10_Sweep", "10",
"NR11_DutyLen", "11",
"NR12_VolEnv", "12",
"NR13_FreqL", "13",
"NR14_FreqH", "14",
"NR21_DutyLen", "16",
"NR22_VolEnv", "17",
"NR23_FreqL", "18",
"NR24_FreqH", "19",
"NR30_WaveOn", "1A",
"NR31_Len", "1B",
"NR32_Vol", "1C",
"NR33_FreqL", "1D",
"NR34_FreqH", "1E",
"NR41_Len", "20",
"NR42_VolEnv", "21",
"NR43_Freq", "22",
"NR44_Control", "23",
"NR50_MasterVol", "24",
"NR51_Toggle", "25",
"NR52_PowerStat", "26",
"Wave", "30",
NULL
};
void DivPlatformGB::acquire(short* bufL, short* bufR, size_t start, size_t len) { void DivPlatformGB::acquire(short* bufL, short* bufR, size_t start, size_t len) {
for (size_t i=start; i<start+len; i++) { for (size_t i=start; i<start+len; i++) {
GB_advance_cycles(gb,16); GB_advance_cycles(gb,16);

24
src/engine/platform/nes.cpp
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@ -8,6 +8,30 @@
#define rWrite(a,v) if (!skipRegisterWrites) {apu_wr_reg(nes,a,v); if (dumpWrites) {addWrite(a,v);} } #define rWrite(a,v) if (!skipRegisterWrites) {apu_wr_reg(nes,a,v); if (dumpWrites) {addWrite(a,v);} }
const char* regCheatSheetNES[]={
"S0Volume", "4000",
"S0Sweep", "4001",
"S0PeriodL", "4002",
"S0PeriodH", "4003",
"S1Volume", "4004",
"S1Sweep", "4005",
"S1PeriodL", "4006",
"S1PeriodH", "4007",
"TRVolume", "4008",
"TRPeriodL", "400A",
"TRPeriodH", "400B",
"NSVolume", "400C",
"NSPeriod", "400E",
"NSLength", "400F",
"DMCControl", "4010",
"DMCLoad", "4011",
"DMCAddr", "4012",
"DMCLength", "4013",
"APUControl", "4015",
"APUFrameCtl", "4017",
NULL
};
void DivPlatformNES::acquire(short* bufL, short* bufR, size_t start, size_t len) { void DivPlatformNES::acquire(short* bufL, short* bufR, size_t start, size_t len) {
for (size_t i=start; i<start+len; i++) { for (size_t i=start; i<start+len; i++) {
if (dacSample!=-1) { if (dacSample!=-1) {

14
src/engine/platform/pce.cpp
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@ -15,6 +15,20 @@
#define CHIP_DIVIDER 32 #define CHIP_DIVIDER 32
const char* regCheatSheetPCE[]={
"Select", "0",
"MasterVol", "1",
"FreqL", "2",
"FreqH", "3",
"DataCtl", "4",
"ChanVol", "5",
"WaveCtl", "6",
"NoiseCtl", "7",
"LFOFreq", "8",
"LFOCtl", "9",
NULL
};
void DivPlatformPCE::acquire(short* bufL, short* bufR, size_t start, size_t len) { void DivPlatformPCE::acquire(short* bufL, short* bufR, size_t start, size_t len) {
for (size_t h=start; h<start+len; h++) { for (size_t h=start; h<start+len; h++) {
// PCM part // PCM part

25
src/engine/platform/saa.cpp
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@ -8,6 +8,31 @@
#define CHIP_DIVIDER 2 #define CHIP_DIVIDER 2
const char* regCheatSheetSAA[]={
"Vol0", "00",
"Vol1", "01",
"Vol2", "02",
"Vol3", "03",
"Vol4", "04",
"Vol5", "05",
"Freq0", "08",
"Freq1", "09",
"Freq2", "0A",
"Freq3", "0B",
"Freq4", "0C",
"Freq5", "0D",
"Octave10", "10",
"Octave32", "11",
"Octave54", "12",
"ToneOn", "14",
"NoiseOn", "15",
"NoiseCtl", "16",
"EnvCtl0", "18",
"EnvCtl1", "19",
"Power", "1C",
NULL
};
void DivPlatformSAA1099::acquire(short* bufL, short* bufR, size_t start, size_t len) { void DivPlatformSAA1099::acquire(short* bufL, short* bufR, size_t start, size_t len) {
if (saaBufLen<len) { if (saaBufLen<len) {
saaBufLen=len; saaBufLen=len;

5
src/engine/platform/sms.cpp
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@ -6,6 +6,11 @@
#define CHIP_DIVIDER 64 #define CHIP_DIVIDER 64
const char* regCheatSheetSN[]={
"DATA", "0",
NULL
};
void DivPlatformSMS::acquire(short* bufL, short* bufR, size_t start, size_t len) { void DivPlatformSMS::acquire(short* bufL, short* bufR, size_t start, size_t len) {
sn->sound_stream_update(bufL+start,len); sn->sound_stream_update(bufL+start,len);
} }

10
src/engine/platform/tia.cpp
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@ -5,6 +5,16 @@
#define rWrite(a,v) if (!skipRegisterWrites) {tia.set(a,v); if (dumpWrites) {addWrite(a,v);} } #define rWrite(a,v) if (!skipRegisterWrites) {tia.set(a,v); if (dumpWrites) {addWrite(a,v);} }
const char* regCheatSheetTIA[]={
"AUDC0", "15",
"AUDC1", "16",
"AUDF0", "17",
"AUDF1", "18",
"AUDV0", "19",
"AUDV1", "1A",
NULL
};
void DivPlatformTIA::acquire(short* bufL, short* bufR, size_t start, size_t len) { void DivPlatformTIA::acquire(short* bufL, short* bufR, size_t start, size_t len) {
tia.process(bufL+start,len); tia.process(bufL+start,len);
} }