Make register view work again

This commit is contained in:
Natt Akuma 2022-03-07 19:08:18 +07:00
parent b8ea64b801
commit bbaf31d0c2

View file

@ -97,6 +97,7 @@ void DivPlatformSwan::acquire(short* bufL, short* bufR, size_t start, size_t len
// the rest // the rest
while (!writes.empty()) { while (!writes.empty()) {
QueuedWrite w=writes.front(); QueuedWrite w=writes.front();
regPool[w.addr]=w.val;
if (w.addr<0x40) ws->SoundWrite(w.addr|0x80,w.val); if (w.addr<0x40) ws->SoundWrite(w.addr|0x80,w.val);
else ws->RAMWrite(w.addr&0x3f,w.val); else ws->RAMWrite(w.addr&0x3f,w.val);
writes.pop(); writes.pop();