add a define for SN noise start value
some SN chips have the start value set to an Atari-like one
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@ -144,6 +144,8 @@
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#define MAX_OUTPUT 0x7fff
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#define NOISE_START 0x8000
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//#define NOISE_START 0x0f35
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sn76496_base_device::sn76496_base_device(
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const char *tag,
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@ -193,7 +195,7 @@ void sn76496_base_device::device_start()
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m_count[i] = 0;
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}
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m_RNG = m_feedback_mask;
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m_RNG = NOISE_START;
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m_output[3] = m_RNG & 1;
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m_current_clock = m_clock_divider-1;
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@ -230,7 +232,7 @@ void sn76496_base_device::write(u8 data)
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{
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r = (data & 0x70) >> 4;
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m_last_register = r;
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if (((m_ncr_style_psg) && (r == 6)) && ((data&0x04) != (m_register[6]&0x04))) m_RNG = m_feedback_mask; // NCR-style PSG resets the LFSR only on a mode write which actually changes the state of bit 2 of register 6
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if (((m_ncr_style_psg) && (r == 6)) && ((data&0x04) != (m_register[6]&0x04))) m_RNG = NOISE_START; // NCR-style PSG resets the LFSR only on a mode write which actually changes the state of bit 2 of register 6
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m_register[r] = (m_register[r] & 0x3f0) | (data & 0x0f);
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}
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else
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@ -269,7 +271,7 @@ void sn76496_base_device::write(u8 data)
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n = m_register[6];
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// N/512,N/1024,N/2048,Tone #3 output
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m_period[3] = ((n&3) == 3)? (m_period[2]<<1) : (1 << (5+(n&3)));
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if (!(m_ncr_style_psg)) m_RNG = m_feedback_mask;
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if (!(m_ncr_style_psg)) m_RNG = NOISE_START;
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}
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break;
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}
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