mirror of
https://github.com/tildearrow/furnace.git
synced 2024-11-27 06:53:01 +00:00
apply new hard reset strategy on all OPN chips
This commit is contained in:
parent
48a1e6a976
commit
b33ea8f0ac
6 changed files with 187 additions and 100 deletions
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@ -47,6 +47,8 @@ class DivPlatformFMBase: public DivDispatch {
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0,2,1,3
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};
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const unsigned int hardResetCycles=127;
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struct FMChannel: public SharedChannel<int> {
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DivInstrumentFM state;
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unsigned char freqH, freqL;
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@ -83,7 +85,6 @@ class DivPlatformFMBase: public DivDispatch {
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unsigned char lastBusy;
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int delay;
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unsigned int hardResetCycles;
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bool flushFirst;
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unsigned char regPool[512];
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@ -124,7 +125,6 @@ class DivPlatformFMBase: public DivDispatch {
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DivDispatch(),
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lastBusy(0),
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delay(0),
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hardResetCycles(0),
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flushFirst(false) {}
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};
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@ -549,6 +549,7 @@ void DivPlatformGenesis::tick(bool sysTick) {
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immWrite(0xf0,i&0xff);
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}
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for (int i=0; i<csmChan; i++) {
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if (i==2 && extMode) continue;
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if ((chan[i].keyOn || chan[i].opMaskChanged) && chan[i].hardReset) {
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if (i<6) {
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immWrite(0x28,(chan[i].opMask<<4)|konOffs[i]);
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@ -1320,8 +1321,6 @@ void DivPlatformGenesis::setFlags(const DivConfig& flags) {
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} else {
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rate=chipClock/36;
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}
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// 2ms
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hardResetCycles=(chipClock/144)/500;
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for (int i=0; i<10; i++) {
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oscBuf[i]->rate=rate;
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}
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@ -411,29 +411,6 @@ void DivPlatformYM2203::tick(bool sysTick) {
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rWrite(baseAddr+ADDR_SSG,op.ssgEnv&15);
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}
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}
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if (chan[i].keyOn || chan[i].keyOff) {
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if (chan[i].hardReset && chan[i].keyOn) {
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for (int j=0; j<4; j++) {
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unsigned short baseAddr=chanOffs[i]|opOffs[j];
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immWrite(baseAddr+ADDR_SL_RR,0x0f);
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immWrite(baseAddr+ADDR_TL,0x7f);
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oldWrites[baseAddr+ADDR_SL_RR]=-1;
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oldWrites[baseAddr+ADDR_TL]=-1;
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//rWrite(baseAddr+ADDR_SL_RR,(op.rr&15)|(op.sl<<4));
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}
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}
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immWrite(0x28,0x00|konOffs[i]);
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if (chan[i].hardReset && chan[i].keyOn) {
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for (int j=0; j<4; j++) {
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unsigned short baseAddr=chanOffs[i]|opOffs[j];
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for (int k=0; k<100; k++) {
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immWrite(baseAddr+ADDR_SL_RR,0x0f);
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}
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}
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}
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chan[i].keyOff=false;
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}
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}
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for (int i=16; i<256; i++) {
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@ -443,6 +420,26 @@ void DivPlatformYM2203::tick(bool sysTick) {
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}
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}
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int hardResetElapsed=0;
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bool mustHardReset=false;
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for (int i=0; i<3; i++) {
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if (i==2 && extMode) continue;
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if (chan[i].keyOn || chan[i].keyOff) {
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immWrite(0x28,0x00|konOffs[i]);
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if (chan[i].hardReset && chan[i].keyOn) {
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mustHardReset=true;
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for (int j=0; j<4; j++) {
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unsigned short baseAddr=chanOffs[i]|opOffs[j];
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oldWrites[baseAddr+ADDR_SL_RR]=-1;
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immWrite(baseAddr+ADDR_SL_RR,0x0f);
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hardResetElapsed++;
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}
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}
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chan[i].keyOff=false;
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}
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}
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for (int i=0; i<3; i++) {
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if (i==2 && extMode) continue;
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if (chan[i].freqChanged) {
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@ -464,14 +461,31 @@ void DivPlatformYM2203::tick(bool sysTick) {
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if (chan[i].freq>0x3fff) chan[i].freq=0x3fff;
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immWrite(chanOffs[i]+ADDR_FREQH,chan[i].freq>>8);
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immWrite(chanOffs[i]+ADDR_FREQ,chan[i].freq&0xff);
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hardResetElapsed+=2;
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chan[i].freqChanged=false;
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}
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if (chan[i].keyOn || chan[i].opMaskChanged) {
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if ((chan[i].keyOn || chan[i].opMaskChanged) && !chan[i].hardReset) {
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immWrite(0x28,(chan[i].opMask<<4)|konOffs[i]);
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hardResetElapsed++;
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chan[i].opMaskChanged=false;
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chan[i].keyOn=false;
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}
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}
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// hard reset handling
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if (mustHardReset) {
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for (unsigned int i=hardResetElapsed; i<hardResetCycles; i++) {
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immWrite(0xf0,i&0xff);
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}
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for (int i=0; i<3; i++) {
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if (i==2 && extMode) continue;
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if ((chan[i].keyOn || chan[i].opMaskChanged) && chan[i].hardReset) {
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immWrite(0x28,(chan[i].opMask<<4)|konOffs[i]);
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chan[i].opMaskChanged=false;
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chan[i].keyOn=false;
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}
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}
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}
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}
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void DivPlatformYM2203::commitState(int ch, DivInstrument* ins) {
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@ -606,29 +606,6 @@ void DivPlatformYM2608::tick(bool sysTick) {
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rWrite(baseAddr+ADDR_SSG,op.ssgEnv&15);
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}
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}
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if (chan[i].keyOn || chan[i].keyOff) {
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if (chan[i].hardReset && chan[i].keyOn) {
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for (int j=0; j<4; j++) {
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unsigned short baseAddr=chanOffs[i]|opOffs[j];
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immWrite(baseAddr+ADDR_SL_RR,0x0f);
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immWrite(baseAddr+ADDR_TL,0x7f);
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oldWrites[baseAddr+ADDR_SL_RR]=-1;
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oldWrites[baseAddr+ADDR_TL]=-1;
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//rWrite(baseAddr+ADDR_SL_RR,(op.rr&15)|(op.sl<<4));
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}
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}
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immWrite(0x28,0x00|konOffs[i]);
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if (chan[i].hardReset && chan[i].keyOn) {
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for (int j=0; j<4; j++) {
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unsigned short baseAddr=chanOffs[i]|opOffs[j];
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for (int k=0; k<100; k++) {
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immWrite(baseAddr+ADDR_SL_RR,0x0f);
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}
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}
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}
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chan[i].keyOff=false;
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}
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}
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for (int i=16; i<512; i++) {
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@ -638,6 +615,26 @@ void DivPlatformYM2608::tick(bool sysTick) {
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}
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}
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int hardResetElapsed=0;
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bool mustHardReset=false;
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for (int i=0; i<6; i++) {
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if (i==2 && extMode) continue;
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if (chan[i].keyOn || chan[i].keyOff) {
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immWrite(0x28,0x00|konOffs[i]);
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if (chan[i].hardReset && chan[i].keyOn) {
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mustHardReset=true;
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for (int j=0; j<4; j++) {
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unsigned short baseAddr=chanOffs[i]|opOffs[j];
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oldWrites[baseAddr+ADDR_SL_RR]=-1;
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immWrite(baseAddr+ADDR_SL_RR,0x0f);
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hardResetElapsed++;
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}
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}
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chan[i].keyOff=false;
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}
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}
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for (int i=0; i<6; i++) {
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if (i==2 && extMode) continue;
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if (chan[i].freqChanged) {
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@ -659,10 +656,12 @@ void DivPlatformYM2608::tick(bool sysTick) {
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if (chan[i].freq>0x3fff) chan[i].freq=0x3fff;
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immWrite(chanOffs[i]+ADDR_FREQH,chan[i].freq>>8);
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immWrite(chanOffs[i]+ADDR_FREQ,chan[i].freq&0xff);
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hardResetElapsed+=2;
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chan[i].freqChanged=false;
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}
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if (chan[i].keyOn || chan[i].opMaskChanged) {
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if ((chan[i].keyOn || chan[i].opMaskChanged) && !chan[i].hardReset) {
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immWrite(0x28,(chan[i].opMask<<4)|konOffs[i]);
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hardResetElapsed++;
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chan[i].opMaskChanged=false;
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chan[i].keyOn=false;
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}
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@ -679,6 +678,7 @@ void DivPlatformYM2608::tick(bool sysTick) {
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if (globalRSSVolume!=(chan[i].std.duty.val&0x3f)) {
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globalRSSVolume=chan[i].std.duty.val&0x3f;
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immWrite(0x11,globalRSSVolume);
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hardResetElapsed++;
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}
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}
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if (chan[i].std.panL.had) {
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@ -691,6 +691,7 @@ void DivPlatformYM2608::tick(bool sysTick) {
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}
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if (!isMuted[i] && (chan[i].std.vol.had || chan[i].std.panL.had)) {
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immWrite(0x18+(i-9),isMuted[i]?0:((chan[i].pan<<6)|chan[i].outVol));
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hardResetElapsed++;
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}
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}
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if (chan[i].keyOff) {
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@ -709,6 +710,7 @@ void DivPlatformYM2608::tick(bool sysTick) {
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if (chan[15].std.vol.had) {
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chan[15].outVol=(chan[15].vol*MIN(chan[15].macroVolMul,chan[15].std.vol.val))/chan[15].macroVolMul;
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immWrite(0x10b,chan[15].outVol);
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hardResetElapsed++;
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}
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if (NEW_ARP_STRAT) {
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@ -735,6 +737,7 @@ void DivPlatformYM2608::tick(bool sysTick) {
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chan[15].pan=chan[15].std.panL.val&3;
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if (!isMuted[15]) {
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immWrite(0x101,(isMuted[15]?0:(chan[15].pan<<6))|2);
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hardResetElapsed++;
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}
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}
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}
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@ -755,12 +758,17 @@ void DivPlatformYM2608::tick(bool sysTick) {
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}
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immWrite(0x109,chan[15].freq&0xff);
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immWrite(0x10a,(chan[15].freq>>8)&0xff);
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hardResetElapsed+=2;
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if (chan[15].keyOn || chan[15].keyOff) {
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if (chan[15].keyOff) immWrite(0x100,0x01); // reset
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if (chan[15].keyOff) {
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immWrite(0x100,0x01); // reset
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hardResetElapsed++;
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}
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if (chan[15].active && chan[15].keyOn && !chan[15].keyOff) {
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if (chan[15].sample>=0 && chan[15].sample<parent->song.sampleLen) {
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DivSample* s=parent->getSample(chan[15].sample);
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immWrite(0x100,(s->isLoopable())?0xb0:0xa0); // start/repeat
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hardResetElapsed++;
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}
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}
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chan[15].keyOn=false;
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@ -771,11 +779,13 @@ void DivPlatformYM2608::tick(bool sysTick) {
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if (writeRSSOff) {
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immWrite(0x10,0x80|writeRSSOff);
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hardResetElapsed++;
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writeRSSOff=0;
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}
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if (writeRSSOn) {
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immWrite(0x10,writeRSSOn);
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hardResetElapsed++;
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writeRSSOn=0;
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}
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@ -785,8 +795,24 @@ void DivPlatformYM2608::tick(bool sysTick) {
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for (DivRegWrite& i: ay->getRegisterWrites()) {
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if (i.addr>15) continue;
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immWrite(i.addr&15,i.val);
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hardResetElapsed++;
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}
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ay->getRegisterWrites().clear();
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// hard reset handling
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if (mustHardReset) {
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for (unsigned int i=hardResetElapsed; i<hardResetCycles; i++) {
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immWrite(0xf0,i&0xff);
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}
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for (int i=0; i<6; i++) {
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if (i==2 && extMode) continue;
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if ((chan[i].keyOn || chan[i].opMaskChanged) && chan[i].hardReset) {
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immWrite(0x28,(chan[i].opMask<<4)|konOffs[i]);
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chan[i].opMaskChanged=false;
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chan[i].keyOn=false;
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}
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}
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}
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}
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void DivPlatformYM2608::commitState(int ch, DivInstrument* ins) {
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@ -539,29 +539,6 @@ void DivPlatformYM2610::tick(bool sysTick) {
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rWrite(baseAddr+ADDR_SSG,op.ssgEnv&15);
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}
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}
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if (chan[i].keyOn || chan[i].keyOff) {
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if (chan[i].hardReset && chan[i].keyOn) {
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for (int j=0; j<4; j++) {
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unsigned short baseAddr=chanOffs[i]|opOffs[j];
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immWrite(baseAddr+ADDR_SL_RR,0x0f);
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immWrite(baseAddr+ADDR_TL,0x7f);
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oldWrites[baseAddr+ADDR_SL_RR]=-1;
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oldWrites[baseAddr+ADDR_TL]=-1;
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//rWrite(baseAddr+ADDR_SL_RR,(op.rr&15)|(op.sl<<4));
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}
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}
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immWrite(0x28,0x00|konOffs[i]);
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if (chan[i].hardReset && chan[i].keyOn) {
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for (int j=0; j<4; j++) {
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unsigned short baseAddr=chanOffs[i]|opOffs[j];
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for (int k=0; k<100; k++) {
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immWrite(baseAddr+ADDR_SL_RR,0x0f);
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}
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}
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}
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chan[i].keyOff=false;
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}
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}
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for (int i=16; i<512; i++) {
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@ -571,6 +548,26 @@ void DivPlatformYM2610::tick(bool sysTick) {
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}
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}
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int hardResetElapsed=0;
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bool mustHardReset=false;
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for (int i=0; i<psgChanOffs; i++) {
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if (i==1 && extMode) continue;
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if (chan[i].keyOn || chan[i].keyOff) {
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immWrite(0x28,0x00|konOffs[i]);
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if (chan[i].hardReset && chan[i].keyOn) {
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mustHardReset=true;
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for (int j=0; j<4; j++) {
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unsigned short baseAddr=chanOffs[i]|opOffs[j];
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oldWrites[baseAddr+ADDR_SL_RR]=-1;
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immWrite(baseAddr+ADDR_SL_RR,0x0f);
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hardResetElapsed++;
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}
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}
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chan[i].keyOff=false;
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}
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}
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for (int i=0; i<psgChanOffs; i++) {
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if (i==1 && extMode) continue;
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if (chan[i].freqChanged) {
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@ -592,10 +589,12 @@ void DivPlatformYM2610::tick(bool sysTick) {
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if (chan[i].freq>0x3fff) chan[i].freq=0x3fff;
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immWrite(chanOffs[i]+ADDR_FREQH,chan[i].freq>>8);
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immWrite(chanOffs[i]+ADDR_FREQ,chan[i].freq&0xff);
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hardResetElapsed+=2;
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chan[i].freqChanged=false;
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}
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if (chan[i].keyOn || chan[i].opMaskChanged) {
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if ((chan[i].keyOn || chan[i].opMaskChanged) && !chan[i].hardReset) {
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immWrite(0x28,(chan[i].opMask<<4)|konOffs[i]);
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hardResetElapsed++;
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chan[i].opMaskChanged=false;
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chan[i].keyOn=false;
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}
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@ -612,6 +611,7 @@ void DivPlatformYM2610::tick(bool sysTick) {
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if (globalADPCMAVolume!=(chan[i].std.duty.val&0x3f)) {
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globalADPCMAVolume=chan[i].std.duty.val&0x3f;
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immWrite(0x101,globalADPCMAVolume);
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hardResetElapsed++;
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}
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}
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if (chan[i].std.panL.had) {
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@ -624,6 +624,7 @@ void DivPlatformYM2610::tick(bool sysTick) {
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}
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if (!isMuted[i] && (chan[i].std.vol.had || chan[i].std.panL.had)) {
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immWrite(0x108+(i-adpcmAChanOffs),isMuted[i]?0:((chan[i].pan<<6)|chan[i].outVol));
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hardResetElapsed++;
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}
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}
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if (chan[i].keyOff) {
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@ -644,6 +645,7 @@ void DivPlatformYM2610::tick(bool sysTick) {
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if (chan[adpcmBChanOffs].std.vol.had) {
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chan[adpcmBChanOffs].outVol=(chan[adpcmBChanOffs].vol*MIN(chan[adpcmBChanOffs].macroVolMul,chan[adpcmBChanOffs].std.vol.val))/chan[adpcmBChanOffs].macroVolMul;
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immWrite(0x1b,chan[adpcmBChanOffs].outVol);
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hardResetElapsed++;
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}
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if (NEW_ARP_STRAT) {
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@ -670,6 +672,7 @@ void DivPlatformYM2610::tick(bool sysTick) {
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chan[adpcmBChanOffs].pan=chan[adpcmBChanOffs].std.panL.val&3;
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if (!isMuted[adpcmBChanOffs]) {
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immWrite(0x11,(isMuted[adpcmBChanOffs]?0:(chan[adpcmBChanOffs].pan<<6)));
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hardResetElapsed++;
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}
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}
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}
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@ -689,13 +692,16 @@ void DivPlatformYM2610::tick(bool sysTick) {
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}
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immWrite(0x19,chan[adpcmBChanOffs].freq&0xff);
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immWrite(0x1a,(chan[adpcmBChanOffs].freq>>8)&0xff);
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hardResetElapsed+=2;
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}
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if (chan[adpcmBChanOffs].keyOn || chan[adpcmBChanOffs].keyOff) {
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immWrite(0x10,0x01); // reset
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hardResetElapsed++;
|
||||
if (chan[adpcmBChanOffs].active && chan[adpcmBChanOffs].keyOn && !chan[adpcmBChanOffs].keyOff) {
|
||||
if (chan[adpcmBChanOffs].sample>=0 && chan[adpcmBChanOffs].sample<parent->song.sampleLen) {
|
||||
DivSample* s=parent->getSample(chan[adpcmBChanOffs].sample);
|
||||
immWrite(0x10,(s->isLoopable())?0x90:0x80); // start/repeat
|
||||
hardResetElapsed++;
|
||||
}
|
||||
}
|
||||
chan[adpcmBChanOffs].keyOn=false;
|
||||
|
@ -706,11 +712,13 @@ void DivPlatformYM2610::tick(bool sysTick) {
|
|||
|
||||
if (writeADPCMAOff) {
|
||||
immWrite(0x100,0x80|writeADPCMAOff);
|
||||
hardResetElapsed++;
|
||||
writeADPCMAOff=0;
|
||||
}
|
||||
|
||||
if (writeADPCMAOn) {
|
||||
immWrite(0x100,writeADPCMAOn);
|
||||
hardResetElapsed++;
|
||||
writeADPCMAOn=0;
|
||||
}
|
||||
|
||||
|
@ -720,8 +728,24 @@ void DivPlatformYM2610::tick(bool sysTick) {
|
|||
for (DivRegWrite& i: ay->getRegisterWrites()) {
|
||||
if (i.addr>15) continue;
|
||||
immWrite(i.addr&15,i.val);
|
||||
hardResetElapsed++;
|
||||
}
|
||||
ay->getRegisterWrites().clear();
|
||||
|
||||
// hard reset handling
|
||||
if (mustHardReset) {
|
||||
for (unsigned int i=hardResetElapsed; i<hardResetCycles; i++) {
|
||||
immWrite(0xf0,i&0xff);
|
||||
}
|
||||
for (int i=0; i<psgChanOffs; i++) {
|
||||
if (i==1 && extMode) continue;
|
||||
if ((chan[i].keyOn || chan[i].opMaskChanged) && chan[i].hardReset) {
|
||||
immWrite(0x28,(chan[i].opMask<<4)|konOffs[i]);
|
||||
chan[i].opMaskChanged=false;
|
||||
chan[i].keyOn=false;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void DivPlatformYM2610::commitState(int ch, DivInstrument* ins) {
|
||||
|
|
|
@ -606,29 +606,6 @@ void DivPlatformYM2610B::tick(bool sysTick) {
|
|||
rWrite(baseAddr+ADDR_SSG,op.ssgEnv&15);
|
||||
}
|
||||
}
|
||||
|
||||
if (chan[i].keyOn || chan[i].keyOff) {
|
||||
if (chan[i].hardReset && chan[i].keyOn) {
|
||||
for (int j=0; j<4; j++) {
|
||||
unsigned short baseAddr=chanOffs[i]|opOffs[j];
|
||||
immWrite(baseAddr+ADDR_SL_RR,0x0f);
|
||||
immWrite(baseAddr+ADDR_TL,0x7f);
|
||||
oldWrites[baseAddr+ADDR_SL_RR]=-1;
|
||||
oldWrites[baseAddr+ADDR_TL]=-1;
|
||||
//rWrite(baseAddr+ADDR_SL_RR,(op.rr&15)|(op.sl<<4));
|
||||
}
|
||||
}
|
||||
immWrite(0x28,0x00|konOffs[i]);
|
||||
if (chan[i].hardReset && chan[i].keyOn) {
|
||||
for (int j=0; j<4; j++) {
|
||||
unsigned short baseAddr=chanOffs[i]|opOffs[j];
|
||||
for (int k=0; k<100; k++) {
|
||||
immWrite(baseAddr+ADDR_SL_RR,0x0f);
|
||||
}
|
||||
}
|
||||
}
|
||||
chan[i].keyOff=false;
|
||||
}
|
||||
}
|
||||
|
||||
for (int i=16; i<512; i++) {
|
||||
|
@ -638,6 +615,26 @@ void DivPlatformYM2610B::tick(bool sysTick) {
|
|||
}
|
||||
}
|
||||
|
||||
int hardResetElapsed=0;
|
||||
bool mustHardReset=false;
|
||||
|
||||
for (int i=0; i<psgChanOffs; i++) {
|
||||
if (i==2 && extMode) continue;
|
||||
if (chan[i].keyOn || chan[i].keyOff) {
|
||||
immWrite(0x28,0x00|konOffs[i]);
|
||||
if (chan[i].hardReset && chan[i].keyOn) {
|
||||
mustHardReset=true;
|
||||
for (int j=0; j<4; j++) {
|
||||
unsigned short baseAddr=chanOffs[i]|opOffs[j];
|
||||
oldWrites[baseAddr+ADDR_SL_RR]=-1;
|
||||
immWrite(baseAddr+ADDR_SL_RR,0x0f);
|
||||
hardResetElapsed++;
|
||||
}
|
||||
}
|
||||
chan[i].keyOff=false;
|
||||
}
|
||||
}
|
||||
|
||||
for (int i=0; i<psgChanOffs; i++) {
|
||||
if (i==2 && extMode) continue;
|
||||
if (chan[i].freqChanged) {
|
||||
|
@ -659,10 +656,12 @@ void DivPlatformYM2610B::tick(bool sysTick) {
|
|||
if (chan[i].freq>0x3fff) chan[i].freq=0x3fff;
|
||||
immWrite(chanOffs[i]+ADDR_FREQH,chan[i].freq>>8);
|
||||
immWrite(chanOffs[i]+ADDR_FREQ,chan[i].freq&0xff);
|
||||
hardResetElapsed+=2;
|
||||
chan[i].freqChanged=false;
|
||||
}
|
||||
if (chan[i].keyOn || chan[i].opMaskChanged) {
|
||||
immWrite(0x28,(chan[i].opMask<<4)|konOffs[i]);
|
||||
hardResetElapsed++;
|
||||
chan[i].opMaskChanged=false;
|
||||
chan[i].keyOn=false;
|
||||
}
|
||||
|
@ -679,6 +678,7 @@ void DivPlatformYM2610B::tick(bool sysTick) {
|
|||
if (globalADPCMAVolume!=(chan[i].std.duty.val&0x3f)) {
|
||||
globalADPCMAVolume=chan[i].std.duty.val&0x3f;
|
||||
immWrite(0x101,globalADPCMAVolume);
|
||||
hardResetElapsed++;
|
||||
}
|
||||
}
|
||||
if (chan[i].std.panL.had) {
|
||||
|
@ -691,6 +691,7 @@ void DivPlatformYM2610B::tick(bool sysTick) {
|
|||
}
|
||||
if (!isMuted[i] && (chan[i].std.vol.had || chan[i].std.panL.had)) {
|
||||
immWrite(0x108+(i-adpcmAChanOffs),isMuted[i]?0:((chan[i].pan<<6)|chan[i].outVol));
|
||||
hardResetElapsed++;
|
||||
}
|
||||
}
|
||||
if (chan[i].keyOff) {
|
||||
|
@ -711,6 +712,7 @@ void DivPlatformYM2610B::tick(bool sysTick) {
|
|||
if (chan[adpcmBChanOffs].std.vol.had) {
|
||||
chan[adpcmBChanOffs].outVol=(chan[adpcmBChanOffs].vol*MIN(chan[adpcmBChanOffs].macroVolMul,chan[adpcmBChanOffs].std.vol.val))/chan[adpcmBChanOffs].macroVolMul;
|
||||
immWrite(0x1b,chan[adpcmBChanOffs].outVol);
|
||||
hardResetElapsed++;
|
||||
}
|
||||
|
||||
if (NEW_ARP_STRAT) {
|
||||
|
@ -737,6 +739,7 @@ void DivPlatformYM2610B::tick(bool sysTick) {
|
|||
chan[adpcmBChanOffs].pan=chan[adpcmBChanOffs].std.panL.val&3;
|
||||
if (!isMuted[adpcmBChanOffs]) {
|
||||
immWrite(0x11,(isMuted[adpcmBChanOffs]?0:(chan[adpcmBChanOffs].pan<<6)));
|
||||
hardResetElapsed++;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
@ -756,13 +759,16 @@ void DivPlatformYM2610B::tick(bool sysTick) {
|
|||
}
|
||||
immWrite(0x19,chan[adpcmBChanOffs].freq&0xff);
|
||||
immWrite(0x1a,(chan[adpcmBChanOffs].freq>>8)&0xff);
|
||||
hardResetElapsed+=2;
|
||||
}
|
||||
if (chan[adpcmBChanOffs].keyOn || chan[adpcmBChanOffs].keyOff) {
|
||||
immWrite(0x10,0x01); // reset
|
||||
hardResetElapsed++;
|
||||
if (chan[adpcmBChanOffs].active && chan[adpcmBChanOffs].keyOn && !chan[adpcmBChanOffs].keyOff) {
|
||||
if (chan[adpcmBChanOffs].sample>=0 && chan[adpcmBChanOffs].sample<parent->song.sampleLen) {
|
||||
DivSample* s=parent->getSample(chan[adpcmBChanOffs].sample);
|
||||
immWrite(0x10,(s->isLoopable())?0x90:0x80); // start/repeat
|
||||
hardResetElapsed++;
|
||||
}
|
||||
}
|
||||
chan[adpcmBChanOffs].keyOn=false;
|
||||
|
@ -773,11 +779,13 @@ void DivPlatformYM2610B::tick(bool sysTick) {
|
|||
|
||||
if (writeADPCMAOff) {
|
||||
immWrite(0x100,0x80|writeADPCMAOff);
|
||||
hardResetElapsed++;
|
||||
writeADPCMAOff=0;
|
||||
}
|
||||
|
||||
if (writeADPCMAOn) {
|
||||
immWrite(0x100,writeADPCMAOn);
|
||||
hardResetElapsed++;
|
||||
writeADPCMAOn=0;
|
||||
}
|
||||
|
||||
|
@ -787,8 +795,24 @@ void DivPlatformYM2610B::tick(bool sysTick) {
|
|||
for (DivRegWrite& i: ay->getRegisterWrites()) {
|
||||
if (i.addr>15) continue;
|
||||
immWrite(i.addr&15,i.val);
|
||||
hardResetElapsed++;
|
||||
}
|
||||
ay->getRegisterWrites().clear();
|
||||
|
||||
// hard reset handling
|
||||
if (mustHardReset) {
|
||||
for (unsigned int i=hardResetElapsed; i<hardResetCycles; i++) {
|
||||
immWrite(0xf0,i&0xff);
|
||||
}
|
||||
for (int i=0; i<psgChanOffs; i++) {
|
||||
if (i==2 && extMode) continue;
|
||||
if ((chan[i].keyOn || chan[i].opMaskChanged) && chan[i].hardReset) {
|
||||
immWrite(0x28,(chan[i].opMask<<4)|konOffs[i]);
|
||||
chan[i].opMaskChanged=false;
|
||||
chan[i].keyOn=false;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void DivPlatformYM2610B::commitState(int ch, DivInstrument* ins) {
|
||||
|
|
Loading…
Reference in a new issue