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Add register sheet for YM2610*

This commit is contained in:
cam900 2022-02-28 04:45:55 +09:00
parent d92b662851
commit ac1c65fd62
4 changed files with 490 additions and 0 deletions
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212
src/engine/platform/ym2610.cpp
View File

@ -32,6 +32,218 @@ static unsigned char konOffs[4]={
#define CHIP_DIVIDER 32
const char* regCheatSheetYM2610[]={
// SSG
"SSG_FreqL_A", "000",
"SSG_FreqH_A", "001",
"SSG_FreqL_B", "002",
"SSG_FreqH_B", "003",
"SSG_FreqL_C", "004",
"SSG_FreqH_C", "005",
"SSG_FreqNoise", "006",
"SSG_Enable", "007",
"SSG_Volume_A", "008",
"SSG_Volume_B", "009",
"SSG_Volume_C", "00A",
"SSG_FreqL_Env", "00B",
"SSG_FreqH_Env", "00C",
"SSG_Control_Env", "00D",
// ADPCM-B
"ADPCMB_Control", "010",
"ADPCMB_L_R", "011",
"ADPCMB_StartL", "012",
"ADPCMB_StartH", "013",
"ADPCMB_EndL", "014",
"ADPCMB_EndH", "015",
"ADPCMB_FreqL", "019",
"ADPCMB_FreqH", "01A",
"ADPCMB_Volume", "01B",
"ADPCM_Flag", "01C",
// FM (Common)
"FM_Test", "021",
"FM_LFOFreq", "022",
"ClockA1", "024",
"ClockA2", "025",
"ClockB", "026",
"FM_Control", "027",
"FM_NoteCtl", "028",
// FM (Channel 1-2)
"FM1_Op1_DT_MULT", "031",
"FM2_Op1_DT_MULT", "032",
"FM1_Op2_DT_MULT", "035",
"FM2_Op2_DT_MULT", "036",
"FM1_Op3_DT_MULT", "039",
"FM2_Op3_DT_MULT", "03A",
"FM1_Op4_DT_MULT", "03D",
"FM2_Op4_DT_MULT", "03E",
"FM1_Op1_TL", "041",
"FM2_Op1_TL", "042",
"FM1_Op2_TL", "045",
"FM2_Op2_TL", "046",
"FM1_Op3_TL", "049",
"FM2_Op3_TL", "04A",
"FM1_Op4_TL", "04D",
"FM2_Op4_TL", "04E",
"FM1_Op1_KS_AR", "051",
"FM2_Op1_KS_AR", "052",
"FM1_Op2_KS_AR", "055",
"FM2_Op2_KS_AR", "056",
"FM1_Op3_KS_AR", "059",
"FM2_Op3_KS_AR", "05A",
"FM1_Op4_KS_AR", "05D",
"FM2_Op4_KS_AR", "05E",
"FM1_Op1_AM_DR", "061",
"FM2_Op1_AM_DR", "062",
"FM1_Op2_AM_DR", "065",
"FM2_Op2_AM_DR", "066",
"FM1_Op3_AM_DR", "069",
"FM2_Op3_AM_DR", "06A",
"FM1_Op4_AM_DR", "06D",
"FM2_Op4_AM_DR", "06E",
"FM1_Op1_SR", "071",
"FM2_Op1_SR", "072",
"FM1_Op2_SR", "075",
"FM2_Op2_SR", "076",
"FM1_Op3_SR", "079",
"FM2_Op3_SR", "07A",
"FM1_Op4_SR", "07D",
"FM2_Op4_SR", "07E",
"FM1_Op1_SL_RR", "081",
"FM2_Op1_SL_RR", "082",
"FM1_Op2_SL_RR", "085",
"FM2_Op2_SL_RR", "086",
"FM1_Op3_SL_RR", "089",
"FM2_Op3_SL_RR", "08A",
"FM1_Op4_SL_RR", "08D",
"FM2_Op4_SL_RR", "08E",
"FM1_Op1_SSG_EG", "091",
"FM2_Op1_SSG_EG", "092",
"FM1_Op2_SSG_EG", "095",
"FM2_Op2_SSG_EG", "096",
"FM1_Op3_SSG_EG", "099",
"FM2_Op3_SSG_EG", "09A",
"FM1_Op4_SSG_EG", "09D",
"FM2_Op4_SSG_EG", "09E",
"FM1_FNum1", "0A1",
"FM2_(Op1)FNum1", "0A2",
"FM1_FNum2", "0A5",
"FM2_(Op1)FNum2", "0A6",
"FM2_Op2_FNum1", "0A8",
"FM2_Op3_FNum1", "0A9",
"FM2_Op4_FNum1", "0AA",
"FM2_Op2_FNum2", "0AC",
"FM2_Op3_FNum2", "0AD",
"FM2_Op4_FNum2", "0AE",
"FM1_FB_ALG", "0B1",
"FM2_FB_ALG", "0B2",
"FM1_Pan_LFO", "0B5",
"FM2_Pan_LFO", "0B6",
// ADPCM-A
"ADPCMA_Control", "100",
"ADPCMA_MVol", "101",
"ADPCMA_Test", "102",
"ADPCMA_Ch1_Vol", "108",
"ADPCMA_Ch2_Vol", "109",
"ADPCMA_Ch3_Vol", "10A",
"ADPCMA_Ch4_Vol", "10B",
"ADPCMA_Ch5_Vol", "10C",
"ADPCMA_Ch6_Vol", "10D",
"ADPCMA_Ch1_StL", "110",
"ADPCMA_Ch2_StL", "111",
"ADPCMA_Ch3_StL", "112",
"ADPCMA_Ch4_StL", "113",
"ADPCMA_Ch5_StL", "114",
"ADPCMA_Ch6_StL", "115",
"ADPCMA_Ch1_StH", "118",
"ADPCMA_Ch2_StH", "119",
"ADPCMA_Ch3_StH", "11A",
"ADPCMA_Ch4_StH", "11B",
"ADPCMA_Ch5_StH", "11C",
"ADPCMA_Ch6_StH", "11D",
"ADPCMA_Ch1_EdL", "120",
"ADPCMA_Ch2_EdL", "121",
"ADPCMA_Ch3_EdL", "122",
"ADPCMA_Ch4_EdL", "123",
"ADPCMA_Ch5_EdL", "124",
"ADPCMA_Ch6_EdL", "125",
"ADPCMA_Ch1_EdH", "128",
"ADPCMA_Ch2_EdH", "129",
"ADPCMA_Ch3_EdH", "12A",
"ADPCMA_Ch4_EdH", "12B",
"ADPCMA_Ch5_EdH", "12C",
"ADPCMA_Ch6_EdH", "12D",
// FM (Channel 3-4)
"FM3_Op1_DT_MULT", "131",
"FM4_Op1_DT_MULT", "132",
"FM3_Op2_DT_MULT", "135",
"FM4_Op2_DT_MULT", "136",
"FM3_Op3_DT_MULT", "139",
"FM4_Op3_DT_MULT", "13A",
"FM3_Op4_DT_MULT", "13D",
"FM4_Op4_DT_MULT", "13E",
"FM3_Op1_TL", "141",
"FM4_Op1_TL", "142",
"FM3_Op2_TL", "145",
"FM4_Op2_TL", "146",
"FM3_Op3_TL", "149",
"FM4_Op3_TL", "14A",
"FM3_Op4_TL", "14D",
"FM4_Op4_TL", "14E",
"FM3_Op1_KS_AR", "151",
"FM4_Op1_KS_AR", "152",
"FM3_Op2_KS_AR", "155",
"FM4_Op2_KS_AR", "156",
"FM3_Op3_KS_AR", "159",
"FM4_Op3_KS_AR", "15A",
"FM3_Op4_KS_AR", "15D",
"FM4_Op4_KS_AR", "15E",
"FM3_Op1_AM_DR", "161",
"FM4_Op1_AM_DR", "162",
"FM3_Op2_AM_DR", "165",
"FM4_Op2_AM_DR", "166",
"FM3_Op3_AM_DR", "169",
"FM4_Op3_AM_DR", "16A",
"FM3_Op4_AM_DR", "16D",
"FM4_Op4_AM_DR", "16E",
"FM3_Op1_SR", "171",
"FM4_Op1_SR", "172",
"FM3_Op2_SR", "175",
"FM4_Op2_SR", "176",
"FM3_Op3_SR", "179",
"FM4_Op3_SR", "17A",
"FM3_Op4_SR", "17D",
"FM4_Op4_SR", "17E",
"FM3_Op1_SL_RR", "181",
"FM4_Op1_SL_RR", "182",
"FM3_Op2_SL_RR", "185",
"FM4_Op2_SL_RR", "186",
"FM3_Op3_SL_RR", "189",
"FM4_Op3_SL_RR", "18A",
"FM3_Op4_SL_RR", "18D",
"FM4_Op4_SL_RR", "18E",
"FM3_Op1_SSG_EG", "191",
"FM4_Op1_SSG_EG", "192",
"FM3_Op2_SSG_EG", "195",
"FM4_Op2_SSG_EG", "196",
"FM3_Op3_SSG_EG", "199",
"FM4_Op3_SSG_EG", "19A",
"FM3_Op4_SSG_EG", "19D",
"FM4_Op4_SSG_EG", "19E",
"FM3_FNum1", "1A1",
"FM4_FNum1", "1A2",
"FM3_FNum2", "1A5",
"FM4_FNum2", "1A6",
"FM3_FB_ALG", "1B1",
"FM4_FB_ALG", "1B2",
"FM3_Pan_LFO", "1B5",
"FM4_Pan_LFO", "1B6",
NULL
};
const char** DivPlatformYM2610::getRegisterSheet() {
return regCheatSheetYM2610;
}
const char* DivPlatformYM2610::getEffectName(unsigned char effect) {
switch (effect) {
case 0x10:

1
src/engine/platform/ym2610.h
View File

@ -127,6 +127,7 @@ class DivPlatformYM2610: public DivDispatch {
void notifyInsDeletion(void* ins);
void poke(unsigned int addr, unsigned short val);
void poke(std::vector<DivRegWrite>& wlist);
const char** getRegisterSheet();
const char* getEffectName(unsigned char effect);
int init(DivEngine* parent, int channels, int sugRate, unsigned int flags);
void quit();

276
src/engine/platform/ym2610b.cpp
View File

@ -32,6 +32,282 @@ static unsigned char konOffs[6]={
#define CHIP_DIVIDER 32
const char* regCheatSheetYM2610B[]={
// SSG
"SSG_FreqL_A", "000",
"SSG_FreqH_A", "001",
"SSG_FreqL_B", "002",
"SSG_FreqH_B", "003",
"SSG_FreqL_C", "004",
"SSG_FreqH_C", "005",
"SSG_FreqNoise", "006",
"SSG_Enable", "007",
"SSG_Volume_A", "008",
"SSG_Volume_B", "009",
"SSG_Volume_C", "00A",
"SSG_FreqL_Env", "00B",
"SSG_FreqH_Env", "00C",
"SSG_Control_Env", "00D",
// ADPCM-B
"ADPCMB_Control", "010",
"ADPCMB_L_R", "011",
"ADPCMB_StartL", "012",
"ADPCMB_StartH", "013",
"ADPCMB_EndL", "014",
"ADPCMB_EndH", "015",
"ADPCMB_FreqL", "019",
"ADPCMB_FreqH", "01A",
"ADPCMB_Volume", "01B",
"ADPCM_Flag", "01C",
// FM (Common)
"FM_Test", "021",
"FM_LFOFreq", "022",
"ClockA1", "024",
"ClockA2", "025",
"ClockB", "026",
"FM_Control", "027",
"FM_NoteCtl", "028",
// FM (Channel 1-3)
"FM1_Op1_DT_MULT", "030",
"FM2_Op1_DT_MULT", "031",
"FM3_Op1_DT_MULT", "032",
"FM1_Op2_DT_MULT", "034",
"FM2_Op2_DT_MULT", "035",
"FM3_Op2_DT_MULT", "036",
"FM1_Op3_DT_MULT", "038",
"FM2_Op3_DT_MULT", "039",
"FM3_Op3_DT_MULT", "03A",
"FM1_Op4_DT_MULT", "03C",
"FM2_Op4_DT_MULT", "03D",
"FM3_Op4_DT_MULT", "03E",
"FM1_Op1_TL", "040",
"FM2_Op1_TL", "041",
"FM3_Op1_TL", "042",
"FM1_Op2_TL", "044",
"FM2_Op2_TL", "045",
"FM3_Op2_TL", "046",
"FM1_Op3_TL", "048",
"FM2_Op3_TL", "049",
"FM3_Op3_TL", "04A",
"FM1_Op4_TL", "04C",
"FM2_Op4_TL", "04D",
"FM3_Op4_TL", "04E",
"FM1_Op1_KS_AR", "050",
"FM2_Op1_KS_AR", "051",
"FM3_Op1_KS_AR", "052",
"FM1_Op2_KS_AR", "054",
"FM2_Op2_KS_AR", "055",
"FM3_Op2_KS_AR", "056",
"FM1_Op3_KS_AR", "058",
"FM2_Op3_KS_AR", "059",
"FM3_Op3_KS_AR", "05A",
"FM1_Op4_KS_AR", "05C",
"FM2_Op4_KS_AR", "05D",
"FM3_Op4_KS_AR", "05E",
"FM1_Op1_AM_DR", "060",
"FM2_Op1_AM_DR", "061",
"FM3_Op1_AM_DR", "062",
"FM1_Op2_AM_DR", "064",
"FM2_Op2_AM_DR", "065",
"FM3_Op2_AM_DR", "066",
"FM1_Op3_AM_DR", "068",
"FM2_Op3_AM_DR", "069",
"FM3_Op3_AM_DR", "06A",
"FM1_Op4_AM_DR", "06C",
"FM2_Op4_AM_DR", "06D",
"FM3_Op4_AM_DR", "06E",
"FM1_Op1_SR", "070",
"FM2_Op1_SR", "071",
"FM3_Op1_SR", "072",
"FM1_Op2_SR", "074",
"FM2_Op2_SR", "075",
"FM3_Op2_SR", "076",
"FM1_Op3_SR", "078",
"FM2_Op3_SR", "079",
"FM3_Op3_SR", "07A",
"FM1_Op4_SR", "07C",
"FM2_Op4_SR", "07D",
"FM3_Op4_SR", "07E",
"FM1_Op1_SL_RR", "080",
"FM2_Op1_SL_RR", "081",
"FM3_Op1_SL_RR", "082",
"FM1_Op2_SL_RR", "084",
"FM2_Op2_SL_RR", "085",
"FM3_Op2_SL_RR", "086",
"FM1_Op3_SL_RR", "088",
"FM2_Op3_SL_RR", "089",
"FM3_Op3_SL_RR", "08A",
"FM1_Op4_SL_RR", "08C",
"FM2_Op4_SL_RR", "08D",
"FM3_Op4_SL_RR", "08E",
"FM1_Op1_SSG_EG", "090",
"FM2_Op1_SSG_EG", "091",
"FM3_Op1_SSG_EG", "092",
"FM1_Op2_SSG_EG", "094",
"FM2_Op2_SSG_EG", "095",
"FM3_Op2_SSG_EG", "096",
"FM1_Op3_SSG_EG", "098",
"FM2_Op3_SSG_EG", "099",
"FM3_Op3_SSG_EG", "09A",
"FM1_Op4_SSG_EG", "09C",
"FM2_Op4_SSG_EG", "09D",
"FM3_Op4_SSG_EG", "09E",
"FM1_FNum1", "0A0",
"FM2_FNum1", "0A1",
"FM3_(Op1)FNum1", "0A2",
"FM1_FNum2", "0A4",
"FM2_FNum2", "0A5",
"FM3_(Op1)FNum2", "0A6",
"FM3_Op2_FNum1", "0A8",
"FM3_Op3_FNum1", "0A9",
"FM3_Op4_FNum1", "0AA",
"FM3_Op2_FNum2", "0AC",
"FM3_Op3_FNum2", "0AD",
"FM3_Op4_FNum2", "0AE",
"FM1_FB_ALG", "0B0",
"FM2_FB_ALG", "0B1",
"FM3_FB_ALG", "0B2",
"FM1_Pan_LFO", "0B4",
"FM2_Pan_LFO", "0B5",
"FM3_Pan_LFO", "0B6",
// ADPCM-A
"ADPCMA_Control", "100",
"ADPCMA_MVol", "101",
"ADPCMA_Test", "102",
"ADPCMA_Ch1_Vol", "108",
"ADPCMA_Ch2_Vol", "109",
"ADPCMA_Ch3_Vol", "10A",
"ADPCMA_Ch4_Vol", "10B",
"ADPCMA_Ch5_Vol", "10C",
"ADPCMA_Ch6_Vol", "10D",
"ADPCMA_Ch1_StL", "110",
"ADPCMA_Ch2_StL", "111",
"ADPCMA_Ch3_StL", "112",
"ADPCMA_Ch4_StL", "113",
"ADPCMA_Ch5_StL", "114",
"ADPCMA_Ch6_StL", "115",
"ADPCMA_Ch1_StH", "118",
"ADPCMA_Ch2_StH", "119",
"ADPCMA_Ch3_StH", "11A",
"ADPCMA_Ch4_StH", "11B",
"ADPCMA_Ch5_StH", "11C",
"ADPCMA_Ch6_StH", "11D",
"ADPCMA_Ch1_EdL", "120",
"ADPCMA_Ch2_EdL", "121",
"ADPCMA_Ch3_EdL", "122",
"ADPCMA_Ch4_EdL", "123",
"ADPCMA_Ch5_EdL", "124",
"ADPCMA_Ch6_EdL", "125",
"ADPCMA_Ch1_EdH", "128",
"ADPCMA_Ch2_EdH", "129",
"ADPCMA_Ch3_EdH", "12A",
"ADPCMA_Ch4_EdH", "12B",
"ADPCMA_Ch5_EdH", "12C",
"ADPCMA_Ch6_EdH", "12D",
// FM (Channel 4-6)
"FM4_Op1_DT_MULT", "130",
"FM5_Op1_DT_MULT", "131",
"FM6_Op1_DT_MULT", "132",
"FM4_Op2_DT_MULT", "134",
"FM5_Op2_DT_MULT", "135",
"FM6_Op2_DT_MULT", "136",
"FM4_Op3_DT_MULT", "138",
"FM5_Op3_DT_MULT", "139",
"FM6_Op3_DT_MULT", "13A",
"FM4_Op4_DT_MULT", "13C",
"FM5_Op4_DT_MULT", "13D",
"FM6_Op4_DT_MULT", "13E",
"FM4_Op1_TL", "140",
"FM5_Op1_TL", "141",
"FM6_Op1_TL", "142",
"FM4_Op2_TL", "144",
"FM5_Op2_TL", "145",
"FM6_Op2_TL", "146",
"FM4_Op3_TL", "148",
"FM5_Op3_TL", "149",
"FM6_Op3_TL", "14A",
"FM4_Op4_TL", "14C",
"FM5_Op4_TL", "14D",
"FM6_Op4_TL", "14E",
"FM4_Op1_KS_AR", "150",
"FM5_Op1_KS_AR", "151",
"FM6_Op1_KS_AR", "152",
"FM4_Op2_KS_AR", "154",
"FM5_Op2_KS_AR", "155",
"FM6_Op2_KS_AR", "156",
"FM4_Op3_KS_AR", "158",
"FM5_Op3_KS_AR", "159",
"FM6_Op3_KS_AR", "15A",
"FM4_Op4_KS_AR", "15C",
"FM5_Op4_KS_AR", "15D",
"FM6_Op4_KS_AR", "15E",
"FM4_Op1_AM_DR", "160",
"FM5_Op1_AM_DR", "161",
"FM6_Op1_AM_DR", "162",
"FM4_Op2_AM_DR", "164",
"FM5_Op2_AM_DR", "165",
"FM6_Op2_AM_DR", "166",
"FM4_Op3_AM_DR", "168",
"FM5_Op3_AM_DR", "169",
"FM6_Op3_AM_DR", "16A",
"FM4_Op4_AM_DR", "16C",
"FM5_Op4_AM_DR", "16D",
"FM6_Op4_AM_DR", "16E",
"FM4_Op1_SR", "170",
"FM5_Op1_SR", "171",
"FM6_Op1_SR", "172",
"FM4_Op2_SR", "174",
"FM5_Op2_SR", "175",
"FM6_Op2_SR", "176",
"FM4_Op3_SR", "178",
"FM5_Op3_SR", "179",
"FM6_Op3_SR", "17A",
"FM4_Op4_SR", "17C",
"FM5_Op4_SR", "17D",
"FM6_Op4_SR", "17E",
"FM4_Op1_SL_RR", "180",
"FM5_Op1_SL_RR", "181",
"FM6_Op1_SL_RR", "182",
"FM4_Op2_SL_RR", "184",
"FM5_Op2_SL_RR", "185",
"FM6_Op2_SL_RR", "186",
"FM4_Op3_SL_RR", "188",
"FM5_Op3_SL_RR", "189",
"FM6_Op3_SL_RR", "18A",
"FM4_Op4_SL_RR", "18C",
"FM5_Op4_SL_RR", "18D",
"FM6_Op4_SL_RR", "18E",
"FM4_Op1_SSG_EG", "190",
"FM5_Op1_SSG_EG", "191",
"FM6_Op1_SSG_EG", "192",
"FM4_Op2_SSG_EG", "194",
"FM5_Op2_SSG_EG", "195",
"FM6_Op2_SSG_EG", "196",
"FM4_Op3_SSG_EG", "198",
"FM5_Op3_SSG_EG", "199",
"FM6_Op3_SSG_EG", "19A",
"FM4_Op4_SSG_EG", "19C",
"FM5_Op4_SSG_EG", "19D",
"FM6_Op4_SSG_EG", "19E",
"FM4_FNum1", "1A0",
"FM5_FNum1", "1A1",
"FM6_FNum1", "1A2",
"FM4_FNum2", "1A4",
"FM5_FNum2", "1A5",
"FM6_FNum2", "1A6",
"FM4_FB_ALG", "1B0",
"FM5_FB_ALG", "1B1",
"FM6_FB_ALG", "1B2",
"FM4_Pan_LFO", "1B4",
"FM5_Pan_LFO", "1B5",
"FM6_Pan_LFO", "1B6",
NULL
};
const char** DivPlatformYM2610B::getRegisterSheet() {
return regCheatSheetYM2610B;
}
const char* DivPlatformYM2610B::getEffectName(unsigned char effect) {
switch (effect) {
case 0x10:

1
src/engine/platform/ym2610b.h
View File

@ -120,6 +120,7 @@ class DivPlatformYM2610B: public DivDispatch {
void notifyInsDeletion(void* ins);
void poke(unsigned int addr, unsigned short val);
void poke(std::vector<DivRegWrite>& wlist);
const char** getRegisterSheet();
const char* getEffectName(unsigned char effect);
int init(DivEngine* parent, int channels, int sugRate, unsigned int flags);
void quit();