C219: chip config and proper clock rate

This commit is contained in:
tildearrow 2023-08-28 18:37:35 -05:00
parent 35faa8c23c
commit 9cb239438e
3 changed files with 22 additions and 3 deletions

View File

@ -639,10 +639,26 @@ void DivPlatformC140::set219(bool is_219) {
totalChans=is219?16:24;
}
int DivPlatformC140::getClockRangeMin() {
if (is219) return 1000000;
return MIN_CUSTOM_CLOCK;
}
int DivPlatformC140::getClockRangeMax() {
if (is219) return 100000000;
return MAX_CUSTOM_CLOCK;
}
void DivPlatformC140::setFlags(const DivConfig& flags) {
chipClock=32000*256; // 8.192MHz and 12.288MHz input, verified from Assault Schematics
CHECK_CUSTOM_CLOCK;
rate=chipClock/192;
if (is219) {
chipClock=50113000; // 50.113MHz clock input in Namco NA-1/NA-2 PCB
CHECK_CUSTOM_CLOCK;
rate=chipClock/1136; // assumed as ~44100hz
} else {
chipClock=32000*256; // 8.192MHz and 12.288MHz input, verified from Assault Schematics
CHECK_CUSTOM_CLOCK;
rate=chipClock/192;
}
for (int i=0; i<totalChans; i++) {
oscBuf[i]->rate=rate;
}

View File

@ -106,6 +106,8 @@ class DivPlatformC140: public DivDispatch {
size_t getSampleMemUsage(int index = 0);
bool isSampleLoaded(int index, int sample);
void renderSamples(int chipID);
int getClockRangeMin();
int getClockRangeMax();
void set219(bool is_219);
void setFlags(const DivConfig& flags);
int init(DivEngine* parent, int channels, int sugRate, const DivConfig& flags);

View File

@ -2099,6 +2099,7 @@ bool FurnaceGUI::drawSysConf(int chan, DivSystem type, DivConfig& flags, bool mo
case DIV_SYSTEM_PV1000:
case DIV_SYSTEM_VERA:
case DIV_SYSTEM_C140:
case DIV_SYSTEM_C219:
break;
case DIV_SYSTEM_YMU759:
supportsCustomRate=false;