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Fix compile (again)
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parent
5473b8722d
commit
8bc545c8ab
3 changed files with 30 additions and 15 deletions
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@ -22,6 +22,21 @@
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#include "fmsharedbase.h"
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#define rWrite(a,v) if (!skipRegisterWrites) {pendingWrites[a]=v;}
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#define immWrite(a,v) if (!skipRegisterWrites) {writes.push_back(QueuedWrite(a,v)); if (dumpWrites) {addWrite(a,v);} }
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#define urgentWrite(a,v) if (!skipRegisterWrites) { \
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if (writes.empty()) { \
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writes.push_back(QueuedWrite(a,v)); \
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} else if (writes.size()>16 || writes.front().addrOrVal) { \
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writes.push_back(QueuedWrite(a,v)); \
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} else { \
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writes.push_front(QueuedWrite(a,v)); \
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} \
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if (dumpWrites) { \
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addWrite(a,v); \
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} \
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}
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#define NOTE_LINEAR(x) (((x)<<6)+baseFreqOff+log2(parent->song.tuning/440.0)*12.0*64.0)
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class DivPlatformOPMBase: public DivPlatformFMBase {
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@ -22,6 +22,21 @@
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#include "fmsharedbase.h"
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#define rWrite(a,v) if (!skipRegisterWrites) {pendingWrites[a]=v;}
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#define immWrite(a,v) if (!skipRegisterWrites) {writes.push_back(QueuedWrite(a,v)); if (dumpWrites) {addWrite(a,v);} }
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#define urgentWrite(a,v) if (!skipRegisterWrites) { \
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if (writes.empty()) { \
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writes.push_back(QueuedWrite(a,v)); \
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} else if (writes.size()>16 || writes.front().addrOrVal) { \
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writes.push_back(QueuedWrite(a,v)); \
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} else { \
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writes.push_front(QueuedWrite(a,v)); \
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} \
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if (dumpWrites) { \
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addWrite(a,v); \
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} \
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}
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#define CHIP_FREQBASE fmFreqBase
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#define CHIP_DIVIDER fmDivBase
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@ -65,19 +65,4 @@ class DivPlatformFMBase: public DivDispatch {
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delay(0) {}
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};
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#define rWrite(a,v) if (!skipRegisterWrites) {pendingWrites[a]=v;}
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#define immWrite(a,v) if (!skipRegisterWrites) {writes.push_back(QueuedWrite(a,v)); if (dumpWrites) {addWrite(a,v);} }
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#define urgentWrite(a,v) if (!skipRegisterWrites) { \
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if (writes.empty()) { \
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writes.push_back(QueuedWrite(a,v)); \
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} else if (writes.size()>16 || writes.front().addrOrVal) { \
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writes.push_back(QueuedWrite(a,v)); \
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} else { \
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writes.push_front(QueuedWrite(a,v)); \
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} \
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if (dumpWrites) { \
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addWrite(a,v); \
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} \
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}
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#endif
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