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prepare for writing register dumps

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tildearrow 2022-01-17 13:29:35 -05:00
parent 871a417e25
commit 8b89f1b516
14 changed files with 47 additions and 35 deletions
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4
src/engine/dispatch.h
View file

@ -6,6 +6,8 @@
#define ONE_SEMITONE 2200
#define addWrite(a,v) regWrites.push_back(DivRegWrite(a,v));
enum DivDispatchCmds {
DIV_CMD_NOTE_ON=0,
DIV_CMD_NOTE_OFF,
@ -108,6 +110,8 @@ struct DivRegWrite {
*/
unsigned int addr;
unsigned char val;
DivRegWrite(unsigned int a, unsigned char v):
addr(a), val(v) {}
};
class DivEngine;

7
src/engine/engine.cpp
View file

@ -2114,6 +2114,13 @@ SafeWriter* DivEngine::saveDMF() {
return w;
}
SafeWriter* DivEngine::saveVGM() {
isBusy.lock();
// play the song ourselves
isBusy.unlock();
return NULL;
}
#ifdef _WIN32
#define CONFIG_FILE "\\furnace.cfg"
#else

2
src/engine/platform/arcade.cpp
View file

@ -29,7 +29,7 @@ static int orderedOps[4]={
};
#define rWrite(a,v) if (!skipRegisterWrites) {pendingWrites[a]=v;}
#define immWrite(a,v) if (!skipRegisterWrites) {writes.emplace(a,v);}
#define immWrite(a,v) if (!skipRegisterWrites) {writes.emplace(a,v); if (dumpWrites) {addWrite(a,v);} }
void DivPlatformArcade::acquire_nuked(short* bufL, short* bufR, size_t start, size_t len) {
static int o[2];

2
src/engine/platform/ay.cpp
View file

@ -5,7 +5,7 @@
#include <math.h>
#define rWrite(a,v) if (!skipRegisterWrites) {pendingWrites[a]=v;}
#define immWrite(a,v) if (!skipRegisterWrites) {writes.emplace(a,v);}
#define immWrite(a,v) if (!skipRegisterWrites) {writes.emplace(a,v); if (dumpWrites) {addWrite(a,v);} }
#define PSG_FREQ_BASE 6848.0f

2
src/engine/platform/ay8930.cpp
View file

@ -5,7 +5,7 @@
#include <math.h>
#define rWrite(a,v) if (!skipRegisterWrites) {pendingWrites[a]=v;}
#define immWrite(a,v) if (!skipRegisterWrites) {writes.emplace(a,v);}
#define immWrite(a,v) if (!skipRegisterWrites) {writes.emplace(a,v); if (dumpWrites) {addWrite(a,v);} }
#define PSG_FREQ_BASE 6848.0f

2
src/engine/platform/c64.cpp
View file

@ -4,7 +4,7 @@
#define FREQ_BASE 277.0f
#define rWrite(a,v) if (!skipRegisterWrites) {sid.write(a,v);}
#define rWrite(a,v) if (!skipRegisterWrites) {sid.write(a,v); if (dumpWrites) {addWrite(a,v);} }
void DivPlatformC64::acquire(short* bufL, short* bufR, size_t start, size_t len) {
for (size_t i=start; i<start+len; i++) {

3
src/engine/platform/gb.cpp
View file

@ -2,8 +2,7 @@
#include "../engine.h"
#include <math.h>
//#define rWrite(a,v) pendingWrites[a]=v;
#define rWrite(a,v) if (!skipRegisterWrites) {GB_apu_write(gb,a,v);}
#define rWrite(a,v) if (!skipRegisterWrites) {GB_apu_write(gb,a,v); if (dumpWrites) {addWrite(a,v);} }
#define FREQ_BASE 8015.85f

2
src/engine/platform/genesisshared.h
View file

@ -24,4 +24,4 @@ static int orderedOps[4]={
};
#define rWrite(a,v) if (!skipRegisterWrites) {pendingWrites[a]=v;}
#define immWrite(a,v) if (!skipRegisterWrites) {writes.emplace(a,v);}
#define immWrite(a,v) if (!skipRegisterWrites) {writes.emplace(a,v); if (dumpWrites) {addWrite(a,v);} }

2
src/engine/platform/nes.cpp
View file

@ -7,7 +7,7 @@
#define FREQ_BASE 3424.0f
#define FREQ_BASE_PAL 3180.0f
#define rWrite(a,v) if (!skipRegisterWrites) {apu_wr_reg(nes,a,v);}
#define rWrite(a,v) if (!skipRegisterWrites) {apu_wr_reg(nes,a,v); if (dumpWrites) {addWrite(a,v);} }
void DivPlatformNES::acquire(short* bufL, short* bufR, size_t start, size_t len) {
for (size_t i=start; i<start+len; i++) {

2
src/engine/platform/pce.cpp
View file

@ -3,7 +3,7 @@
#include <math.h>
//#define rWrite(a,v) pendingWrites[a]=v;
#define rWrite(a,v) if (!skipRegisterWrites) {writes.emplace(a,v);}
#define rWrite(a,v) if (!skipRegisterWrites) {writes.emplace(a,v); if (dumpWrites) {addWrite(a,v);} }
#define chWrite(c,a,v) \
if (!skipRegisterWrites) { \
if (curChan!=c) { \

2
src/engine/platform/saa.cpp
View file

@ -4,7 +4,7 @@
#include <string.h>
#include <math.h>
#define rWrite(a,v) if (!skipRegisterWrites) {writes.emplace(a,v);}
#define rWrite(a,v) if (!skipRegisterWrites) {writes.emplace(a,v); if (dumpWrites) {addWrite(a,v);} }
#define PSG_FREQ_BASE 122240.0f

28
src/engine/platform/sms.cpp
View file

@ -4,6 +4,8 @@
#define FREQ_BASE 1712.0f
#define rWrite(v) {sn->write(v); if (dumpWrites) {addWrite(0,v);} }
void DivPlatformSMS::acquire(short* bufL, short* bufR, size_t start, size_t len) {
sn->sound_stream_update(bufL+start,len);
}
@ -19,7 +21,7 @@ void DivPlatformSMS::tick() {
chan[i].std.next();
if (chan[i].std.hadVol) {
chan[i].outVol=(chan[i].vol*chan[i].std.vol)>>4;
sn->write(0x90|(i<<5)|(isMuted[i]?15:(15-(chan[i].outVol&15))));
rWrite(0x90|(i<<5)|(isMuted[i]?15:(15-(chan[i].outVol&15))));
}
if (chan[i].std.hadArp) {
if (chan[i].std.arpMode) {
@ -46,8 +48,8 @@ void DivPlatformSMS::tick() {
if (chan[i].freqChanged) {
chan[i].freq=parent->calcFreq(chan[i].baseFreq,chan[i].pitch,true);
if (chan[i].note>0x5d) chan[i].freq=0x01;
sn->write(0x80|i<<5|(chan[i].freq&15));
sn->write(chan[i].freq>>4);
rWrite(0x80|i<<5|(chan[i].freq&15));
rWrite(chan[i].freq>>4);
chan[i].freqChanged=false;
}
}
@ -59,13 +61,13 @@ void DivPlatformSMS::tick() {
chan[3].freqChanged=false;
if (snNoiseMode&2) { // take period from channel 3
if (snNoiseMode&1) {
sn->write(0xe7);
rWrite(0xe7);
} else {
sn->write(0xe3);
rWrite(0xe3);
}
sn->write(0xdf);
sn->write(0xc0|(chan[3].freq&15));
sn->write(chan[3].freq>>4);
rWrite(0xdf);
rWrite(0xc0|(chan[3].freq&15));
rWrite(chan[3].freq>>4);
} else { // 3 fixed values
unsigned char value;
if (chan[3].std.hadArp) {
@ -79,7 +81,7 @@ void DivPlatformSMS::tick() {
}
if (value<3) {
value=2-value;
sn->write(0xe0|value|((snNoiseMode&1)<<2));
rWrite(0xe0|value|((snNoiseMode&1)<<2));
}
}
}
@ -92,12 +94,12 @@ int DivPlatformSMS::dispatch(DivCommand c) {
chan[c.chan].freqChanged=true;
chan[c.chan].note=c.value;
chan[c.chan].active=true;
sn->write(0x90|c.chan<<5|(isMuted[c.chan]?15:(15-(chan[c.chan].vol&15))));
rWrite(0x90|c.chan<<5|(isMuted[c.chan]?15:(15-(chan[c.chan].vol&15))));
chan[c.chan].std.init(parent->getIns(chan[c.chan].ins));
break;
case DIV_CMD_NOTE_OFF:
chan[c.chan].active=false;
sn->write(0x9f|c.chan<<5);
rWrite(0x9f|c.chan<<5);
chan[c.chan].std.init(NULL);
break;
case DIV_CMD_INSTRUMENT:
@ -110,7 +112,7 @@ int DivPlatformSMS::dispatch(DivCommand c) {
if (!chan[c.chan].std.hasVol) {
chan[c.chan].outVol=c.value;
}
if (chan[c.chan].active) sn->write(0x90|c.chan<<5|(isMuted[c.chan]?15:(15-(chan[c.chan].vol&15))));
if (chan[c.chan].active) rWrite(0x90|c.chan<<5|(isMuted[c.chan]?15:(15-(chan[c.chan].vol&15))));
}
break;
case DIV_CMD_GET_VOLUME:
@ -169,7 +171,7 @@ int DivPlatformSMS::dispatch(DivCommand c) {
void DivPlatformSMS::muteChannel(int ch, bool mute) {
isMuted[ch]=mute;
if (chan[ch].active) sn->write(0x90|ch<<5|(isMuted[ch]?15:(15-(chan[ch].outVol&15))));
if (chan[ch].active) rWrite(0x90|ch<<5|(isMuted[ch]?15:(15-(chan[ch].outVol&15))));
}
void DivPlatformSMS::reset() {

2
src/engine/platform/tia.cpp
View file

@ -3,7 +3,7 @@
#include <string.h>
#include <math.h>
#define rWrite(a,v) if (!skipRegisterWrites) {tia.set(a,v);}
#define rWrite(a,v) if (!skipRegisterWrites) {tia.set(a,v); if (dumpWrites) {addWrite(a,v);} }
void DivPlatformTIA::acquire(short* bufL, short* bufR, size_t start, size_t len) {
tia.process(bufL+start,len);

2
src/engine/platform/ym2610shared.h
View file

@ -24,7 +24,7 @@ static int orderedOps[4]={
};
#define rWrite(a,v) if (!skipRegisterWrites) {pendingWrites[a]=v;}
#define immWrite(a,v) if (!skipRegisterWrites) {writes.emplace(a,v);}
#define immWrite(a,v) if (!skipRegisterWrites) {writes.emplace(a,v); if (dumpWrites) {addWrite(a,v);} }
#define FM_FREQ_BASE 622.0f
#define PSG_FREQ_BASE 7640.0f