earliest VGM export!
only supports single-chip Genesis for now the other systems will be added shortly
This commit is contained in:
tildearrow
parent
35ee06d6cf
commit
858d5343b8
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@ -110,14 +110,21 @@ struct DivDelayedCommand {
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struct DivRegWrite {
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/**
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* an address of 0xffffff00 indicates a Furnace specific command.
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* an address of 0xffffxx00 indicates a Furnace specific command.
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* the following addresses are available:
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* - 0xffffff00: start sample playback
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* - 0xffffxx00: start sample playback
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* - xx is the instance ID
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* - data is the sample number
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* - 0xffffxx01: set sample rate
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* - xx is the instance ID
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* - data is the sample rate
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* - 0xffffxx02: stop sample playback
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* - xx is the instance ID
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* - 0xffffffff: reset
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*/
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unsigned int addr;
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unsigned char val;
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DivRegWrite(unsigned int a, unsigned char v):
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unsigned short val;
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DivRegWrite(unsigned int a, unsigned short v):
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addr(a), val(v) {}
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};
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@ -252,7 +259,7 @@ class DivDispatch {
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/**
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* enable register dumping.
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*/
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void toggleRegisterDump(bool enable);
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virtual void toggleRegisterDump(bool enable);
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/**
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* get register writes.
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@ -22,6 +22,8 @@
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#include <sndfile.h>
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#include <fmt/printf.h>
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constexpr int MASTER_CLOCK_PREC=(sizeof(void*)==8)?8:0;
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void process(void* u, float** in, float** out, int inChans, int outChans, unsigned int size) {
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((DivEngine*)u)->nextBuf(in,out,inChans,outChans,size);
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}
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@ -1907,6 +1909,54 @@ SafeWriter* DivEngine::saveDMF() {
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return w;
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}
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void DivEngine::performVGMWrite(SafeWriter* w, DivSystem sys, DivRegWrite& write, int streamOff) {
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if (write.addr>=0xffff0000) { // Furnace special command
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unsigned char streamID=streamOff+((write.addr&0xff00)>>8);
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switch (write.addr&0xff) {
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case 0: // play sample
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w->writeC(0x95);
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w->writeC(streamID);
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w->writeS(write.val); // sample number
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w->writeC(0); // flags
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break;
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case 1: // set sample freq
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w->writeC(0x92);
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w->writeC(streamID);
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w->writeI(write.val);
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break;
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case 2: // stop sample
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w->writeC(0x94);
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w->writeC(streamID);
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break;
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}
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return;
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}
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switch (sys) {
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case DIV_SYSTEM_GENESIS:
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case DIV_SYSTEM_GENESIS_EXT:
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switch (write.addr>>8) {
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case 0: // port 0
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w->writeC(0x52);
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w->writeC(write.addr&0xff);
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w->writeC(write.val);
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break;
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case 1: // port 1
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w->writeC(0x53);
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w->writeC(write.addr&0xff);
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w->writeC(write.val);
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break;
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case 2: // PSG
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w->writeC(0x50);
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w->writeC(write.val);
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break;
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}
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break;
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default:
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logW("write not handled!\n");
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break;
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}
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}
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SafeWriter* DivEngine::saveVGM() {
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stop();
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setOrder(0);
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@ -1916,44 +1966,52 @@ SafeWriter* DivEngine::saveVGM() {
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bool done=false;
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int hasSN=0;
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//int hasOPLL=0;
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int snNoiseConfig=9;
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int snNoiseSize=16;
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int snFlags=0;
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int hasOPLL=0;
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int hasOPN2=0;
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int hasOPM=0;
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int hasSegaPCM=0;
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//int hasRFC=0;
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//int hasOPN=0;
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//int hasOPNA=0;
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int segaPCMOffset=0x2000;
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int hasRFC=0;
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int hasOPN=0;
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int hasOPNA=0;
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int hasOPNB=0;
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//int hasOPL2=0;
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//int hasOPL=0;
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//int hasY8950=0;
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//int hasOPL3=0;
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//int hasZ280=0;
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//int hasRFC1=0;
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//int hasPWM=0;
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int hasOPL2=0;
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int hasOPL=0;
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int hasY8950=0;
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int hasOPL3=0;
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int hasOPL4=0;
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int hasOPX=0;
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int hasZ280=0;
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int hasRFC1=0;
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int hasPWM=0;
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int hasAY=0;
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int ayConfig=0;
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int ayFlags=0;
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int hasGB=0;
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int hasNES=0;
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//int hasMultiPCM=0;
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//int hasuPD7759=0;
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//int hasOKIM6258=0;
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//int hasK054539=0;
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//int hasOKIM6295=0;
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//int hasK051649=0;
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//int hasK054539=0;
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int hasMultiPCM=0;
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int hasuPD7759=0;
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int hasOKIM6258=0;
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int hasK054539=0;
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int hasOKIM6295=0;
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int hasK051649=0;
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int hasPCE=0;
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//int hasNamco=0;
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//int hasK053260=0;
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//int hasPOKEY=0;
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//int hasQSound=0;
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//int hasSCSP=0;
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//int hasSwan=0;
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//int hasVSU=0;
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int hasNamco=0;
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int hasK053260=0;
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int hasPOKEY=0;
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int hasQSound=0;
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int hasSCSP=0;
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int hasSwan=0;
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int hasVSU=0;
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int hasSAA=0;
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//int hasES5503=0;
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//int hasX1=0;
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//int hasC352=0;
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//int hasGA20=0;
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int hasES5503=0;
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int hasES5505=0;
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int hasX1=0;
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int hasC352=0;
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int hasGA20=0;
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SafeWriter* w=new SafeWriter;
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w->init();
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@ -1963,108 +2021,254 @@ SafeWriter* DivEngine::saveVGM() {
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w->writeI(0); // will be written later
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w->writeI(0x171); // VGM 1.71
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bool willExport[32];
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int streamIDs[32];
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for (int i=0; i<song.systemLen; i++) {
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bool willExport=false;
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willExport[i]=false;
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streamIDs[i]=0;
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switch (song.system[i]) {
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case DIV_SYSTEM_GENESIS:
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case DIV_SYSTEM_GENESIS_EXT:
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if (!hasOPN2) {
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hasOPN2=7670454;
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willExport=true;
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willExport[i]=true;
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}
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if (!hasSN) {
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hasSN=3579545;
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willExport=true;
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willExport[i]=true;
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}
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break;
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case DIV_SYSTEM_SMS:
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if (!hasSN) {
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hasSN=3579545;
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willExport=true;
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willExport[i]=true;
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}
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break;
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case DIV_SYSTEM_GB:
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if (!hasGB) {
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hasGB=4194304;
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willExport=true;
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willExport[i]=true;
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}
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break;
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case DIV_SYSTEM_PCE:
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if (!hasPCE) {
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hasPCE=3579545;
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willExport=true;
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willExport[i]=true;
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}
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break;
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case DIV_SYSTEM_NES:
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if (!hasNES) {
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hasNES=1789773;
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willExport=true;
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willExport[i]=true;
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}
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break;
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case DIV_SYSTEM_ARCADE:
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if (!hasOPM) {
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hasOPM=3579545;
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willExport=true;
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willExport[i]=true;
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}
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if (!hasSegaPCM) {
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hasSegaPCM=4000000;
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willExport=true;
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willExport[i]=true;
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}
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break;
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case DIV_SYSTEM_YM2610:
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case DIV_SYSTEM_YM2610_EXT:
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if (!hasOPNB) {
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hasOPNB=8000000;
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willExport=true;
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willExport[i]=true;
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}
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break;
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case DIV_SYSTEM_AY8910:
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case DIV_SYSTEM_AY8930:
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if (!hasAY) {
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hasAY=1789773;
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willExport=true;
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ayConfig=(song.system[i]==DIV_SYSTEM_AY8930)?3:0;
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ayFlags=1;
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willExport[i]=true;
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}
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break;
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case DIV_SYSTEM_SAA1099:
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if (!hasSAA) {
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hasSAA=8000000;
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willExport=true;
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willExport[i]=true;
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}
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break;
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case DIV_SYSTEM_YM2612:
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if (!hasOPN2) {
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hasOPN2=7670454;
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willExport=true;
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willExport[i]=true;
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}
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break;
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case DIV_SYSTEM_YM2151:
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if (!hasOPM) {
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hasOPM=3579545;
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willExport=true;
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willExport[i]=true;
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}
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break;
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default:
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break;
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}
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if (willExport) {
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if (willExport[i]) {
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disCont[i].dispatch->toggleRegisterDump(true);
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}
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}
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// write chips and stuff
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w->writeI(hasSN);
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w->writeI(hasOPLL);
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w->writeI(0);
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w->writeI(0); // length. will be written later
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w->writeI(0); // loop. will be written later
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w->writeI(0); // loop length. why is this necessary?
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w->writeI(0); // tick rate
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w->writeS(snNoiseConfig);
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w->writeC(snNoiseSize);
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w->writeC(snFlags);
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w->writeI(hasOPN2);
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w->writeI(hasOPM);
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w->writeI(0x100-w->tell()); // data pointer
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w->writeI(hasSegaPCM);
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w->writeI(segaPCMOffset);
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w->writeI(hasRFC);
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w->writeI(hasOPN);
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w->writeI(hasOPNA);
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w->writeI(hasOPNB);
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w->writeI(hasOPL2);
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w->writeI(hasOPL);
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w->writeI(hasY8950);
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w->writeI(hasOPL3);
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w->writeI(hasOPL4);
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w->writeI(hasOPX);
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w->writeI(hasZ280);
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w->writeI(hasRFC1);
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w->writeI(hasPWM);
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w->writeI(hasAY);
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w->writeC(ayConfig);
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w->writeC(ayFlags);
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w->writeC(ayFlags); // OPN
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w->writeC(ayFlags); // OPNA
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w->writeC(0); // volume
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w->writeC(0); // reserved
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w->writeC(0); // loop count
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w->writeC(0); // loop modifier
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w->writeI(hasGB);
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w->writeI(hasNES);
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w->writeI(hasMultiPCM);
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w->writeI(hasuPD7759);
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w->writeI(hasOKIM6258);
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w->writeC(0); // flags
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w->writeC(0); // K flags
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w->writeC(0); // C140 chip type
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w->writeC(0); // reserved
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w->writeI(hasOKIM6295);
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w->writeI(hasK051649);
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w->writeI(hasK054539);
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w->writeI(hasPCE);
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w->writeI(hasNamco);
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w->writeI(hasK053260);
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w->writeI(hasPOKEY);
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w->writeI(hasQSound);
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w->writeI(hasSCSP);
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w->writeI(0); // extra header. currently not written to
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w->writeI(hasSwan);
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w->writeI(hasVSU);
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w->writeI(hasSAA);
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w->writeI(hasES5503);
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w->writeI(hasES5505);
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w->writeC(0); // 5503 chans
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w->writeC(0); // 5505 chans
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w->writeC(0); // C352 clock divider
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w->writeC(0); // reserved
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w->writeI(hasX1);
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w->writeI(hasC352);
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w->writeI(hasGA20);
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for (int i=0; i<7; i++) { // reserved
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w->writeI(0);
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}
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// write samples
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for (int i=0; i<song.sampleLen; i++) {
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DivSample* sample=song.sample[i];
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w->writeC(0x67);
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w->writeC(0x66);
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w->writeC(0); // for now!
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w->writeI(sample->rendLength);
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if (sample->depth==8) {
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for (unsigned int j=0; j<sample->rendLength; j++) {
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w->writeC((unsigned char)sample->rendData[j]+0x80);
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}
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} else {
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for (unsigned int j=0; j<sample->rendLength; j++) {
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w->writeC(((unsigned short)sample->rendData[j]+0x8000)>>8);
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}
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}
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}
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// initialize streams
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int streamID=0;
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for (int i=0; i<song.systemLen; i++) {
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if (!willExport[i]) continue;
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streamIDs[i]=streamID;
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switch (song.system[i]) {
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case DIV_SYSTEM_GENESIS:
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case DIV_SYSTEM_GENESIS_EXT:
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w->writeC(0x90);
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w->writeC(streamID);
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w->writeC(0x02);
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w->writeC(0); // port
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w->writeC(0x2a); // DAC
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w->writeC(0x91);
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w->writeC(streamID);
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w->writeC(0);
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w->writeC(1);
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w->writeC(0);
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w->writeC(0x92);
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w->writeC(streamID);
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w->writeI(32000); // default
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streamID++;
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break;
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default:
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logE("what? trying to play sample on unsupported system\n");
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break;
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}
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}
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// write song data
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size_t tickCount=0;
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while (!done) {
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if (nextTick()) done=true;
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// get register dumps
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for (int i=0; i<song.systemLen; i++) {
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for (DivRegWrite& j: disCont[i].dispatch->getRegisterWrites()) {
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printf("- (%d) %.2x = %.2x\n",i,j.addr,j.val);
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std::vector<DivRegWrite>& writes=disCont[i].dispatch->getRegisterWrites();
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for (DivRegWrite& j: writes) {
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performVGMWrite(w,song.system[i],j,streamIDs[i]);
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}
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writes.clear();
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}
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// write wait
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w->writeC(0x61);
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w->writeS(cycles>>MASTER_CLOCK_PREC);
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tickCount+=cycles>>MASTER_CLOCK_PREC;
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}
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for (int i=0; i<song.systemLen; i++) {
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disCont[i].dispatch->toggleRegisterDump(false);
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}
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// finish file
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size_t len=w->size()-4;
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w->seek(4,SEEK_SET);
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w->writeI(len);
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w->seek(0x18,SEEK_SET);
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w->writeI(tickCount);
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// loop not handled for now
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w->writeI(0);
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w->writeI(0);
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isBusy.unlock();
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return w;
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}
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@ -188,6 +188,7 @@ class DivEngine {
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void processRow(int i, bool afterDelay);
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void nextOrder();
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void nextRow();
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void performVGMWrite(SafeWriter* w, DivSystem sys, DivRegWrite& write, int streamOff);
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// returns true if end of song.
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bool nextTick(bool noAccum=false);
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bool perSystemEffect(int ch, unsigned char effect, unsigned char effectVal);
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@ -192,6 +192,7 @@ void DivPlatformGenesis::tick() {
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immWrite(chanOffs[i]+ADDR_FREQ,freqt&0xff);
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if (chan[i].furnaceDac) {
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dacRate=(1280000*1.25)/chan[i].baseFreq;
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if (dumpWrites) addWrite(0xffff0001,chan[i].baseFreq);
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}
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chan[i].freqChanged=false;
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}
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@ -202,6 +203,11 @@ void DivPlatformGenesis::tick() {
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}
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psg.tick();
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for (DivRegWrite& i: psg.getRegisterWrites()) {
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if (dumpWrites) addWrite(i.addr,i.val);
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}
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psg.getRegisterWrites().clear();
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}
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int DivPlatformGenesis::octave(int freq) {
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@ -277,7 +283,10 @@ int DivPlatformGenesis::dispatch(DivCommand c) {
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|||
dacSample=ins->amiga.initSample;
|
||||
if (dacSample<0 || dacSample>=parent->song.sampleLen) {
|
||||
dacSample=-1;
|
||||
if (dumpWrites) addWrite(0xffff0002,0);
|
||||
break;
|
||||
} else {
|
||||
if (dumpWrites) addWrite(0xffff0000,dacSample);
|
||||
}
|
||||
dacPos=0;
|
||||
dacPeriod=0;
|
||||
|
|
@ -288,11 +297,15 @@ int DivPlatformGenesis::dispatch(DivCommand c) {
|
|||
dacSample=12*sampleBank+c.value%12;
|
||||
if (dacSample>=parent->song.sampleLen) {
|
||||
dacSample=-1;
|
||||
if (dumpWrites) addWrite(0xffff0002,0);
|
||||
break;
|
||||
} else {
|
||||
if (dumpWrites) addWrite(0xffff0000,dacSample);
|
||||
}
|
||||
dacPos=0;
|
||||
dacPeriod=0;
|
||||
dacRate=1280000/parent->song.sample[dacSample]->rate;
|
||||
if (dumpWrites) addWrite(0xffff0001,parent->song.sample[dacSample]->rate);
|
||||
chan[c.chan].furnaceDac=false;
|
||||
}
|
||||
break;
|
||||
|
|
@ -342,6 +355,7 @@ int DivPlatformGenesis::dispatch(DivCommand c) {
|
|||
case DIV_CMD_NOTE_OFF:
|
||||
if (c.chan==5) {
|
||||
dacSample=-1;
|
||||
if (dumpWrites) addWrite(0xffff0002,0);
|
||||
}
|
||||
chan[c.chan].keyOff=true;
|
||||
chan[c.chan].active=false;
|
||||
|
|
@ -522,6 +536,11 @@ void DivPlatformGenesis::forceIns() {
|
|||
immWrite(0x22,lfoValue);
|
||||
}
|
||||
|
||||
void DivPlatformGenesis::toggleRegisterDump(bool enable) {
|
||||
DivDispatch::toggleRegisterDump(enable);
|
||||
psg.toggleRegisterDump(enable);
|
||||
}
|
||||
|
||||
void DivPlatformGenesis::reset() {
|
||||
while (!writes.empty()) writes.pop();
|
||||
OPN2_Reset(&fm);
|
||||
|
|
|
|||
|
|
@ -78,6 +78,7 @@ class DivPlatformGenesis: public DivDispatch {
|
|||
bool isStereo();
|
||||
bool keyOffAffectsArp(int ch);
|
||||
bool keyOffAffectsPorta(int ch);
|
||||
void toggleRegisterDump(bool enable);
|
||||
void setPAL(bool pal);
|
||||
void notifyInsChange(int ins);
|
||||
void notifyInsDeletion(void* ins);
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
|
||||
#define FREQ_BASE 1712.0f
|
||||
|
||||
#define rWrite(v) {sn->write(v); if (dumpWrites) {addWrite(0,v);} }
|
||||
#define rWrite(v) {sn->write(v); if (dumpWrites) {addWrite(0x200,v);} }
|
||||
|
||||
void DivPlatformSMS::acquire(short* bufL, short* bufR, size_t start, size_t len) {
|
||||
sn->sound_stream_update(bufL+start,len);
|
||||
|
|
|
|||
Loading…
Reference in New Issue