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VERA: fix custom clock
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parent
f67faf9f23
commit
72ed5deeb1
2 changed files with 11 additions and 6 deletions
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@ -441,6 +441,15 @@ void DivPlatformVERA::poke(std::vector<DivRegWrite>& wlist) {
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for (auto &i: wlist) poke(i.addr,i.val);
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}
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void DivPlatformVERA::setFlags(const DivConfig& flags) {
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chipClock=25000000;
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CHECK_CUSTOM_CLOCK;
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rate=chipClock/512;
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for (int i=0; i<17; i++) {
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oscBuf[i]->rate=rate;
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}
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}
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int DivPlatformVERA::init(DivEngine* p, int channels, int sugRate, const DivConfig& flags) {
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for (int i=0; i<17; i++) {
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isMuted[i]=false;
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@ -451,12 +460,7 @@ int DivPlatformVERA::init(DivEngine* p, int channels, int sugRate, const DivConf
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pcm=new struct VERA_PCM;
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dumpWrites=false;
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skipRegisterWrites=false;
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chipClock=25000000;
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CHECK_CUSTOM_CLOCK;
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rate=chipClock/512;
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for (int i=0; i<17; i++) {
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oscBuf[i]->rate=rate;
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}
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setFlags(flags);
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reset();
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return 17;
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}
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@ -70,6 +70,7 @@ class DivPlatformVERA: public DivDispatch {
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void reset();
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void tick(bool sysTick=true);
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void muteChannel(int ch, bool mute);
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void setFlags(const DivConfig& flags);
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void notifyInsDeletion(void* ins);
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float getPostAmp();
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int getOutputCount();
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