mirror of
https://github.com/tildearrow/furnace.git
synced 2024-11-01 18:42:40 +00:00
core quality, part 3 - final
- SAA1099 - SCC - SM8521 - Swan - Virtual Boy
This commit is contained in:
parent
cb1f268335
commit
70a6affd3d
11 changed files with 180 additions and 10 deletions
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@ -527,6 +527,11 @@ void DivDispatchContainer::init(DivSystem sys, DivEngine* eng, int chanCount, do
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break;
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case DIV_SYSTEM_SAA1099: {
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dispatch=new DivPlatformSAA1099;
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if (isRender) {
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((DivPlatformSAA1099*)dispatch)->setCoreQuality(eng->getConfInt("saaQualityRender",3));
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} else {
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((DivPlatformSAA1099*)dispatch)->setCoreQuality(eng->getConfInt("saaQuality",3));
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}
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break;
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}
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case DIV_SYSTEM_PCSPKR:
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@ -564,12 +569,22 @@ void DivDispatchContainer::init(DivSystem sys, DivEngine* eng, int chanCount, do
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break;
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case DIV_SYSTEM_SWAN:
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dispatch=new DivPlatformSwan;
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if (isRender) {
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((DivPlatformSwan*)dispatch)->setCoreQuality(eng->getConfInt("swanQualityRender",3));
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} else {
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((DivPlatformSwan*)dispatch)->setCoreQuality(eng->getConfInt("swanQuality",3));
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}
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break;
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case DIV_SYSTEM_T6W28:
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dispatch=new DivPlatformT6W28;
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break;
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case DIV_SYSTEM_VBOY:
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dispatch=new DivPlatformVB;
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if (isRender) {
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((DivPlatformVB*)dispatch)->setCoreQuality(eng->getConfInt("vbQualityRender",3));
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} else {
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((DivPlatformVB*)dispatch)->setCoreQuality(eng->getConfInt("vbQuality",3));
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}
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break;
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case DIV_SYSTEM_VERA:
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dispatch=new DivPlatformVERA;
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@ -606,10 +621,20 @@ void DivDispatchContainer::init(DivSystem sys, DivEngine* eng, int chanCount, do
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case DIV_SYSTEM_SCC:
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dispatch=new DivPlatformSCC;
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((DivPlatformSCC*)dispatch)->setChipModel(false);
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if (isRender) {
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((DivPlatformSCC*)dispatch)->setCoreQuality(eng->getConfInt("sccQualityRender",3));
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} else {
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((DivPlatformSCC*)dispatch)->setCoreQuality(eng->getConfInt("sccQuality",3));
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}
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break;
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case DIV_SYSTEM_SCC_PLUS:
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dispatch=new DivPlatformSCC;
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((DivPlatformSCC*)dispatch)->setChipModel(true);
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if (isRender) {
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((DivPlatformSCC*)dispatch)->setCoreQuality(eng->getConfInt("sccQualityRender",3));
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} else {
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((DivPlatformSCC*)dispatch)->setCoreQuality(eng->getConfInt("sccQuality",3));
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}
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break;
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case DIV_SYSTEM_YMZ280B:
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dispatch=new DivPlatformYMZ280B;
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@ -654,6 +679,11 @@ void DivDispatchContainer::init(DivSystem sys, DivEngine* eng, int chanCount, do
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break;
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case DIV_SYSTEM_SM8521:
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dispatch=new DivPlatformSM8521;
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if (isRender) {
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((DivPlatformSM8521*)dispatch)->setCoreQuality(eng->getConfInt("smQualityRender",3));
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} else {
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((DivPlatformSM8521*)dispatch)->setCoreQuality(eng->getConfInt("smQuality",3));
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}
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break;
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case DIV_SYSTEM_PV1000:
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dispatch=new DivPlatformPV1000;
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@ -455,7 +455,7 @@ void DivPlatformSAA1099::setFlags(const DivConfig& flags) {
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chipClock=8000000;
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}
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CHECK_CUSTOM_CLOCK;
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rate=chipClock/32;
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rate=chipClock/coreQuality;
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for (int i=0; i<6; i++) {
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oscBuf[i]->rate=rate;
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@ -473,6 +473,32 @@ void DivPlatformSAA1099::poke(std::vector<DivRegWrite>& wlist) {
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for (DivRegWrite& i: wlist) rWrite(i.addr,i.val);
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}
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void DivPlatformSAA1099::setCoreQuality(unsigned char q) {
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switch (q) {
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case 0:
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coreQuality=256;
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break;
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case 1:
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coreQuality=128;
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break;
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case 2:
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coreQuality=64;
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break;
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case 3:
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coreQuality=32;
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break;
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case 4:
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coreQuality=8;
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break;
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case 5:
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coreQuality=1;
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break;
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default:
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coreQuality=32;
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break;
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}
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}
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int DivPlatformSAA1099::init(DivEngine* p, int channels, int sugRate, const DivConfig& flags) {
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parent=p;
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dumpWrites=false;
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@ -48,6 +48,7 @@ class DivPlatformSAA1099: public DivDispatch {
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QueuedWrite(unsigned short a, unsigned char v): addr(a), val(v), addrOrVal(false) {}
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};
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FixedQueue<QueuedWrite,256> writes;
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int coreQuality;
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CSAASound* saa_saaSound;
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unsigned char regPool[32];
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unsigned char lastBusy;
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@ -96,6 +97,7 @@ class DivPlatformSAA1099: public DivDispatch {
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void poke(unsigned int addr, unsigned short val);
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void poke(std::vector<DivRegWrite>& wlist);
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const char** getRegisterSheet();
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void setCoreQuality(unsigned char q);
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int init(DivEngine* parent, int channels, int sugRate, const DivConfig& flags);
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void quit();
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};
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@ -82,7 +82,7 @@ const char** DivPlatformSCC::getRegisterSheet() {
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void DivPlatformSCC::acquire(short** buf, size_t len) {
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for (size_t h=0; h<len; h++) {
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scc->tick(16);
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scc->tick(coreQuality);
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short out=(short)scc->out()<<5;
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buf[0][h]=out;
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@ -383,12 +383,38 @@ void DivPlatformSCC::setFlags(const DivConfig& flags) {
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break;
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}
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CHECK_CUSTOM_CLOCK;
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rate=chipClock/8;
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rate=chipClock/(coreQuality>>1);
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for (int i=0; i<5; i++) {
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oscBuf[i]->rate=rate;
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}
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}
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void DivPlatformSCC::setCoreQuality(unsigned char q) {
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switch (q) {
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case 0:
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coreQuality=128;
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break;
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case 1:
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coreQuality=64;
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break;
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case 2:
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coreQuality=32;
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break;
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case 3:
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coreQuality=16;
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break;
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case 4:
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coreQuality=8;
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break;
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case 5:
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coreQuality=2;
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break;
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default:
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coreQuality=16;
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break;
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}
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}
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int DivPlatformSCC::init(DivEngine* p, int channels, int sugRate, const DivConfig& flags) {
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parent=p;
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dumpWrites=false;
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@ -41,6 +41,7 @@ class DivPlatformSCC: public DivDispatch {
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unsigned char writeOscBuf;
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int lastUpdated34;
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int coreQuality;
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scc_core* scc;
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bool isPlus;
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unsigned char regBase;
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@ -68,6 +69,7 @@ class DivPlatformSCC: public DivDispatch {
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const char** getRegisterSheet();
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void setFlags(const DivConfig& flags);
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int init(DivEngine* parent, int channels, int sugRate, const DivConfig& flags);
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void setCoreQuality(unsigned char q);
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void setChipModel(bool isPlus);
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void quit();
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~DivPlatformSCC();
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@ -55,7 +55,7 @@ void DivPlatformSM8521::acquire(short** buf, size_t len) {
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writes.pop();
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}
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for (size_t h=0; h<len; h++) {
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sm8521_sound_tick(&sm8521,8);
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sm8521_sound_tick(&sm8521,coreQuality);
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buf[0][h]=sm8521.out<<6;
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for (int i=0; i<2; i++) {
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oscBuf[i]->data[oscBuf[i]->needle++]=sm8521.sg[i].base.out<<7;
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@ -367,7 +367,7 @@ void DivPlatformSM8521::setFlags(const DivConfig& flags) {
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chipClock=11059200;
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CHECK_CUSTOM_CLOCK;
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antiClickEnabled=!flags.getBool("noAntiClick",false);
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rate=chipClock/4/8; // CKIN -> fCLK(/2) -> Function blocks (/2)
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rate=chipClock/4/coreQuality; // CKIN -> fCLK(/2) -> Function blocks (/2)
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for (int i=0; i<3; i++) {
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oscBuf[i]->rate=rate;
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}
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for (DivRegWrite& i: wlist) rWrite(i.addr,i.val);
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}
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void DivPlatformSM8521::setCoreQuality(unsigned char q) {
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switch (q) {
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case 0:
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coreQuality=64;
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break;
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case 1:
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coreQuality=32;
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break;
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case 2:
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coreQuality=16;
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break;
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case 3:
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coreQuality=8;
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break;
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case 4:
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coreQuality=4;
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break;
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case 5:
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coreQuality=1;
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break;
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default:
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coreQuality=8;
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break;
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}
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}
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int DivPlatformSM8521::init(DivEngine* p, int channels, int sugRate, const DivConfig& flags) {
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parent=p;
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dumpWrites=false;
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@ -54,6 +54,7 @@ class DivPlatformSM8521: public DivDispatch {
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FixedQueue<QueuedWrite,128> writes;
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bool antiClickEnabled;
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int coreQuality;
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struct sm8521_t sm8521;
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unsigned char regPool[256];
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void updateWave(int ch);
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void poke(unsigned int addr, unsigned short val);
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void poke(std::vector<DivRegWrite>& wlist);
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const char** getRegisterSheet();
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void setCoreQuality(unsigned char q);
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int init(DivEngine* parent, int channels, int sugRate, const DivConfig& flags);
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void quit();
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~DivPlatformSM8521();
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@ -84,8 +84,8 @@ void DivPlatformSwan::acquire(short** buf, size_t len) {
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writes.pop();
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}
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int16_t samp[2]{0, 0};
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ws->SoundUpdate(16);
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ws->SoundFlush(samp, 1);
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ws->SoundUpdate(coreQuality);
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ws->SoundFlush(samp,1);
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buf[0][h]=samp[0];
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buf[1][h]=samp[1];
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for (int i=0; i<4; i++) {
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void DivPlatformSwan::setFlags(const DivConfig& flags) {
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chipClock=3072000;
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CHECK_CUSTOM_CLOCK;
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rate=chipClock/16; // = 192000kHz, should be enough
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rate=chipClock/coreQuality;
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for (int i=0; i<4; i++) {
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oscBuf[i]->rate=rate;
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}
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}
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void DivPlatformSwan::setCoreQuality(unsigned char q) {
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switch (q) {
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case 0:
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coreQuality=96;
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break;
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case 1:
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coreQuality=64;
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break;
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case 2:
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coreQuality=32;
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break;
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case 3:
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coreQuality=16;
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break;
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case 4:
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coreQuality=4;
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break;
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case 5:
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coreQuality=1;
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break;
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default:
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coreQuality=16;
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break;
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}
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}
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int DivPlatformSwan::init(DivEngine* p, int channels, int sugRate, const DivConfig& flags) {
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parent=p;
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dumpWrites=false;
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@ -53,6 +53,7 @@ class DivPlatformSwan: public DivDispatch {
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};
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FixedQueue<QueuedWrite,256> writes;
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FixedQueue<DivRegWrite,2048> postDACWrites;
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int coreQuality;
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WSwan* ws;
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void updateWave(int ch);
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friend void putDispatchChip(void*,int);
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void poke(unsigned int addr, unsigned short val);
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void poke(std::vector<DivRegWrite>& wlist);
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const char** getRegisterSheet();
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void setCoreQuality(unsigned char q);
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int init(DivEngine* parent, int channels, int sugRate, const DivConfig& flags);
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void quit();
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~DivPlatformSwan();
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@ -102,7 +102,7 @@ void DivPlatformVB::acquire(short** buf, size_t len) {
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regPool[w.addr>>2]=w.val;
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writes.pop();
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}
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vb->EndFrame(16);
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vb->EndFrame(coreQuality);
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tempL=0;
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tempR=0;
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void DivPlatformVB::setFlags(const DivConfig& flags) {
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chipClock=5000000.0;
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CHECK_CUSTOM_CLOCK;
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rate=chipClock/16;
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rate=chipClock/coreQuality;
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for (int i=0; i<6; i++) {
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oscBuf[i]->rate=rate;
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}
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for (DivRegWrite& i: wlist) rWrite(i.addr,i.val);
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}
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void DivPlatformVB::setCoreQuality(unsigned char q) {
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switch (q) {
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case 0:
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coreQuality=128;
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break;
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case 1:
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coreQuality=64;
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break;
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case 2:
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coreQuality=32;
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break;
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case 3:
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coreQuality=16;
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break;
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case 4:
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coreQuality=4;
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break;
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case 5:
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coreQuality=1;
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break;
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default:
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coreQuality=16;
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break;
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}
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}
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int DivPlatformVB::init(DivEngine* p, int channels, int sugRate, const DivConfig& flags) {
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parent=p;
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dumpWrites=false;
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@ -59,6 +59,7 @@ class DivPlatformVB: public DivDispatch {
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bool modType;
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bool romMode;
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signed char modTable[32];
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int coreQuality;
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VSU* vb;
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unsigned char regPool[0x600];
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void updateWave(int ch);
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void poke(unsigned int addr, unsigned short val);
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void poke(std::vector<DivRegWrite>& wlist);
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const char** getRegisterSheet();
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void setCoreQuality(unsigned char q);
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int init(DivEngine* parent, int channels, int sugRate, const DivConfig& flags);
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void quit();
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~DivPlatformVB();
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Reference in a new issue