core quality, part 3 - final

- SAA1099
- SCC
- SM8521
- Swan
- Virtual Boy
This commit is contained in:
tildearrow 2024-04-06 16:25:16 -05:00
parent cb1f268335
commit 70a6affd3d
11 changed files with 180 additions and 10 deletions

View file

@ -527,6 +527,11 @@ void DivDispatchContainer::init(DivSystem sys, DivEngine* eng, int chanCount, do
break;
case DIV_SYSTEM_SAA1099: {
dispatch=new DivPlatformSAA1099;
if (isRender) {
((DivPlatformSAA1099*)dispatch)->setCoreQuality(eng->getConfInt("saaQualityRender",3));
} else {
((DivPlatformSAA1099*)dispatch)->setCoreQuality(eng->getConfInt("saaQuality",3));
}
break;
}
case DIV_SYSTEM_PCSPKR:
@ -564,12 +569,22 @@ void DivDispatchContainer::init(DivSystem sys, DivEngine* eng, int chanCount, do
break;
case DIV_SYSTEM_SWAN:
dispatch=new DivPlatformSwan;
if (isRender) {
((DivPlatformSwan*)dispatch)->setCoreQuality(eng->getConfInt("swanQualityRender",3));
} else {
((DivPlatformSwan*)dispatch)->setCoreQuality(eng->getConfInt("swanQuality",3));
}
break;
case DIV_SYSTEM_T6W28:
dispatch=new DivPlatformT6W28;
break;
case DIV_SYSTEM_VBOY:
dispatch=new DivPlatformVB;
if (isRender) {
((DivPlatformVB*)dispatch)->setCoreQuality(eng->getConfInt("vbQualityRender",3));
} else {
((DivPlatformVB*)dispatch)->setCoreQuality(eng->getConfInt("vbQuality",3));
}
break;
case DIV_SYSTEM_VERA:
dispatch=new DivPlatformVERA;
@ -606,10 +621,20 @@ void DivDispatchContainer::init(DivSystem sys, DivEngine* eng, int chanCount, do
case DIV_SYSTEM_SCC:
dispatch=new DivPlatformSCC;
((DivPlatformSCC*)dispatch)->setChipModel(false);
if (isRender) {
((DivPlatformSCC*)dispatch)->setCoreQuality(eng->getConfInt("sccQualityRender",3));
} else {
((DivPlatformSCC*)dispatch)->setCoreQuality(eng->getConfInt("sccQuality",3));
}
break;
case DIV_SYSTEM_SCC_PLUS:
dispatch=new DivPlatformSCC;
((DivPlatformSCC*)dispatch)->setChipModel(true);
if (isRender) {
((DivPlatformSCC*)dispatch)->setCoreQuality(eng->getConfInt("sccQualityRender",3));
} else {
((DivPlatformSCC*)dispatch)->setCoreQuality(eng->getConfInt("sccQuality",3));
}
break;
case DIV_SYSTEM_YMZ280B:
dispatch=new DivPlatformYMZ280B;
@ -654,6 +679,11 @@ void DivDispatchContainer::init(DivSystem sys, DivEngine* eng, int chanCount, do
break;
case DIV_SYSTEM_SM8521:
dispatch=new DivPlatformSM8521;
if (isRender) {
((DivPlatformSM8521*)dispatch)->setCoreQuality(eng->getConfInt("smQualityRender",3));
} else {
((DivPlatformSM8521*)dispatch)->setCoreQuality(eng->getConfInt("smQuality",3));
}
break;
case DIV_SYSTEM_PV1000:
dispatch=new DivPlatformPV1000;

View file

@ -455,7 +455,7 @@ void DivPlatformSAA1099::setFlags(const DivConfig& flags) {
chipClock=8000000;
}
CHECK_CUSTOM_CLOCK;
rate=chipClock/32;
rate=chipClock/coreQuality;
for (int i=0; i<6; i++) {
oscBuf[i]->rate=rate;
@ -473,6 +473,32 @@ void DivPlatformSAA1099::poke(std::vector<DivRegWrite>& wlist) {
for (DivRegWrite& i: wlist) rWrite(i.addr,i.val);
}
void DivPlatformSAA1099::setCoreQuality(unsigned char q) {
switch (q) {
case 0:
coreQuality=256;
break;
case 1:
coreQuality=128;
break;
case 2:
coreQuality=64;
break;
case 3:
coreQuality=32;
break;
case 4:
coreQuality=8;
break;
case 5:
coreQuality=1;
break;
default:
coreQuality=32;
break;
}
}
int DivPlatformSAA1099::init(DivEngine* p, int channels, int sugRate, const DivConfig& flags) {
parent=p;
dumpWrites=false;

View file

@ -48,6 +48,7 @@ class DivPlatformSAA1099: public DivDispatch {
QueuedWrite(unsigned short a, unsigned char v): addr(a), val(v), addrOrVal(false) {}
};
FixedQueue<QueuedWrite,256> writes;
int coreQuality;
CSAASound* saa_saaSound;
unsigned char regPool[32];
unsigned char lastBusy;
@ -96,6 +97,7 @@ class DivPlatformSAA1099: public DivDispatch {
void poke(unsigned int addr, unsigned short val);
void poke(std::vector<DivRegWrite>& wlist);
const char** getRegisterSheet();
void setCoreQuality(unsigned char q);
int init(DivEngine* parent, int channels, int sugRate, const DivConfig& flags);
void quit();
};

View file

@ -82,7 +82,7 @@ const char** DivPlatformSCC::getRegisterSheet() {
void DivPlatformSCC::acquire(short** buf, size_t len) {
for (size_t h=0; h<len; h++) {
scc->tick(16);
scc->tick(coreQuality);
short out=(short)scc->out()<<5;
buf[0][h]=out;
@ -383,12 +383,38 @@ void DivPlatformSCC::setFlags(const DivConfig& flags) {
break;
}
CHECK_CUSTOM_CLOCK;
rate=chipClock/8;
rate=chipClock/(coreQuality>>1);
for (int i=0; i<5; i++) {
oscBuf[i]->rate=rate;
}
}
void DivPlatformSCC::setCoreQuality(unsigned char q) {
switch (q) {
case 0:
coreQuality=128;
break;
case 1:
coreQuality=64;
break;
case 2:
coreQuality=32;
break;
case 3:
coreQuality=16;
break;
case 4:
coreQuality=8;
break;
case 5:
coreQuality=2;
break;
default:
coreQuality=16;
break;
}
}
int DivPlatformSCC::init(DivEngine* p, int channels, int sugRate, const DivConfig& flags) {
parent=p;
dumpWrites=false;

View file

@ -41,6 +41,7 @@ class DivPlatformSCC: public DivDispatch {
unsigned char writeOscBuf;
int lastUpdated34;
int coreQuality;
scc_core* scc;
bool isPlus;
unsigned char regBase;
@ -68,6 +69,7 @@ class DivPlatformSCC: public DivDispatch {
const char** getRegisterSheet();
void setFlags(const DivConfig& flags);
int init(DivEngine* parent, int channels, int sugRate, const DivConfig& flags);
void setCoreQuality(unsigned char q);
void setChipModel(bool isPlus);
void quit();
~DivPlatformSCC();

View file

@ -55,7 +55,7 @@ void DivPlatformSM8521::acquire(short** buf, size_t len) {
writes.pop();
}
for (size_t h=0; h<len; h++) {
sm8521_sound_tick(&sm8521,8);
sm8521_sound_tick(&sm8521,coreQuality);
buf[0][h]=sm8521.out<<6;
for (int i=0; i<2; i++) {
oscBuf[i]->data[oscBuf[i]->needle++]=sm8521.sg[i].base.out<<7;
@ -367,7 +367,7 @@ void DivPlatformSM8521::setFlags(const DivConfig& flags) {
chipClock=11059200;
CHECK_CUSTOM_CLOCK;
antiClickEnabled=!flags.getBool("noAntiClick",false);
rate=chipClock/4/8; // CKIN -> fCLK(/2) -> Function blocks (/2)
rate=chipClock/4/coreQuality; // CKIN -> fCLK(/2) -> Function blocks (/2)
for (int i=0; i<3; i++) {
oscBuf[i]->rate=rate;
}
@ -381,6 +381,32 @@ void DivPlatformSM8521::poke(std::vector<DivRegWrite>& wlist) {
for (DivRegWrite& i: wlist) rWrite(i.addr,i.val);
}
void DivPlatformSM8521::setCoreQuality(unsigned char q) {
switch (q) {
case 0:
coreQuality=64;
break;
case 1:
coreQuality=32;
break;
case 2:
coreQuality=16;
break;
case 3:
coreQuality=8;
break;
case 4:
coreQuality=4;
break;
case 5:
coreQuality=1;
break;
default:
coreQuality=8;
break;
}
}
int DivPlatformSM8521::init(DivEngine* p, int channels, int sugRate, const DivConfig& flags) {
parent=p;
dumpWrites=false;

View file

@ -54,6 +54,7 @@ class DivPlatformSM8521: public DivDispatch {
FixedQueue<QueuedWrite,128> writes;
bool antiClickEnabled;
int coreQuality;
struct sm8521_t sm8521;
unsigned char regPool[256];
void updateWave(int ch);
@ -79,6 +80,7 @@ class DivPlatformSM8521: public DivDispatch {
void poke(unsigned int addr, unsigned short val);
void poke(std::vector<DivRegWrite>& wlist);
const char** getRegisterSheet();
void setCoreQuality(unsigned char q);
int init(DivEngine* parent, int channels, int sugRate, const DivConfig& flags);
void quit();
~DivPlatformSM8521();

View file

@ -84,8 +84,8 @@ void DivPlatformSwan::acquire(short** buf, size_t len) {
writes.pop();
}
int16_t samp[2]{0, 0};
ws->SoundUpdate(16);
ws->SoundFlush(samp, 1);
ws->SoundUpdate(coreQuality);
ws->SoundFlush(samp,1);
buf[0][h]=samp[0];
buf[1][h]=samp[1];
for (int i=0; i<4; i++) {
@ -596,12 +596,38 @@ void DivPlatformSwan::poke(std::vector<DivRegWrite>& wlist) {
void DivPlatformSwan::setFlags(const DivConfig& flags) {
chipClock=3072000;
CHECK_CUSTOM_CLOCK;
rate=chipClock/16; // = 192000kHz, should be enough
rate=chipClock/coreQuality;
for (int i=0; i<4; i++) {
oscBuf[i]->rate=rate;
}
}
void DivPlatformSwan::setCoreQuality(unsigned char q) {
switch (q) {
case 0:
coreQuality=96;
break;
case 1:
coreQuality=64;
break;
case 2:
coreQuality=32;
break;
case 3:
coreQuality=16;
break;
case 4:
coreQuality=4;
break;
case 5:
coreQuality=1;
break;
default:
coreQuality=16;
break;
}
}
int DivPlatformSwan::init(DivEngine* p, int channels, int sugRate, const DivConfig& flags) {
parent=p;
dumpWrites=false;

View file

@ -53,6 +53,7 @@ class DivPlatformSwan: public DivDispatch {
};
FixedQueue<QueuedWrite,256> writes;
FixedQueue<DivRegWrite,2048> postDACWrites;
int coreQuality;
WSwan* ws;
void updateWave(int ch);
friend void putDispatchChip(void*,int);
@ -78,6 +79,7 @@ class DivPlatformSwan: public DivDispatch {
void poke(unsigned int addr, unsigned short val);
void poke(std::vector<DivRegWrite>& wlist);
const char** getRegisterSheet();
void setCoreQuality(unsigned char q);
int init(DivEngine* parent, int channels, int sugRate, const DivConfig& flags);
void quit();
~DivPlatformSwan();

View file

@ -102,7 +102,7 @@ void DivPlatformVB::acquire(short** buf, size_t len) {
regPool[w.addr>>2]=w.val;
writes.pop();
}
vb->EndFrame(16);
vb->EndFrame(coreQuality);
tempL=0;
tempR=0;
@ -539,7 +539,7 @@ void DivPlatformVB::notifyInsDeletion(void* ins) {
void DivPlatformVB::setFlags(const DivConfig& flags) {
chipClock=5000000.0;
CHECK_CUSTOM_CLOCK;
rate=chipClock/16;
rate=chipClock/coreQuality;
for (int i=0; i<6; i++) {
oscBuf[i]->rate=rate;
}
@ -561,6 +561,32 @@ void DivPlatformVB::poke(std::vector<DivRegWrite>& wlist) {
for (DivRegWrite& i: wlist) rWrite(i.addr,i.val);
}
void DivPlatformVB::setCoreQuality(unsigned char q) {
switch (q) {
case 0:
coreQuality=128;
break;
case 1:
coreQuality=64;
break;
case 2:
coreQuality=32;
break;
case 3:
coreQuality=16;
break;
case 4:
coreQuality=4;
break;
case 5:
coreQuality=1;
break;
default:
coreQuality=16;
break;
}
}
int DivPlatformVB::init(DivEngine* p, int channels, int sugRate, const DivConfig& flags) {
parent=p;
dumpWrites=false;

View file

@ -59,6 +59,7 @@ class DivPlatformVB: public DivDispatch {
bool modType;
bool romMode;
signed char modTable[32];
int coreQuality;
VSU* vb;
unsigned char regPool[0x600];
void updateWave(int ch);
@ -89,6 +90,7 @@ class DivPlatformVB: public DivDispatch {
void poke(unsigned int addr, unsigned short val);
void poke(std::vector<DivRegWrite>& wlist);
const char** getRegisterSheet();
void setCoreQuality(unsigned char q);
int init(DivEngine* parent, int channels, int sugRate, const DivConfig& flags);
void quit();
~DivPlatformVB();