add SN chip ported from MAME
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// license:BSD-3-Clause
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// copyright-holders:Nicola Salmoria
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/***************************************************************************
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sn76496.c
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by Nicola Salmoria
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with contributions by others
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Routines to emulate the:
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Texas Instruments SN76489, SN76489A, SN76494/SN76496
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( Also known as, or at least compatible with, the TMS9919 and SN94624.)
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and the Sega 'PSG' used on the Master System, Game Gear, and Megadrive/Genesis
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This chip is known as the Programmable Sound Generator, or PSG, and is a 4
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channel sound generator, with three squarewave channels and a noise/arbitrary
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duty cycle channel.
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Noise emulation for all verified chips should be accurate:
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** SN76489 uses a 15-bit shift register with taps on bits D and E, output on E,
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XOR function.
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It uses a 15-bit ring buffer for periodic noise/arbitrary duty cycle.
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Its output is inverted.
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** SN94624 is the same as SN76489 but lacks the /8 divider on its clock input.
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** SN76489A uses a 15-bit shift register with taps on bits D and E, output on F,
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XOR function.
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It uses a 15-bit ring buffer for periodic noise/arbitrary duty cycle.
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Its output is not inverted.
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** SN76494 is the same as SN76489A but lacks the /8 divider on its clock input.
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** SN76496 is identical in operation to the SN76489A, but the audio input on pin 9 is
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documented.
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All the TI-made PSG chips have an audio input line which is mixed with the 4 channels
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of output. (It is undocumented and may not function properly on the sn76489, 76489a
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and 76494; the sn76489a input is mentioned in datasheets for the tms5200)
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All the TI-made PSG chips act as if the frequency was set to 0x400 if 0 is
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written to the frequency register.
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** Sega Master System III/MD/Genesis PSG uses a 16-bit shift register with taps
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on bits C and F, output on F
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It uses a 16-bit ring buffer for periodic noise/arbitrary duty cycle.
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(whether it uses an XOR or XNOR needs to be verified, assumed XOR)
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(whether output is inverted or not needs to be verified, assumed to be inverted)
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** Sega Game Gear PSG is identical to the SMS3/MD/Genesis one except it has an
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extra register for mapping which channels go to which speaker.
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The register, connected to a z80 port, means:
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for bits 7 6 5 4 3 2 1 0
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L3 L2 L1 L0 R3 R2 R1 R0
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Noise is an XOR function, and audio output is negated before being output.
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All the Sega-made PSG chips act as if the frequency was set to 0 if 0 is written
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to the frequency register.
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** NCR8496 (as used on the Tandy 1000TX) is similar to the SN76489 but with a
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different noise LFSR pattern: taps on bits A and E, output on E, XNOR function
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It uses a 15-bit ring buffer for periodic noise/arbitrary duty cycle.
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Its output is inverted.
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** PSSJ-3 (as used on the later Tandy 1000 series computers) is the same as the
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NCR8496 with the exception that its output is not inverted.
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28/03/2005 : Sebastien Chevalier
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Update th SN76496Write func, according to SN76489 doc found on SMSPower.
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- On write with 0x80 set to 0, when LastRegister is other then TONE,
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the function is similar than update with 0x80 set to 1
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23/04/2007 : Lord Nightmare
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Major update, implement all three different noise generation algorithms and a
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set_variant call to discern among them.
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28/04/2009 : Lord Nightmare
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Add READY line readback; cleaned up struct a bit. Cleaned up comments.
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Add more TODOs. Fixed some unsaved savestate related stuff.
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04/11/2009 : Lord Nightmare
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Changed the way that the invert works (it now selects between XOR and XNOR
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for the taps), and added R->OldNoise to simulate the extra 0 that is always
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output before the noise LFSR contents are after an LFSR reset.
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This fixes SN76489/A to match chips. Added SN94624.
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14/11/2009 : Lord Nightmare
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Removed STEP mess, vastly simplifying the code. Made output bipolar rather
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than always above the 0 line, but disabled that code due to pending issues.
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16/11/2009 : Lord Nightmare
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Fix screeching in regulus: When summing together four equal channels, the
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size of the max amplitude per channel should be 1/4 of the max range, not
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1/3. Added NCR8496.
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18/11/2009 : Lord Nightmare
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Modify Init functions to support negating the audio output. The gamegear
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psg does this. Change gamegear and sega psgs to use XOR rather than XNOR
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based on testing. Got rid of R->OldNoise and fixed taps accordingly.
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Added stereo support for game gear.
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15/01/2010 : Lord Nightmare
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Fix an issue with SN76489 and SN76489A having the wrong periodic noise periods.
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Note that properly emulating the noise cycle bit timing accurately may require
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extensive rewriting.
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24/01/2010: Lord Nightmare
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Implement periodic noise as forcing one of the XNOR or XOR taps to 1 or 0 respectively.
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Thanks to PlgDavid for providing samples which helped immensely here.
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Added true clock divider emulation, so sn94624 and sn76494 run 8x faster than
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the others, as in real life.
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15/02/2010: Lord Nightmare & Michael Zapf (additional testing by PlgDavid)
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Fix noise period when set to mirror channel 3 and channel 3 period is set to 0 (tested on hardware for noise, wave needs tests) - MZ
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Fix phase of noise on sn94624 and sn76489; all chips use a standard XOR, the only inversion is the output itself - LN, Plgdavid
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Thanks to PlgDavid and Michael Zapf for providing samples which helped immensely here.
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23/02/2011: Lord Nightmare & Enik
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Made it so the Sega PSG chips have a frequency of 0 if 0 is written to the
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frequency register, while the others have 0x400 as before. Should fix a bug
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or two on sega games, particularly Vigilante on Sega Master System. Verified
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on SMS hardware.
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27/06/2012: Michael Zapf
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Converted to modern device, legacy devices were gradually removed afterwards.
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16/09/2015: Lord Nightmare
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Fix PSG chips to have volume reg inited on reset to 0x0 based on tests by
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ValleyBell. Made Sega PSG chips start up with register 0x3 selected (volume
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for channel 2) based on hardware tests by Nemesis.
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03/09/2018: Lord Nightmare, Qbix, ValleyBell, NewRisingSun
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* renamed the NCR8496 to its correct name, based on chip pictures on VGMPF
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* fixed NCR8496's noise LFSR behavior so it is only reset if the mode bit in
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register 6 is changed.
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* NCR8496's LFSR feedback function is an XNOR, which is now supported.
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* add PSSJ-3 support for the later Tandy 1000 series computers.
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* NCR8496's output is inverted, PSSJ-3's output is not.
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10/12/2019: Michael Zapf
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* READY line handling by own emu_timer, not depending on sound_stream_update
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TODO: * Implement the TMS9919 - any difference to sn94624?
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* Implement the T6W28; has registers in a weird order, needs writes
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to be 'sanitized' first. Also is stereo, similar to game gear.
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* Factor out common code so that the SAA1099 can share some code.
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* verify NCR8496/PSSJ-3 behavior on write to mirrored registers; unlike the
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other variants, the NCR-derived variants are implied to ignore writes to
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regs 1,3,5,6,7 if 0x80 is not set. This needs to be verified on real hardware.
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***************************************************************************/
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#include "sn76496.h"
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#include <stdio.h>
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#define MAX_OUTPUT 0x7fff
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sn76496_base_device::sn76496_base_device(
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const char *tag,
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int feedbackmask,
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int noisetap1,
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int noisetap2,
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bool negate,
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int clockdivider,
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bool ncr,
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bool sega,
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uint32_t clock)
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: m_feedback_mask(feedbackmask)
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, m_whitenoise_tap1(noisetap1)
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, m_whitenoise_tap2(noisetap2)
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, m_clock_divider(clockdivider)
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, m_ncr_style_psg(ncr)
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, m_sega_style_psg(sega)
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{
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}
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sn76496_device::sn76496_device(const char *tag, uint32_t clock)
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: sn76496_base_device(tag, 0x10000, 0x04, 0x08, false, 8, false, true, clock)
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{
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}
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void sn76496_base_device::device_start()
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{
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int i;
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double out;
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int gain;
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for (i = 0; i < 4; i++) m_volume[i] = 0;
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m_last_register = m_sega_style_psg?3:0; // Sega VDP PSG defaults to selected period reg for 2nd channel
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for (i = 0; i < 8; i+=2)
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{
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m_register[i] = 0;
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m_register[i + 1] = 0x0; // volume = 0x0 (max volume) on reset; this needs testing on chips other than SN76489A and Sega VDP PSG
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}
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for (i = 0; i < 4; i++)
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{
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m_output[i] = 0;
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m_period[i] = 0;
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m_count[i] = 0;
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}
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m_RNG = m_feedback_mask;
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m_output[3] = m_RNG & 1;
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m_current_clock = m_clock_divider-1;
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// set gain
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gain = 0;
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gain &= 0xff;
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// increase max output basing on gain (0.2 dB per step)
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out = MAX_OUTPUT / 4; // four channels, each gets 1/4 of the total range
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while (gain-- > 0)
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out *= 1.023292992; // = (10 ^ (0.2/20))
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// build volume table (2dB per step)
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for (i = 0; i < 15; i++)
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{
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// limit volume to avoid clipping
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if (out > MAX_OUTPUT / 4) m_vol_table[i] = MAX_OUTPUT / 4;
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else m_vol_table[i] = out;
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out /= 1.258925412; /* = 10 ^ (2/20) = 2dB */
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}
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m_vol_table[15] = 0;
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m_ready_state = true;
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}
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void sn76496_base_device::write(u8 data)
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{
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int n, r, c;
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if (data & 0x80)
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{
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r = (data & 0x70) >> 4;
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m_last_register = r;
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if (((m_ncr_style_psg) && (r == 6)) && ((data&0x04) != (m_register[6]&0x04))) m_RNG = m_feedback_mask; // NCR-style PSG resets the LFSR only on a mode write which actually changes the state of bit 2 of register 6
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m_register[r] = (m_register[r] & 0x3f0) | (data & 0x0f);
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}
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else
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{
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r = m_last_register;
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//if ((m_ncr_style_psg) && ((r & 1) || (r == 6))) return; // NCR-style PSG ignores writes to regs 1, 3, 5, 6 and 7 with bit 7 clear; this behavior is not verified on hardware yet, uncomment it once verified.
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}
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c = r >> 1;
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switch (r)
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{
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case 0: // tone 0: frequency
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case 2: // tone 1: frequency
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case 4: // tone 2: frequency
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if ((data & 0x80) == 0) m_register[r] = (m_register[r] & 0x0f) | ((data & 0x3f) << 4);
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if ((m_register[r] != 0) || (!m_sega_style_psg)) m_period[c] = m_register[r];
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else m_period[c] = 0x400;
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if (r == 4)
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{
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// update noise shift frequency
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if ((m_register[6] & 0x03) == 0x03) m_period[3] = m_period[2]<<1;
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}
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break;
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case 1: // tone 0: volume
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case 3: // tone 1: volume
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case 5: // tone 2: volume
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case 7: // noise: volume
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m_volume[c] = m_vol_table[data & 0x0f];
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if ((data & 0x80) == 0) m_register[r] = (m_register[r] & 0x3f0) | (data & 0x0f);
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break;
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case 6: // noise: frequency, mode
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{
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if ((data & 0x80) == 0) printf("sn76496_base_device: write to reg 6 with bit 7 clear; data was %03x, new write is %02x! report this to LN!\n", m_register[6], data);
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if ((data & 0x80) == 0) m_register[r] = (m_register[r] & 0x3f0) | (data & 0x0f);
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n = m_register[6];
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// N/512,N/1024,N/2048,Tone #3 output
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m_period[3] = ((n&3) == 3)? (m_period[2]<<1) : (1 << (5+(n&3)));
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if (!(m_ncr_style_psg)) m_RNG = m_feedback_mask;
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}
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break;
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}
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//m_ready_state = false;
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}
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inline bool sn76496_base_device::in_noise_mode()
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{
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return ((m_register[6] & 4)!=0);
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}
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void sn76496_base_device::sound_stream_update(short* outputs, int outLen)
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{
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int i;
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int16_t out;
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int16_t out2 = 0;
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for (int sampindex = 0; sampindex < outLen; sampindex++)
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{
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// clock chip once
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if (m_current_clock > 0) // not ready for new divided clock
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{
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m_current_clock--;
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}
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else // ready for new divided clock, make a new sample
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{
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m_current_clock = m_clock_divider-1;
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// handle channels 0,1,2
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for (i = 0; i < 3; i++)
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{
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m_count[i]--;
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if (m_count[i] <= 0)
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{
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m_output[i] ^= 1;
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m_count[i] = m_period[i];
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}
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}
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// handle channel 3
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m_count[3]--;
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if (m_count[3] <= 0)
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{
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// if noisemode is 1, both taps are enabled
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// if noisemode is 0, the lower tap, whitenoisetap2, is held at 0
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// The != was a bit-XOR (^) before
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if (((m_RNG & m_whitenoise_tap1)!=0) != (((int32_t)(m_RNG & m_whitenoise_tap2)!=(m_ncr_style_psg?m_whitenoise_tap2:0)) && in_noise_mode()))
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{
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m_RNG >>= 1;
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m_RNG |= m_feedback_mask;
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}
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else
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{
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m_RNG >>= 1;
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}
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m_output[3] = m_RNG & 1;
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m_count[3] = m_period[3];
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}
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}
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out= ((m_output[0]!=0)? m_volume[0]:0)
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+((m_output[1]!=0)? m_volume[1]:0)
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+((m_output[2]!=0)? m_volume[2]:0)
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+((m_output[3]!=0)? m_volume[3]:0);
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if (m_negate) { out = -out; out2 = -out2; }
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outputs[sampindex]=out;
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}
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}
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@ -0,0 +1,65 @@
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// license:BSD-3-Clause
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// copyright-holders:Nicola Salmoria
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// additional modifications by tildearrow to a
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#ifndef MAME_SOUND_SN76496_H
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#define MAME_SOUND_SN76496_H
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#include <stdlib.h>
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#include <stdint.h>
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typedef unsigned char u8;
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class sn76496_base_device {
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public:
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void stereo_w(u8 data);
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void write(u8 data);
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void device_start();
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void sound_stream_update(short* outputs, int outLen);
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//DECLARE_READ_LINE_MEMBER( ready_r ) { return m_ready_state ? 1 : 0; }
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protected:
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sn76496_base_device(
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const char *tag,
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int feedbackmask,
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int noisetap1,
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int noisetap2,
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bool negate,
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int clockdivider,
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bool ncr,
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bool sega,
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uint32_t clock);
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private:
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inline bool in_noise_mode();
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bool m_ready_state;
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const int32_t m_feedback_mask; // mask for feedback
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const int32_t m_whitenoise_tap1; // mask for white noise tap 1 (higher one, usually bit 14)
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const int32_t m_whitenoise_tap2; // mask for white noise tap 2 (lower one, usually bit 13)
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bool m_negate; // output negate flag
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const int32_t m_clock_divider; // clock divider
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const bool m_ncr_style_psg; // flag to ignore writes to regs 1,3,5,6,7 with bit 7 low
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const bool m_sega_style_psg; // flag to make frequency zero acts as if it is one more than max (0x3ff+1) or if it acts like 0; the initial register is pointing to 0x3 instead of 0x0; the volume reg is preloaded with 0xF instead of 0x0
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int32_t m_clock;
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int32_t m_vol_table[16]; // volume table (for 4-bit to db conversion)
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int32_t m_register[8]; // registers
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int32_t m_last_register; // last register written
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int32_t m_volume[4]; // db volume of voice 0-2 and noise
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uint32_t m_RNG; // noise generator LFSR
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int32_t m_current_clock;
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int32_t m_period[4]; // Length of 1/2 of waveform
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int32_t m_count[4]; // Position within the waveform
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int32_t m_output[4]; // 1-bit output of each channel, pre-volume
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};
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// SN76496: Whitenoise verified, phase verified, periodic verified (by Michael Zapf)
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class sn76496_device : public sn76496_base_device
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{
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public:
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sn76496_device(const char *tag, uint32_t clock);
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};
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#endif // MAME_SOUND_SN76496_H
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