mirror of
https://github.com/tildearrow/furnace.git
synced 2024-11-22 12:35:11 +00:00
initial OPZ bring-up
even emulation is incomplete and one thing is making me tired...
This commit is contained in:
tildearrow
parent
9345576fc3
commit
530327383a
8 changed files with 876 additions and 5 deletions
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@ -314,6 +314,7 @@ src/engine/platform/mmc5.cpp
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src/engine/platform/nes.cpp
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src/engine/platform/c64.cpp
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src/engine/platform/arcade.cpp
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src/engine/platform/tx81z.cpp
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src/engine/platform/ym2610.cpp
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src/engine/platform/ym2610ext.cpp
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src/engine/platform/ym2610b.cpp
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@ -28,6 +28,7 @@
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#include "platform/nes.h"
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#include "platform/c64.h"
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#include "platform/arcade.h"
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#include "platform/tx81z.h"
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#include "platform/ym2610.h"
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#include "platform/ym2610ext.h"
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#include "platform/ym2610b.h"
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@ -252,6 +253,9 @@ void DivDispatchContainer::init(DivSystem sys, DivEngine* eng, int chanCount, do
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dispatch=new DivPlatformOPL;
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((DivPlatformOPL*)dispatch)->setOPLType(3,true);
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break;
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case DIV_SYSTEM_OPZ:
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dispatch=new DivPlatformTX81Z;
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break;
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case DIV_SYSTEM_SAA1099: {
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int saaCore=eng->getConfInt("saaCore",1);
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if (saaCore<0 || saaCore>2) saaCore=0;
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@ -68,9 +68,9 @@ enum DivInstrumentType {
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// - OPL:
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// - AM, AR, DR, MULT, RR, SL, TL, SSG-EG&8 = EG-S
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// - KSL, VIB, WS (OPL2/3), KSR
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// - OPZ: NOT FINAL!
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// - OPZ:
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// - AM, AR, DR, MULT (CRS), RR, SL, TL, DT2, RS, DT, D2R
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// - KSL = LS, WS, DVB = MULT (FINE), DAM = REV, EGT = EGShift
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// - WS, DVB = MULT (FINE), DAM = REV, KSL = EGShift, EGT = Fixed
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struct DivInstrumentFM {
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unsigned char alg, fb, fms, ams, ops, opllPreset;
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@ -208,11 +208,11 @@ void DivPlatformArcade::acquire(short* bufL, short* bufR, size_t start, size_t l
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}
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}
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unsigned char noteMap[12]={
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static unsigned char noteMap[12]={
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0, 1, 2, 4, 5, 6, 8, 9, 10, 12, 13, 14
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};
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int hScale(int note) {
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inline int hScale(int note) {
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return ((note/12)<<4)+(noteMap[note%12]);
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}
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@ -270,6 +270,7 @@ bool opz_registers::write(uint16_t index, uint8_t data, uint32_t &channel, uint3
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bool is_setting_preset = (bitfield(m_regdata[0x100 + (index & 0x1f)], 7) != 0);
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if (is_setting_preset)
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{
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//printf("ISP\n");
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if ((index & 0xe0) == 0xe0)
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{
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m_regdata[0x140 + (index & 0x1f)] = data;
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@ -280,10 +281,14 @@ bool opz_registers::write(uint16_t index, uint8_t data, uint32_t &channel, uint3
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}
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// handle writes to the key on index
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if ((index & 0xf8) == 0x20 && bitfield(index, 0, 3) == bitfield(m_regdata[0x08], 0, 3))
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// note from tildearrow:
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// - are you kidding? I have to write to this "load preset" register before keying on?
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if ((index & 0xf8) == 0x20 /*&& bitfield(index, 0, 3) == bitfield(m_regdata[0x08], 0, 3)*/)
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{
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channel = bitfield(index, 0, 3);
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opmask = ch_key_on(channel) ? 0xf : 0;
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//printf("%d opmask is %d\n",opmask,channel);
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// according to the TX81Z manual, the sync option causes the LFOs
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// to reset at each note on
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762
src/engine/platform/tx81z.cpp
Normal file
762
src/engine/platform/tx81z.cpp
Normal file
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@ -0,0 +1,762 @@
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/**
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* Furnace Tracker - multi-system chiptune tracker
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* Copyright (C) 2021-2022 tildearrow and contributors
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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*/
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#include "tx81z.h"
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#include "../engine.h"
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#include <string.h>
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#include <math.h>
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#include "fmshared_OPM.h"
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// actually 0x40 but the upper bit of data selects address
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#define ADDR_WS_FINE 0x100
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// actually 0xc0 but bit 5 of data selects address
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#define ADDR_EGS_REV 0x120
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static unsigned short chanOffs[8]={
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0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07
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};
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static unsigned short opOffs[4]={
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0x00, 0x08, 0x10, 0x18
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};
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static bool isOutput[8][4]={
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// 1 3 2 4
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{false,false,false,true},
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{false,false,false,true},
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{false,false,false,true},
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{false,false,false,true},
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{false,false,true ,true},
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{false,true ,true ,true},
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{false,true ,true ,true},
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{true ,true ,true ,true},
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};
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static unsigned char dtTable[8]={
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7,6,5,0,1,2,3,4
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};
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static int orderedOps[4]={
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0,2,1,3
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};
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#define rWrite(a,v) if (!skipRegisterWrites) {pendingWrites[a]=v;}
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#define immWrite(a,v) if (!skipRegisterWrites) {writes.emplace(a,v); if (dumpWrites) {addWrite(a,v);} }
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#define NOTE_LINEAR(x) (((x)<<6)+baseFreqOff+log2(parent->song.tuning/440.0)*12.0*64.0)
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const char* regCheatSheetOPZ[]={
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"Test", "00",
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"NoteCtl", "08",
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"NoiseCtl", "0F",
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"ClockA1", "10",
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"ClockA2", "11",
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"ClockB", "12",
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"Control", "14",
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"LFOFreq", "18",
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"AMD_PMD", "19",
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"LFOWave", "1B",
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"L_R_FB_ALG", "20",
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"KC", "28",
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"KF", "30",
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"PMS_AMS", "38",
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"DT_MULT", "40",
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"TL", "60",
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"KS_AR", "80",
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"AM_DR", "A0",
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"DT2_SR", "C0",
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"SL_RR", "E0",
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NULL
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};
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const char** DivPlatformTX81Z::getRegisterSheet() {
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return regCheatSheetOPZ;
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}
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const char* DivPlatformTX81Z::getEffectName(unsigned char effect) {
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switch (effect) {
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case 0x10:
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return "10xx: Set noise frequency (xx: value; 0 disables noise)";
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break;
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case 0x11:
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return "11xx: Set feedback (0 to 7)";
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break;
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case 0x12:
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return "12xx: Set level of operator 1 (0 highest, 7F lowest)";
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break;
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case 0x13:
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return "13xx: Set level of operator 2 (0 highest, 7F lowest)";
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break;
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case 0x14:
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return "14xx: Set level of operator 3 (0 highest, 7F lowest)";
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break;
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case 0x15:
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return "15xx: Set level of operator 4 (0 highest, 7F lowest)";
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break;
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case 0x16:
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return "16xy: Set operator multiplier (x: operator from 1 to 4; y: multiplier)";
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break;
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case 0x17:
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return "17xx: Set LFO speed";
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break;
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case 0x18:
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return "18xx: Set LFO waveform (0 saw, 1 square, 2 triangle, 3 noise)";
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break;
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case 0x19:
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return "19xx: Set attack of all operators (0 to 1F)";
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break;
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case 0x1a:
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return "1Axx: Set attack of operator 1 (0 to 1F)";
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break;
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case 0x1b:
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return "1Bxx: Set attack of operator 2 (0 to 1F)";
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break;
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case 0x1c:
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return "1Cxx: Set attack of operator 3 (0 to 1F)";
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break;
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case 0x1d:
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return "1Dxx: Set attack of operator 4 (0 to 1F)";
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break;
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case 0x1e:
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return "1Exx: Set AM depth (0 to 7F)";
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break;
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case 0x1f:
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return "1Fxx: Set PM depth (0 to 7F)";
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break;
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}
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return NULL;
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}
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void DivPlatformTX81Z::acquire(short* bufL, short* bufR, size_t start, size_t len) {
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static int os[2];
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for (size_t h=start; h<start+len; h++) {
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os[0]=0; os[1]=0;
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if (!writes.empty()) {
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if (--delay<1) {
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QueuedWrite& w=writes.front();
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fm_ymfm->write(0x0+((w.addr>>8)<<1),w.addr);
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fm_ymfm->write(0x1+((w.addr>>8)<<1),w.val);
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regPool[w.addr&0xff]=w.val;
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writes.pop();
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delay=1;
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}
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}
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fm_ymfm->generate(&out_ymfm);
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os[0]=out_ymfm.data[0];
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if (os[0]<-32768) os[0]=-32768;
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if (os[0]>32767) os[0]=32767;
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os[1]=out_ymfm.data[1];
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if (os[1]<-32768) os[1]=-32768;
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if (os[1]>32767) os[1]=32767;
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bufL[h]=os[0];
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bufR[h]=os[1];
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}
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}
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static unsigned char noteMap[12]={
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0, 1, 2, 4, 5, 6, 8, 9, 10, 12, 13, 14
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};
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inline int hScale(int note) {
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return ((note/12)<<4)+(noteMap[note%12]);
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}
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void DivPlatformTX81Z::tick() {
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for (int i=0; i<8; i++) {
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chan[i].std.next();
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if (chan[i].std.hadVol) {
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chan[i].outVol=(chan[i].vol*MIN(127,chan[i].std.vol))/127;
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for (int j=0; j<4; j++) {
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unsigned short baseAddr=chanOffs[i]|opOffs[j];
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DivInstrumentFM::Operator& op=chan[i].state.op[j];
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if (isOutput[chan[i].state.alg][j]) {
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rWrite(baseAddr+ADDR_TL,127-(((127-op.tl)*(chan[i].outVol&0x7f))/127));
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} else {
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rWrite(baseAddr+ADDR_TL,op.tl);
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}
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}
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}
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if (chan[i].std.hadArp) {
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if (!chan[i].inPorta) {
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if (chan[i].std.arpMode) {
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chan[i].baseFreq=NOTE_LINEAR(chan[i].std.arp);
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} else {
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chan[i].baseFreq=NOTE_LINEAR(chan[i].note+(signed char)chan[i].std.arp);
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}
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}
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chan[i].freqChanged=true;
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} else {
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if (chan[i].std.arpMode && chan[i].std.finishedArp) {
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chan[i].baseFreq=NOTE_LINEAR(chan[i].note);
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chan[i].freqChanged=true;
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}
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}
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if (chan[i].std.hadDuty) {
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if (chan[i].std.duty>0) {
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rWrite(0x0f,0x80|(0x20-chan[i].std.duty));
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} else {
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rWrite(0x0f,0);
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}
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}
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if (chan[i].std.hadWave) {
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rWrite(0x1b,chan[i].std.wave&3);
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}
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if (chan[i].std.hadEx1) {
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amDepth=chan[i].std.ex1;
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immWrite(0x19,amDepth);
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}
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if (chan[i].std.hadEx2) {
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pmDepth=chan[i].std.ex2;
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immWrite(0x19,0x80|pmDepth);
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}
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if (chan[i].std.hadEx3) {
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immWrite(0x18,chan[i].std.ex3);
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}
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if (chan[i].std.hadAlg) {
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chan[i].state.alg=chan[i].std.alg;
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if (isMuted[i]) {
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immWrite(chanOffs[i]+ADDR_LR_FB_ALG,(chan[i].state.alg&7)|(chan[i].state.fb<<3)|0x40);
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} else {
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immWrite(chanOffs[i]+ADDR_LR_FB_ALG,(chan[i].state.alg&7)|(chan[i].state.fb<<3)|(chan[i].active?0:0x40)|(chan[i].chVolR<<7));
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}
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if (!parent->song.algMacroBehavior) for (int j=0; j<4; j++) {
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unsigned short baseAddr=chanOffs[i]|opOffs[j];
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DivInstrumentFM::Operator& op=chan[i].state.op[j];
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if (isMuted[i]) {
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rWrite(baseAddr+ADDR_TL,127);
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} else {
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if (isOutput[chan[i].state.alg][j]) {
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rWrite(baseAddr+ADDR_TL,127-(((127-op.tl)*(chan[i].outVol&0x7f))/127));
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} else {
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rWrite(baseAddr+ADDR_TL,op.tl);
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}
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}
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}
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}
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if (chan[i].std.hadFb) {
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chan[i].state.fb=chan[i].std.fb;
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if (isMuted[i]) {
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immWrite(chanOffs[i]+ADDR_LR_FB_ALG,(chan[i].state.alg&7)|(chan[i].state.fb<<3)|0x40);
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} else {
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immWrite(chanOffs[i]+ADDR_LR_FB_ALG,(chan[i].state.alg&7)|(chan[i].state.fb<<3)|(chan[i].active?0:0x40)|(chan[i].chVolR<<7));
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}
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}
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if (chan[i].std.hadFms) {
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chan[i].state.fms=chan[i].std.fms;
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rWrite(chanOffs[i]+ADDR_FMS_AMS,((chan[i].state.fms&7)<<4)|(chan[i].state.ams&3));
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}
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if (chan[i].std.hadAms) {
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chan[i].state.ams=chan[i].std.ams;
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rWrite(chanOffs[i]+ADDR_FMS_AMS,((chan[i].state.fms&7)<<4)|(chan[i].state.ams&3));
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}
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for (int j=0; j<4; j++) {
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unsigned short baseAddr=chanOffs[i]|opOffs[j];
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DivInstrumentFM::Operator& op=chan[i].state.op[j];
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DivMacroInt::IntOp& m=chan[i].std.op[j];
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if (m.hadAm) {
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op.am=m.am;
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rWrite(baseAddr+ADDR_AM_DR,(op.dr&31)|(op.am<<7));
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}
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if (m.hadAr) {
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op.ar=m.ar;
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rWrite(baseAddr+ADDR_RS_AR,(op.ar&31)|(op.egt<<5)|(op.rs<<6));
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}
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if (m.hadDr) {
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op.dr=m.dr;
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rWrite(baseAddr+ADDR_AM_DR,(op.dr&31)|(op.am<<7));
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}
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if (m.hadMult) {
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op.mult=m.mult;
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rWrite(baseAddr+ADDR_MULT_DT,(op.mult&15)|(dtTable[op.dt&7]<<4));
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}
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if (m.hadRr) {
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op.rr=m.rr;
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rWrite(baseAddr+ADDR_SL_RR,(op.rr&15)|(op.sl<<4));
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}
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if (m.hadSl) {
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op.sl=m.sl;
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rWrite(baseAddr+ADDR_SL_RR,(op.rr&15)|(op.sl<<4));
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}
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if (m.hadTl) {
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op.tl=127-m.tl;
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if (isOutput[chan[i].state.alg][j]) {
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rWrite(baseAddr+ADDR_TL,127-(((127-op.tl)*(chan[i].outVol&0x7f))/127));
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} else {
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rWrite(baseAddr+ADDR_TL,op.tl);
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}
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}
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if (m.hadRs) {
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op.rs=m.rs;
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rWrite(baseAddr+ADDR_RS_AR,(op.ar&31)|(op.egt<<5)|(op.rs<<6));
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}
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if (m.hadDt) {
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op.dt=m.dt;
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rWrite(baseAddr+ADDR_MULT_DT,(op.mult&15)|(dtTable[op.dt&7]<<4));
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}
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if (m.hadD2r) {
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op.d2r=m.d2r;
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rWrite(baseAddr+ADDR_DT2_D2R,(op.d2r&31)|(op.dt2<<6));
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}
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if (m.hadDt2) {
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op.dt2=m.dt2;
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rWrite(baseAddr+ADDR_DT2_D2R,(op.d2r&31)|(op.dt2<<6));
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}
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}
|
||||
if (chan[i].keyOn || chan[i].keyOff) {
|
||||
if (isMuted[i]) {
|
||||
immWrite(chanOffs[i]+ADDR_LR_FB_ALG,(chan[i].state.alg&7)|(chan[i].state.fb<<3)|0x00);
|
||||
} else {
|
||||
//if (chan[i].keyOn) immWrite(0x08,i);
|
||||
immWrite(chanOffs[i]+ADDR_LR_FB_ALG,(chan[i].state.alg&7)|(chan[i].state.fb<<3)|0x00|(chan[i].chVolR<<7));
|
||||
}
|
||||
chan[i].keyOff=false;
|
||||
}
|
||||
}
|
||||
|
||||
for (int i=0; i<256; i++) {
|
||||
if (pendingWrites[i]!=oldWrites[i]) {
|
||||
immWrite(i,pendingWrites[i]&0xff);
|
||||
oldWrites[i]=pendingWrites[i];
|
||||
}
|
||||
}
|
||||
for (int i=256; i<288; i++) {
|
||||
if (pendingWrites[i]!=oldWrites[i]) {
|
||||
immWrite(0x40+(i&0x1f),0x80|(pendingWrites[i]&0x7f));
|
||||
oldWrites[i]=pendingWrites[i];
|
||||
}
|
||||
}
|
||||
for (int i=288; i<320; i++) {
|
||||
if (pendingWrites[i]!=oldWrites[i]) {
|
||||
immWrite(0xc0+(i&0x1f),0x20|(pendingWrites[i]&0xdf));
|
||||
oldWrites[i]=pendingWrites[i];
|
||||
}
|
||||
}
|
||||
|
||||
for (int i=0; i<8; i++) {
|
||||
if (chan[i].freqChanged) {
|
||||
chan[i].freq=chan[i].baseFreq+(chan[i].pitch>>1)-64;
|
||||
if (chan[i].freq<0) chan[i].freq=0;
|
||||
if (chan[i].freq>=(95<<6)) chan[i].freq=(95<<6)-1;
|
||||
immWrite(i+0x28,hScale(chan[i].freq>>6));
|
||||
immWrite(i+0x30,(chan[i].freq<<2)|(chan[i].chVolL==chan[i].chVolR));
|
||||
chan[i].freqChanged=false;
|
||||
}
|
||||
if (chan[i].keyOn) {
|
||||
if (isMuted[i]) {
|
||||
immWrite(chanOffs[i]+ADDR_LR_FB_ALG,(chan[i].state.alg&7)|(chan[i].state.fb<<3));
|
||||
} else {
|
||||
//immWrite(0x08,i);
|
||||
immWrite(chanOffs[i]+ADDR_LR_FB_ALG,(chan[i].state.alg&7)|(chan[i].state.fb<<3)|0x40|(chan[i].chVolR<<7));
|
||||
}
|
||||
chan[i].keyOn=false;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void DivPlatformTX81Z::muteChannel(int ch, bool mute) {
|
||||
isMuted[ch]=mute;
|
||||
// TODO: use volume registers!
|
||||
/*
|
||||
if (isMuted[ch]) {
|
||||
immWrite(chanOffs[ch]+ADDR_LR_FB_ALG,(chan[ch].state.alg&7)|(chan[ch].state.fb<<3));
|
||||
} else {
|
||||
immWrite(chanOffs[ch]+ADDR_LR_FB_ALG,(chan[ch].state.alg&7)|(chan[ch].state.fb<<3)|((chan[ch].chVolL&1)<<6)|((chan[ch].chVolR&1)<<7));
|
||||
}*/
|
||||
}
|
||||
|
||||
int DivPlatformTX81Z::dispatch(DivCommand c) {
|
||||
switch (c.cmd) {
|
||||
case DIV_CMD_NOTE_ON: {
|
||||
DivInstrument* ins=parent->getIns(chan[c.chan].ins);
|
||||
|
||||
if (chan[c.chan].insChanged) {
|
||||
chan[c.chan].state=ins->fm;
|
||||
}
|
||||
|
||||
chan[c.chan].std.init(ins);
|
||||
if (!chan[c.chan].std.willVol) {
|
||||
chan[c.chan].outVol=chan[c.chan].vol;
|
||||
}
|
||||
|
||||
for (int i=0; i<4; i++) {
|
||||
unsigned short baseAddr=chanOffs[c.chan]|opOffs[i];
|
||||
DivInstrumentFM::Operator op=chan[c.chan].state.op[i];
|
||||
if (isOutput[chan[c.chan].state.alg][i]) {
|
||||
if (!chan[c.chan].active || chan[c.chan].insChanged) {
|
||||
rWrite(baseAddr+ADDR_TL,127-(((127-op.tl)*(chan[c.chan].outVol&0x7f))/127));
|
||||
}
|
||||
} else {
|
||||
if (chan[c.chan].insChanged) {
|
||||
rWrite(baseAddr+ADDR_TL,op.tl);
|
||||
}
|
||||
}
|
||||
if (chan[c.chan].insChanged) {
|
||||
rWrite(baseAddr+ADDR_MULT_DT,(op.mult&15)|(dtTable[op.dt&7]<<4));
|
||||
rWrite(baseAddr+ADDR_RS_AR,(op.ar&31)|(op.egt<<5)|(op.rs<<6));
|
||||
rWrite(baseAddr+ADDR_AM_DR,(op.dr&31)|(op.am<<7));
|
||||
rWrite(baseAddr+ADDR_DT2_D2R,(op.d2r&31)|(op.dt2<<6));
|
||||
rWrite(baseAddr+ADDR_SL_RR,(op.rr&15)|(op.sl<<4));
|
||||
rWrite(baseAddr+ADDR_WS_FINE,(op.dvb&15)|(op.ws<<4));
|
||||
rWrite(baseAddr+ADDR_EGS_REV,(op.dam&7)|(op.ksl<<6));
|
||||
}
|
||||
}
|
||||
if (chan[c.chan].insChanged) {
|
||||
/*
|
||||
if (isMuted[c.chan]) {
|
||||
rWrite(chanOffs[c.chan]+ADDR_LR_FB_ALG,(chan[c.chan].state.alg&7)|(chan[c.chan].state.fb<<3));
|
||||
} else {
|
||||
rWrite(chanOffs[c.chan]+ADDR_LR_FB_ALG,(chan[c.chan].state.alg&7)|(chan[c.chan].state.fb<<3)|((chan[c.chan].chVolL&1)<<6)|((chan[c.chan].chVolR&1)<<7));
|
||||
}*/
|
||||
rWrite(chanOffs[c.chan]+ADDR_FMS_AMS,((chan[c.chan].state.fms&7)<<4)|(chan[c.chan].state.ams&3));
|
||||
}
|
||||
chan[c.chan].insChanged=false;
|
||||
|
||||
if (c.value!=DIV_NOTE_NULL) {
|
||||
chan[c.chan].baseFreq=NOTE_LINEAR(c.value);
|
||||
chan[c.chan].note=c.value;
|
||||
chan[c.chan].freqChanged=true;
|
||||
}
|
||||
chan[c.chan].keyOn=true;
|
||||
chan[c.chan].active=true;
|
||||
break;
|
||||
}
|
||||
case DIV_CMD_NOTE_OFF:
|
||||
chan[c.chan].keyOff=true;
|
||||
chan[c.chan].keyOn=false;
|
||||
chan[c.chan].active=false;
|
||||
break;
|
||||
case DIV_CMD_NOTE_OFF_ENV:
|
||||
chan[c.chan].keyOff=true;
|
||||
chan[c.chan].keyOn=false;
|
||||
chan[c.chan].active=false;
|
||||
chan[c.chan].std.release();
|
||||
break;
|
||||
case DIV_CMD_ENV_RELEASE:
|
||||
chan[c.chan].std.release();
|
||||
break;
|
||||
case DIV_CMD_VOLUME: {
|
||||
chan[c.chan].vol=c.value;
|
||||
if (!chan[c.chan].std.hasVol) {
|
||||
chan[c.chan].outVol=c.value;
|
||||
}
|
||||
for (int i=0; i<4; i++) {
|
||||
unsigned short baseAddr=chanOffs[c.chan]|opOffs[i];
|
||||
DivInstrumentFM::Operator& op=chan[c.chan].state.op[i];
|
||||
if (isOutput[chan[c.chan].state.alg][i]) {
|
||||
rWrite(baseAddr+ADDR_TL,127-(((127-op.tl)*(chan[c.chan].outVol&0x7f))/127));
|
||||
} else {
|
||||
rWrite(baseAddr+ADDR_TL,op.tl);
|
||||
}
|
||||
}
|
||||
break;
|
||||
}
|
||||
case DIV_CMD_GET_VOLUME: {
|
||||
return chan[c.chan].vol;
|
||||
break;
|
||||
}
|
||||
case DIV_CMD_INSTRUMENT:
|
||||
if (chan[c.chan].ins!=c.value || c.value2==1) {
|
||||
chan[c.chan].insChanged=true;
|
||||
}
|
||||
chan[c.chan].ins=c.value;
|
||||
break;
|
||||
case DIV_CMD_PANNING: {
|
||||
chan[c.chan].chVolL=((c.value>>4)>0);
|
||||
chan[c.chan].chVolR=((c.value&15)>0);
|
||||
/*
|
||||
if (isMuted[c.chan]) {
|
||||
rWrite(chanOffs[c.chan]+ADDR_LR_FB_ALG,(chan[c.chan].state.alg&7)|(chan[c.chan].state.fb<<3));
|
||||
} else {
|
||||
rWrite(chanOffs[c.chan]+ADDR_LR_FB_ALG,(chan[c.chan].state.alg&7)|(chan[c.chan].state.fb<<3)|((chan[c.chan].chVolL&1)<<6)|((chan[c.chan].chVolR&1)<<7));
|
||||
}*/
|
||||
break;
|
||||
}
|
||||
case DIV_CMD_PITCH: {
|
||||
chan[c.chan].pitch=c.value;
|
||||
chan[c.chan].freqChanged=true;
|
||||
break;
|
||||
}
|
||||
case DIV_CMD_NOTE_PORTA: {
|
||||
int destFreq=NOTE_LINEAR(c.value2);
|
||||
int newFreq;
|
||||
bool return2=false;
|
||||
if (destFreq>chan[c.chan].baseFreq) {
|
||||
newFreq=chan[c.chan].baseFreq+c.value;
|
||||
if (newFreq>=destFreq) {
|
||||
newFreq=destFreq;
|
||||
return2=true;
|
||||
}
|
||||
} else {
|
||||
newFreq=chan[c.chan].baseFreq-c.value;
|
||||
if (newFreq<=destFreq) {
|
||||
newFreq=destFreq;
|
||||
return2=true;
|
||||
}
|
||||
}
|
||||
chan[c.chan].baseFreq=newFreq;
|
||||
chan[c.chan].freqChanged=true;
|
||||
if (return2) {
|
||||
chan[c.chan].inPorta=false;
|
||||
return 2;
|
||||
}
|
||||
break;
|
||||
}
|
||||
case DIV_CMD_LEGATO: {
|
||||
chan[c.chan].baseFreq=NOTE_LINEAR(c.value);
|
||||
chan[c.chan].freqChanged=true;
|
||||
break;
|
||||
}
|
||||
case DIV_CMD_FM_LFO: {
|
||||
rWrite(0x18,c.value);
|
||||
break;
|
||||
}
|
||||
case DIV_CMD_FM_LFO_WAVE: {
|
||||
rWrite(0x1b,c.value&3);
|
||||
break;
|
||||
}
|
||||
case DIV_CMD_FM_FB: {
|
||||
chan[c.chan].state.fb=c.value&7;
|
||||
/*
|
||||
if (isMuted[c.chan]) {
|
||||
rWrite(chanOffs[c.chan]+ADDR_LR_FB_ALG,(chan[c.chan].state.alg&7)|(chan[c.chan].state.fb<<3));
|
||||
} else {
|
||||
rWrite(chanOffs[c.chan]+ADDR_LR_FB_ALG,(chan[c.chan].state.alg&7)|(chan[c.chan].state.fb<<3)|((chan[c.chan].chVolL&1)<<6)|((chan[c.chan].chVolR&1)<<7));
|
||||
}*/
|
||||
break;
|
||||
}
|
||||
case DIV_CMD_FM_MULT: {
|
||||
unsigned short baseAddr=chanOffs[c.chan]|opOffs[orderedOps[c.value]];
|
||||
DivInstrumentFM::Operator& op=chan[c.chan].state.op[orderedOps[c.value]];
|
||||
op.mult=c.value2&15;
|
||||
rWrite(baseAddr+ADDR_MULT_DT,(op.mult&15)|(dtTable[op.dt&7]<<4));
|
||||
break;
|
||||
}
|
||||
case DIV_CMD_FM_TL: {
|
||||
unsigned short baseAddr=chanOffs[c.chan]|opOffs[orderedOps[c.value]];
|
||||
DivInstrumentFM::Operator& op=chan[c.chan].state.op[orderedOps[c.value]];
|
||||
op.tl=c.value2;
|
||||
if (isOutput[chan[c.chan].state.alg][c.value]) {
|
||||
rWrite(baseAddr+ADDR_TL,127-(((127-op.tl)*(chan[c.chan].outVol&0x7f))/127));
|
||||
} else {
|
||||
rWrite(baseAddr+ADDR_TL,op.tl);
|
||||
}
|
||||
break;
|
||||
}
|
||||
case DIV_CMD_FM_AR: {
|
||||
if (c.value<0) {
|
||||
for (int i=0; i<4; i++) {
|
||||
DivInstrumentFM::Operator& op=chan[c.chan].state.op[i];
|
||||
op.ar=c.value2&31;
|
||||
unsigned short baseAddr=chanOffs[c.chan]|opOffs[i];
|
||||
rWrite(baseAddr+ADDR_RS_AR,(op.ar&31)|(op.egt<<5)|(op.rs<<6));
|
||||
}
|
||||
} else {
|
||||
DivInstrumentFM::Operator& op=chan[c.chan].state.op[orderedOps[c.value]];
|
||||
op.ar=c.value2&31;
|
||||
unsigned short baseAddr=chanOffs[c.chan]|opOffs[orderedOps[c.value]];
|
||||
rWrite(baseAddr+ADDR_RS_AR,(op.ar&31)|(op.egt<<5)|(op.rs<<6));
|
||||
}
|
||||
break;
|
||||
}
|
||||
case DIV_CMD_FM_AM_DEPTH: {
|
||||
amDepth=c.value;
|
||||
immWrite(0x19,amDepth);
|
||||
break;
|
||||
}
|
||||
case DIV_CMD_FM_PM_DEPTH: {
|
||||
pmDepth=c.value;
|
||||
immWrite(0x19,0x80|pmDepth);
|
||||
break;
|
||||
}
|
||||
case DIV_CMD_STD_NOISE_FREQ: {
|
||||
if (c.chan!=7) break;
|
||||
if (c.value) {
|
||||
if (c.value>0x1f) {
|
||||
rWrite(0x0f,0x80);
|
||||
} else {
|
||||
rWrite(0x0f,0x80|(0x1f-c.value));
|
||||
}
|
||||
} else {
|
||||
rWrite(0x0f,0);
|
||||
}
|
||||
break;
|
||||
}
|
||||
case DIV_ALWAYS_SET_VOLUME:
|
||||
return 0;
|
||||
break;
|
||||
case DIV_CMD_GET_VOLMAX:
|
||||
return 127;
|
||||
break;
|
||||
case DIV_CMD_PRE_PORTA:
|
||||
chan[c.chan].inPorta=c.value;
|
||||
break;
|
||||
case DIV_CMD_PRE_NOTE:
|
||||
break;
|
||||
default:
|
||||
//printf("WARNING: unimplemented command %d\n",c.cmd);
|
||||
break;
|
||||
}
|
||||
return 1;
|
||||
}
|
||||
|
||||
void DivPlatformTX81Z::forceIns() {
|
||||
for (int i=0; i<8; i++) {
|
||||
for (int j=0; j<4; j++) {
|
||||
unsigned short baseAddr=chanOffs[i]|opOffs[j];
|
||||
DivInstrumentFM::Operator op=chan[i].state.op[j];
|
||||
if (isOutput[chan[i].state.alg][j]) {
|
||||
rWrite(baseAddr+ADDR_TL,127-(((127-op.tl)*(chan[i].outVol&0x7f))/127));
|
||||
} else {
|
||||
rWrite(baseAddr+ADDR_TL,op.tl);
|
||||
}
|
||||
rWrite(baseAddr+ADDR_MULT_DT,(op.mult&15)|(dtTable[op.dt&7]<<4));
|
||||
rWrite(baseAddr+ADDR_RS_AR,(op.ar&31)|(op.egt<<5)|(op.rs<<6));
|
||||
rWrite(baseAddr+ADDR_AM_DR,(op.dr&31)|(op.am<<7));
|
||||
rWrite(baseAddr+ADDR_DT2_D2R,(op.d2r&31)|(op.dt2<<6));
|
||||
rWrite(baseAddr+ADDR_SL_RR,(op.rr&15)|(op.sl<<4));
|
||||
rWrite(baseAddr+ADDR_WS_FINE,(op.dvb&15)|(op.ws<<4));
|
||||
rWrite(baseAddr+ADDR_EGS_REV,(op.dam&7)|(op.ksl<<6));
|
||||
}
|
||||
/*
|
||||
if (isMuted[i]) {
|
||||
rWrite(chanOffs[i]+ADDR_LR_FB_ALG,(chan[i].state.alg&7)|(chan[i].state.fb<<3));
|
||||
} else {
|
||||
rWrite(chanOffs[i]+ADDR_LR_FB_ALG,(chan[i].state.alg&7)|(chan[i].state.fb<<3)|((chan[i].chVolL&1)<<6)|((chan[i].chVolR&1)<<7));
|
||||
}*/
|
||||
rWrite(chanOffs[i]+ADDR_FMS_AMS,((chan[i].state.fms&7)<<4)|(chan[i].state.ams&3));
|
||||
if (chan[i].active) {
|
||||
chan[i].keyOn=true;
|
||||
chan[i].freqChanged=true;
|
||||
}
|
||||
}
|
||||
immWrite(0x19,amDepth);
|
||||
immWrite(0x19,0x80|pmDepth);
|
||||
}
|
||||
|
||||
void DivPlatformTX81Z::notifyInsChange(int ins) {
|
||||
for (int i=0; i<8; i++) {
|
||||
if (chan[i].ins==ins) {
|
||||
chan[i].insChanged=true;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void* DivPlatformTX81Z::getChanState(int ch) {
|
||||
return &chan[ch];
|
||||
}
|
||||
|
||||
unsigned char* DivPlatformTX81Z::getRegisterPool() {
|
||||
return regPool;
|
||||
}
|
||||
|
||||
int DivPlatformTX81Z::getRegisterPoolSize() {
|
||||
return 330;
|
||||
}
|
||||
|
||||
void DivPlatformTX81Z::poke(unsigned int addr, unsigned short val) {
|
||||
immWrite(addr,val);
|
||||
}
|
||||
|
||||
void DivPlatformTX81Z::poke(std::vector<DivRegWrite>& wlist) {
|
||||
for (DivRegWrite& i: wlist) immWrite(i.addr,i.val);
|
||||
}
|
||||
|
||||
void DivPlatformTX81Z::reset() {
|
||||
while (!writes.empty()) writes.pop();
|
||||
memset(regPool,0,330);
|
||||
fm_ymfm->reset();
|
||||
if (dumpWrites) {
|
||||
addWrite(0xffffffff,0);
|
||||
}
|
||||
for (int i=0; i<8; i++) {
|
||||
chan[i]=DivPlatformTX81Z::Channel();
|
||||
chan[i].vol=0x7f;
|
||||
chan[i].outVol=0x7f;
|
||||
}
|
||||
|
||||
for (int i=0; i<330; i++) {
|
||||
oldWrites[i]=-1;
|
||||
pendingWrites[i]=-1;
|
||||
}
|
||||
|
||||
lastBusy=60;
|
||||
pcmCycles=0;
|
||||
pcmL=0;
|
||||
pcmR=0;
|
||||
delay=0;
|
||||
amDepth=0x7f;
|
||||
pmDepth=0x7f;
|
||||
|
||||
//rWrite(0x18,0x10);
|
||||
immWrite(0x19,amDepth);
|
||||
immWrite(0x19,0x80|pmDepth);
|
||||
//rWrite(0x1b,0x00);
|
||||
|
||||
extMode=false;
|
||||
}
|
||||
|
||||
void DivPlatformTX81Z::setFlags(unsigned int flags) {
|
||||
if (flags==2) {
|
||||
chipClock=4000000.0;
|
||||
baseFreqOff=-122;
|
||||
} else if (flags==1) {
|
||||
chipClock=COLOR_PAL*4.0/5.0;
|
||||
baseFreqOff=12;
|
||||
} else {
|
||||
chipClock=COLOR_NTSC;
|
||||
baseFreqOff=0;
|
||||
}
|
||||
rate=chipClock/64;
|
||||
}
|
||||
|
||||
bool DivPlatformTX81Z::isStereo() {
|
||||
return true;
|
||||
}
|
||||
|
||||
int DivPlatformTX81Z::init(DivEngine* p, int channels, int sugRate, unsigned int flags) {
|
||||
parent=p;
|
||||
dumpWrites=false;
|
||||
skipRegisterWrites=false;
|
||||
for (int i=0; i<8; i++) {
|
||||
isMuted[i]=false;
|
||||
}
|
||||
setFlags(flags);
|
||||
fm_ymfm=new ymfm::ym2414(iface);
|
||||
reset();
|
||||
|
||||
return 8;
|
||||
}
|
||||
|
||||
void DivPlatformTX81Z::quit() {
|
||||
delete fm_ymfm;
|
||||
}
|
||||
|
||||
DivPlatformTX81Z::~DivPlatformTX81Z() {
|
||||
}
|
||||
98
src/engine/platform/tx81z.h
Normal file
98
src/engine/platform/tx81z.h
Normal file
|
|
@ -0,0 +1,98 @@
|
|||
/**
|
||||
* Furnace Tracker - multi-system chiptune tracker
|
||||
* Copyright (C) 2021-2022 tildearrow and contributors
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
*/
|
||||
|
||||
#ifndef _TX81Z_H
|
||||
#define _TX81Z_H
|
||||
#include "../dispatch.h"
|
||||
#include "../instrument.h"
|
||||
#include <queue>
|
||||
#include "sound/ymfm/ymfm_opz.h"
|
||||
#include "../macroInt.h"
|
||||
|
||||
class DivTXInterface: public ymfm::ymfm_interface {
|
||||
|
||||
};
|
||||
|
||||
class DivPlatformTX81Z: public DivDispatch {
|
||||
protected:
|
||||
struct Channel {
|
||||
DivInstrumentFM state;
|
||||
DivMacroInt std;
|
||||
unsigned char freqH, freqL;
|
||||
int freq, baseFreq, pitch, note;
|
||||
unsigned char ins;
|
||||
signed char konCycles;
|
||||
bool active, insChanged, freqChanged, keyOn, keyOff, inPorta, portaPause, furnacePCM;
|
||||
int vol, outVol;
|
||||
unsigned char chVolL, chVolR;
|
||||
Channel(): freqH(0), freqL(0), freq(0), baseFreq(0), pitch(0), note(0), ins(-1), active(false), insChanged(true), freqChanged(false), keyOn(false), keyOff(false), inPorta(false), portaPause(false), furnacePCM(false), vol(0), outVol(0), chVolL(127), chVolR(127) {}
|
||||
};
|
||||
Channel chan[8];
|
||||
struct QueuedWrite {
|
||||
unsigned short addr;
|
||||
unsigned char val;
|
||||
bool addrOrVal;
|
||||
QueuedWrite(unsigned short a, unsigned char v): addr(a), val(v), addrOrVal(false) {}
|
||||
};
|
||||
std::queue<QueuedWrite> writes;
|
||||
int delay, baseFreqOff;
|
||||
int pcmL, pcmR, pcmCycles;
|
||||
unsigned char lastBusy;
|
||||
unsigned char amDepth, pmDepth;
|
||||
|
||||
ymfm::ym2414* fm_ymfm;
|
||||
ymfm::ym2414::output_data out_ymfm;
|
||||
DivTXInterface iface;
|
||||
|
||||
unsigned char regPool[330];
|
||||
|
||||
bool extMode;
|
||||
|
||||
bool isMuted[8];
|
||||
|
||||
short oldWrites[330];
|
||||
short pendingWrites[330];
|
||||
|
||||
int octave(int freq);
|
||||
int toFreq(int freq);
|
||||
|
||||
friend void putDispatchChan(void*,int,int);
|
||||
|
||||
public:
|
||||
void acquire(short* bufL, short* bufR, size_t start, size_t len);
|
||||
int dispatch(DivCommand c);
|
||||
void* getChanState(int chan);
|
||||
unsigned char* getRegisterPool();
|
||||
int getRegisterPoolSize();
|
||||
void reset();
|
||||
void forceIns();
|
||||
void tick();
|
||||
void muteChannel(int ch, bool mute);
|
||||
void notifyInsChange(int ins);
|
||||
void setFlags(unsigned int flags);
|
||||
bool isStereo();
|
||||
void poke(unsigned int addr, unsigned short val);
|
||||
void poke(std::vector<DivRegWrite>& wlist);
|
||||
const char** getRegisterSheet();
|
||||
const char* getEffectName(unsigned char effect);
|
||||
int init(DivEngine* parent, int channels, int sugRate, unsigned int flags);
|
||||
void quit();
|
||||
~DivPlatformTX81Z();
|
||||
};
|
||||
#endif
|
||||
|
|
@ -493,6 +493,7 @@ const int availableSystems[]={
|
|||
DIV_SYSTEM_OPL2_DRUMS,
|
||||
DIV_SYSTEM_OPL3,
|
||||
DIV_SYSTEM_OPL3_DRUMS,
|
||||
DIV_SYSTEM_OPZ,
|
||||
DIV_SYSTEM_TIA,
|
||||
DIV_SYSTEM_SAA1099,
|
||||
DIV_SYSTEM_AY8930,
|
||||
|
|
|
|||
Loading…
Reference in a new issue