Amiga: validation "export"

only for testing purposes!
wavetables are missing but I might add that at some point
This commit is contained in:
tildearrow 2023-03-15 18:16:47 -05:00
parent 32298f6ab3
commit 4b708e98cf
4 changed files with 99 additions and 40 deletions

2
.gitignore vendored
View File

@ -22,3 +22,5 @@ android/app/.cxx/
CMakeSettings.json CMakeSettings.json
CMakePresets.json CMakePresets.json
extern/imgui_patched/examples/ extern/imgui_patched/examples/
src/asm/68k/amigatest/*.bin
src/asm/68k/amigatest/player

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@ -1,4 +1,4 @@
all: player all: player
player: player.s sample.bin seq.bin wave.bin player: player.s sample.bin seq.bin wave.bin
vasmm68k_mot -Fhunkexe -kick1hunks -o player player.s vasmm68k_mot -Fhunkexe -kick1hunks -nosym -o player player.s

View File

@ -4,6 +4,7 @@
; incomplete! ; incomplete!
VPOSR = $dff004 VPOSR = $dff004
VHPOSR = $dff006
COLOR00 = $dff180 COLOR00 = $dff180
chipBase=$dff000 chipBase=$dff000
@ -18,42 +19,70 @@ AUD0LEN = $a4
AUD0PER = $a6 AUD0PER = $a6
AUD0VOL = $a8 AUD0VOL = $a8
AUD0DAT = $aa AUD0DAT = $aa
AUD1VOL = $b8
AUD2VOL = $c8
AUD3VOL = $d8
code_c code_c
init:
lea chipBase,a0
move.w #15,DMACON(a0)
waitCon:
move.w DMACONR(a0),d0
andi.w #15,d0
bne waitCon
move.w #$8200,DMACON(a0)
move.w #$40,AUD0VOL(a0)
move.w #$40,AUD1VOL(a0)
move.w #$40,AUD2VOL(a0)
move.w #$40,AUD3VOL(a0)
lea seqAddr(pc),a0
lea sequence(pc),a1
move.l a1,(a0)
main: main:
jsr waitVBlank bsr waitVBlank
move.w curColor,d0 ;move.w curColor,d0
move.w d0,COLOR00 ;move.w d0,COLOR00
addi.w #1,d0 ;addi.w #1,d0
move.w d0,curColor ;move.w d0,curColor
jsr nextTick bsr nextTick
jmp main bra main
waitVBlank: waitVBlank:
move.l (VPOSR),d0 move.l (VPOSR),d0
and.l #$1ff00,d0 and.l #$1ff00,d0
cmp.l #$12c00,d0 cmp.l #$8c00,d0
bne waitVBlank bne waitVBlank
waitVBlank2:
move.l (VPOSR),d0
and.l #$1ff00,d0
cmp.l #$8d00,d0
bne waitVBlank2
rts rts
nextTick: nextTick:
lea state(pc),a4 lea state(pc),a4
move.w (a4),d0 move.w (a4),d0
subi.w #1,d0 subi.w #1,d0
bmi nextTick1 bmi nextTick0
move.w d0,(a4) move.w d0,(a4)
rts rts
nextTick1: nextTick0:
move.l seqAddr(pc),a2 move.l seqAddr(pc),a2
nextTick1:
; get next command ; get next command
clr.w d0
move.b (a2)+,d0 move.b (a2)+,d0
move.w #$0ff,d4
move.w d4,COLOR00
testSpecial: testSpecial:
cmp.b #$f0,d0 cmp.w #$f0,d0
blt testChannel bmi testChannel
testF1: testF1:
; f1 - next tick ; f1 - next tick
@ -76,7 +105,7 @@ testF3:
bne testF6 bne testF6
clr.w d2 clr.w d2
move.b (a2)+,d2 move.b (a2)+,d2
rol.w #8,d2 lsl.w #8,d2
or.b (a2)+,d2 or.b (a2)+,d2
move.w d2,(a4) move.w d2,(a4)
bra endTick bra endTick
@ -84,11 +113,23 @@ testF6:
; f6 - write DMACON ; f6 - write DMACON
cmp.b #$f6,d0 cmp.b #$f6,d0
bne testFE bne testFE
move.w #$f00,d4
move.w d4,COLOR00
clr.w d2 clr.w d2
move.b (a2)+,d2 move.b (a2)+,d2
rol.w #8,d2 lsl.w #8,d2
or.b (a2)+,d2 or.b (a2)+,d2
move.w d2,chipBase+DMACON move.w d2,chipBase+DMACON
; wait for DMACON to be done
move.b (VHPOSR),d0
dmaConWait:
cmp.b (VHPOSR),d0
beq dmaConWait
; wait for DMACON to be done -2
move.b (VHPOSR),d0
dmaConWait1:
cmp.b (VHPOSR),d0
beq dmaConWait1
bra nextTick1 bra nextTick1
testFE: testFE:
; fe - write ADKCON ; fe - write ADKCON
@ -96,7 +137,7 @@ testFE:
bne testFF bne testFF
clr.w d2 clr.w d2
move.b (a2)+,d2 move.b (a2)+,d2
rol.w #8,d2 lsl.w #8,d2
or.b (a2)+,d2 or.b (a2)+,d2
move.w d2,chipBase+ADKCON move.w d2,chipBase+ADKCON
bra nextTick1 bra nextTick1
@ -104,7 +145,10 @@ testFF:
; ff - end of song ; ff - end of song
cmp.b #$ff,d0 cmp.b #$ff,d0
bne testOther bne testOther
bra nextTick1 theEnd:
move.w #$fff,d4
move.w d4,COLOR00
bra theEnd
testOther: testOther:
; something else ; something else
bra nextTick1 bra nextTick1
@ -118,25 +162,27 @@ testChannel:
; check for 0 ; check for 0
bne chanNotZero bne chanNotZero
; write loc/len ; write loc/len
move.w #$f0f,d4
move.w d4,COLOR00
clr.l d2 clr.l d2
move.b (a2)+,d2 move.b (a2)+,d2
rol.w #8,d2 lsl.l #8,d2
or.b (a2)+,d2 or.b (a2)+,d2
rol.w #8,d2 lsl.l #8,d2
or.b (a2)+,d2 or.b (a2)+,d2
add.l sampleData(pc),d2 lea sampleData(pc),a0
add.l a0,d2
lea chipBase,a0 lea chipBase,a0
or.b d1,d0 move.b d1,d0
addi.b #AUDBASE,d0 andi.l #$ff,d0
andi.w #$ff,d0 addi.l #$a0,d0
adda.w d0,a0 adda.l d0,a0
move.l d2,(a0) ; location move.l d2,(a0)+ ; location
clr.w d2 clr.w d2
move.b (a2)+,d2 move.b (a2)+,d2
rol.w #8,d2 lsl.w #8,d2
or.b (a2)+,d2 or.b (a2)+,d2
adda.w #4,a0 move.w d2,(a0) ; length
move.l d2,(a0) ; length
bra nextTick1 bra nextTick1
chanNotZero: chanNotZero:
; check for 8 (VOL) ; check for 8 (VOL)
@ -150,14 +196,16 @@ chanOther:
; get value and write ; get value and write
clr.w d2 clr.w d2
move.b (a2)+,d2 move.b (a2)+,d2
rol.w #8,d2 lsl.w #8,d2
or.b (a2)+,d2 or.b (a2)+,d2
chanWrite: chanWrite:
move.w #$ff0,d4
move.w d4,COLOR00
lea chipBase,a0 lea chipBase,a0
or.b d1,d0 or.b d1,d0
addi.b #AUDBASE,d0 addi.b #AUDBASE,d0
andi.w #$ff,d0 andi.l #$ff,d0
adda.w d0,a0 adda.l d0,a0
move.w d2,(a0) move.w d2,(a0)
invalidCmd: invalidCmd:
bra nextTick1 bra nextTick1
@ -165,9 +213,12 @@ invalidCmd:
endTick: endTick:
lea seqAddr(pc),a3 lea seqAddr(pc),a3
move.l a2,(a3) move.l a2,(a3)
move.w #$000,d4
move.w d4,COLOR00
rts rts
data_c data_c
cnop 0,4
curColor: curColor:
dc.w 0 dc.w 0
@ -175,16 +226,22 @@ curColor:
state: state:
dc.w 0 ; ticks dc.w 0 ; ticks
cnop 0,4
seqAddr: seqAddr:
dc.l sequence dc.l 0
sampleData: cnop 0,4
incbin "sample.bin"
data_f
sequence: sequence:
incbin "seq.bin" incbin "seq.bin"
cnop 0,4
sampleData:
incbin "sample.bin"
;data_f
wavetable: wavetable:
incbin "wave.bin" incbin "wave.bin"

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@ -97,10 +97,10 @@ std::vector<DivROMExportOutput> DivExportAmigaValidation::go(DivEngine* e) {
seq->writeC(0xf1); seq->writeC(0xf1);
} else if (delta<256) { } else if (delta<256) {
seq->writeC(0xf2); seq->writeC(0xf2);
seq->writeC(delta); seq->writeC(delta-1);
} else if (delta<65536) { } else if (delta<32768) {
seq->writeC(0xf3); seq->writeC(0xf3);
seq->writeS_BE(delta); seq->writeS_BE(delta-1);
} }
lastTick=songTick; lastTick=songTick;
} }