SCC: VGM export, forceIns bug fix and 10xx

This commit is contained in:
tildearrow 2022-05-11 02:20:14 -05:00
parent 0c0a97c21b
commit 35ff5430d3
3 changed files with 65 additions and 9 deletions

View File

@ -21,7 +21,7 @@
#include "../engine.h"
#include <math.h>
#define CHIP_DIVIDER 32
#define CHIP_DIVIDER 16
#define rWrite(a,v) {if (!skipRegisterWrites) {scc->scc_w(true,a,v); regPool[a]=v; if (dumpWrites) addWrite(a,v); }}
@ -281,7 +281,9 @@ void DivPlatformSCC::forceIns() {
for (int i=0; i<5; i++) {
chan[i].insChanged=true;
chan[i].freqChanged=true;
updateWave(i);
if (chan[i].active) {
updateWave(i);
}
}
}
@ -326,7 +328,9 @@ void DivPlatformSCC::notifyWaveChange(int wave) {
for (int i=0; i<5; i++) {
if (chan[i].wave==wave) {
chan[i].ws.changeWave1(chan[i].wave);
updateWave(i);
if (chan[i].active) {
updateWave(i);
}
}
}
}
@ -358,8 +362,8 @@ int DivPlatformSCC::init(DivEngine* p, int channels, int sugRate, unsigned int f
isMuted[i]=false;
oscBuf[i]=new DivDispatchOscBuffer;
}
chipClock=COLOR_NTSC;
rate=chipClock/16;
chipClock=COLOR_NTSC/2.0;
rate=chipClock/8;
for (int i=0; i<5; i++) {
oscBuf[i]->rate=rate;
}

View File

@ -1459,11 +1459,13 @@ void DivEngine::registerSystems() {
);
sysDefs[DIV_SYSTEM_SCC]=new DivSysDef(
"Konami SCC", NULL, 0xa1, 0, 5, false, true, 0, false,
"Konami SCC", NULL, 0xa1, 0, 5, false, true, 0x161, false,
{"Channel 1", "Channel 2", "Channel 3", "Channel 4", "Channel 5"},
{"CH1", "CH2", "CH3", "CH4", "CH5"},
{DIV_CH_WAVE, DIV_CH_WAVE, DIV_CH_WAVE, DIV_CH_WAVE, DIV_CH_WAVE},
{DIV_INS_SCC, DIV_INS_SCC, DIV_INS_SCC, DIV_INS_SCC, DIV_INS_SCC}
{DIV_INS_SCC, DIV_INS_SCC, DIV_INS_SCC, DIV_INS_SCC, DIV_INS_SCC},
{},
waveOnlyEffectHandler
);
auto oplDrumsEffectHandler=[this](int ch, unsigned char effect, unsigned char effectVal) -> bool {
@ -1740,11 +1742,13 @@ void DivEngine::registerSystems() {
);
sysDefs[DIV_SYSTEM_SCC_PLUS]=new DivSysDef(
"Konami SCC+", NULL, 0xb4, 0, 5, false, true, 0, false,
"Konami SCC+", NULL, 0xb4, 0, 5, false, true, 0x161, false,
{"Channel 1", "Channel 2", "Channel 3", "Channel 4", "Channel 5"},
{"CH1", "CH2", "CH3", "CH4", "CH5"},
{DIV_CH_WAVE, DIV_CH_WAVE, DIV_CH_WAVE, DIV_CH_WAVE, DIV_CH_WAVE},
{DIV_INS_SCC, DIV_INS_SCC, DIV_INS_SCC, DIV_INS_SCC, DIV_INS_SCC}
{DIV_INS_SCC, DIV_INS_SCC, DIV_INS_SCC, DIV_INS_SCC, DIV_INS_SCC},
{},
waveOnlyEffectHandler
);
sysDefs[DIV_SYSTEM_SOUND_UNIT]=new DivSysDef(

View File

@ -598,6 +598,36 @@ void DivEngine::performVGMWrite(SafeWriter* w, DivSystem sys, DivRegWrite& write
break;
}
break;
case DIV_SYSTEM_SCC:
if (write.addr<0x80) {
w->writeC(0xd2);
w->writeC(0);
w->writeC(baseAddr2|(write.addr&0x7f));
w->writeC(write.val&0xff);
} else if (write.addr<0x8a) {
w->writeC(0xd2);
w->writeC(1);
w->writeC(baseAddr2|((write.addr-0x80)&0x7f));
w->writeC(write.val&0xff);
} else if (write.addr<0x8f) {
w->writeC(0xd2);
w->writeC(2);
w->writeC(baseAddr2|((write.addr-0x8a)&0x7f));
w->writeC(write.val&0xff);
} else if (write.addr<0x90) {
w->writeC(0xd2);
w->writeC(3);
w->writeC(baseAddr2|((write.addr-0x8f)&0x7f));
w->writeC(write.val&0xff);
} else if (write.addr>=0xe0) {
w->writeC(0xd2);
w->writeC(5);
w->writeC(baseAddr2|((write.addr-0xe0)&0x7f));
w->writeC(write.val&0xff);
} else {
logW("SCC: writing to unmapped address %.2x!",write.addr);
}
break;
default:
logW("write not handled!");
break;
@ -988,6 +1018,24 @@ SafeWriter* DivEngine::saveVGM(bool* sysToExport, bool loop, int version) {
howManyChips++;
}
break;
case DIV_SYSTEM_SCC:
case DIV_SYSTEM_SCC_PLUS:
if (!hasK051649) {
hasK051649=disCont[i].dispatch->chipClock;
if (song.system[i]==DIV_SYSTEM_SCC_PLUS) {
hasK051649|=0x80000000;
}
willExport[i]=true;
} else if (!(hasK051649&0x40000000)) {
isSecond[i]=true;
willExport[i]=true;
hasK051649|=0x40000000;
if (song.system[i]==DIV_SYSTEM_SCC_PLUS) {
hasK051649|=0x80000000;
}
howManyChips++;
}
break;
default:
break;
}