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OPL: YMF262-LLE, part 1
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a7b3f8edf7
commit
2558da9418
2 changed files with 133 additions and 12 deletions
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@ -661,6 +661,108 @@ void DivPlatformOPL::acquire_nukedLLE2(short** buf, size_t len) {
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}
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void DivPlatformOPL::acquire_nukedLLE3(short** buf, size_t len) {
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int chOut[20];
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for (size_t h=0; h<len; h++) {
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//int curCycle=0;
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//unsigned char subCycle=0;
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for (int i=0; i<20; i++) {
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chOut[i]=0;
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}
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while (true) {
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lastSH=fm_lle3.o_smpac;
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lastSH2=fm_lle3.o_smpbd;
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lastSY=fm_lle3.o_sy;
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// register control
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if (waitingBusy) {
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if (delay<62) {
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fm_lle3.input.cs=0;
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fm_lle3.input.rd=0;
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fm_lle3.input.wr=1;
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fm_lle3.input.address=0;
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}
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} else {
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if (!writes.empty()) {
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QueuedWrite& w=writes.front();
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if (w.addrOrVal) {
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regPool[w.addr&511]=w.val;
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fm_lle3.input.cs=0;
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fm_lle3.input.rd=1;
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fm_lle3.input.wr=0;
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fm_lle3.input.address=(w.addr&0x100)?3:1;
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fm_lle3.input.data_i=w.val;
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writes.pop();
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delay=64;
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} else {
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fm_lle3.input.cs=0;
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fm_lle3.input.rd=1;
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fm_lle3.input.wr=0;
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fm_lle3.input.address=(w.addr&0x100)?2:0;
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fm_lle3.input.data_i=w.addr&0xff;
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w.addrOrVal=true;
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// weird. wasn't it 12?
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delay=64;
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}
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waitingBusy=true;
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}
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}
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fm_lle3.input.mclk=1;
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FMOPL3_Clock(&fm_lle3);
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fm_lle3.input.mclk=0;
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FMOPL3_Clock(&fm_lle3);
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if (waitingBusy) {
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if (--delay<0) waitingBusy=false;
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}
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/*if (!(++subCycle&3)) {
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// TODO: chan osc
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curCycle++;
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}*/
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if (fm_lle3.o_sy && !lastSY) {
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dacVal>>=1;
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dacVal|=(fm_lle3.o_doab&1)<<17;
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dacVal2>>=1;
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dacVal2|=(fm_lle3.o_docd&1)<<17;
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}
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if (!fm_lle3.o_smpbd && lastSH2) {
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dacOut3[0]=((dacVal>>1)&0xffff)-0x8000;
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dacOut3[2]=((dacVal2>>1)&0xffff)-0x8000;
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}
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if (!fm_lle3.o_smpac && lastSH) {
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dacOut3[1]=((dacVal>>1)&0xffff)-0x8000;
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dacOut3[3]=((dacVal2>>1)&0xffff)-0x8000;
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break;
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}
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}
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for (int i=0; i<20; i++) {
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if (i>=15 && properDrums) {
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chOut[i]<<=1;
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} else {
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chOut[i]<<=2;
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}
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if (chOut[i]<-32768) chOut[i]=-32768;
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if (chOut[i]>32767) chOut[i]=32767;
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oscBuf[i]->data[oscBuf[i]->needle++]=chOut[i];
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}
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for (int i=0; i<MIN(4,totalOutputs); i++) {
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if (dacOut3[i]<-32768) dacOut3[i]=-32768;
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if (dacOut3[i]>32767) dacOut3[i]=32767;
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buf[i][h]=dacOut3[i];
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}
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}
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}
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void DivPlatformOPL::acquire(short** buf, size_t len) {
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@ -2015,27 +2117,43 @@ void DivPlatformOPL::reset() {
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memset(regPool,0,512);
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dacVal=0;
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dacVal2=0;
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dacOut=0;
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dacOut3[0]=0;
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dacOut3[1]=0;
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dacOut3[2]=0;
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dacOut3[3]=0;
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lastSH=false;
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lastSH2=false;
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lastSY=false;
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waitingBusy=true;
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const unsigned int downsampledRate=(unsigned int)((double)rate*round(COLOR_NTSC/72.0)/(double)chipRateBase);
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if (emuCore==2) {
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// reset 2
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memset(&fm_lle2,0,sizeof(fmopl2_t));
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fm_lle2.input.ic=0;
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for (int i=0; i<80; i++) {
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fm_lle2.input.mclk=1;
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FMOPL2_Clock(&fm_lle2);
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fm_lle2.input.mclk=0;
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FMOPL2_Clock(&fm_lle2);
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if (chipType==3 || chipType==759 || chipType==4) {
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// reset 3
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memset(&fm_lle3,0,sizeof(fmopl3_t));
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fm_lle3.input.ic=0;
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for (int i=0; i<400; i++) {
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fm_lle3.input.mclk=1;
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FMOPL3_Clock(&fm_lle3);
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fm_lle3.input.mclk=0;
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FMOPL3_Clock(&fm_lle3);
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}
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fm_lle3.input.ic=1;
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} else {
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// reset 2
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memset(&fm_lle2,0,sizeof(fmopl2_t));
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fm_lle2.input.ic=0;
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for (int i=0; i<80; i++) {
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fm_lle2.input.mclk=1;
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FMOPL2_Clock(&fm_lle2);
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fm_lle2.input.mclk=0;
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FMOPL2_Clock(&fm_lle2);
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}
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fm_lle2.input.ic=1;
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}
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fm_lle2.input.ic=1;
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// reset 3
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memset(&fm_lle3,0,sizeof(fmopl3_t));
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} else if (emuCore==1) {
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switch (chipType) {
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case 1:
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@ -75,8 +75,11 @@ class DivPlatformOPL: public DivDispatch {
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FixedQueue<QueuedWrite,2048> writes;
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unsigned int dacVal;
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unsigned int dacVal2;
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int dacOut;
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int dacOut3[4];
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bool lastSH;
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bool lastSH2;
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bool lastSY;
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bool waitingBusy;
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