OPL: Correct CHIP_FREQBASE to match clock ratio

This changes from 9440540 to 9437184
This commit is contained in:
Natt Akuma 2022-07-01 17:33:33 +07:00
parent e3a22ea7c1
commit 02b28e6e7d
2 changed files with 18 additions and 18 deletions

View File

@ -1669,7 +1669,7 @@ void DivPlatformOPL::setOPLType(int type, bool drums) {
slots=drums?slotsDrums:slotsNonDrums; slots=drums?slotsDrums:slotsNonDrums;
chanMap=drums?chanMapOPL2Drums:chanMapOPL2; chanMap=drums?chanMapOPL2Drums:chanMapOPL2;
outChanMap=outChanMapOPL2; outChanMap=outChanMapOPL2;
chipFreqBase=9440540*0.25; chipFreqBase=32768*72;
chans=9; chans=9;
melodicChans=drums?6:9; melodicChans=drums?6:9;
totalChans=drums?11:9; totalChans=drums?11:9;
@ -1683,7 +1683,7 @@ void DivPlatformOPL::setOPLType(int type, bool drums) {
slots=drums?slotsDrums:slotsNonDrums; slots=drums?slotsDrums:slotsNonDrums;
chanMap=drums?chanMapOPL3Drums:chanMapOPL3; chanMap=drums?chanMapOPL3Drums:chanMapOPL3;
outChanMap=outChanMapOPL3; outChanMap=outChanMapOPL3;
chipFreqBase=9440540; chipFreqBase=32768*288;
chans=18; chans=18;
melodicChans=drums?15:18; melodicChans=drums?15:18;
totalChans=drums?20:18; totalChans=drums?20:18;
@ -1735,9 +1735,6 @@ void DivPlatformOPL::setFlags(unsigned int flags) {
default: default:
case 1: case 2: case 8950: case 1: case 2: case 8950:
switch (flags&0xff) { switch (flags&0xff) {
case 0x00:
chipClock=COLOR_NTSC;
break;
case 0x01: case 0x01:
chipClock=COLOR_PAL*4.0/5.0; chipClock=COLOR_PAL*4.0/5.0;
break; break;
@ -1753,15 +1750,15 @@ void DivPlatformOPL::setFlags(unsigned int flags) {
case 0x05: case 0x05:
chipClock=3500000.0; chipClock=3500000.0;
break; break;
default:
chipClock=COLOR_NTSC;
break;
} }
rate=chipClock/72; rate=chipClock/72;
chipRateBase=double(rate); chipRateBase=double(rate);
break; break;
case 3: case 3:
switch (flags&0xff) { switch (flags&0xff) {
case 0x00:
chipClock=COLOR_NTSC*4.0;
break;
case 0x01: case 0x01:
chipClock=COLOR_PAL*16.0/5.0; chipClock=COLOR_PAL*16.0/5.0;
break; break;
@ -1774,28 +1771,31 @@ void DivPlatformOPL::setFlags(unsigned int flags) {
case 0x04: case 0x04:
chipClock=15000000.0; chipClock=15000000.0;
break; break;
default:
chipClock=COLOR_NTSC*4.0;
break;
} }
rate=chipClock/288; rate=chipClock/288;
chipRateBase=double(rate); chipRateBase=rate;
break; break;
case 4: case 4:
switch (flags&0xff) { switch (flags&0xff) {
case 0x02:
chipClock=33868800.0;
break;
case 0x00:
chipClock=COLOR_NTSC*8.0;
break;
case 0x01: case 0x01:
chipClock=COLOR_PAL*32.0/5.0; chipClock=COLOR_PAL*32.0/5.0;
break; break;
case 0x02:
chipClock=33868800.0;
break;
default:
chipClock=COLOR_NTSC*8.0;
break;
} }
chipRateBase=double(chipClock)/684.0;
rate=chipClock/768; rate=chipClock/768;
chipRateBase=chipClock/684;
break; break;
case 759: case 759:
rate=48000; rate=48000;
chipRateBase=double(rate); chipRateBase=rate;
chipClock=rate*288; chipClock=rate*288;
break; break;
} }

View File

@ -95,7 +95,7 @@ class DivPlatformOPL: public DivDispatch {
const unsigned char** slots; const unsigned char** slots;
const unsigned short* chanMap; const unsigned short* chanMap;
const unsigned char* outChanMap; const unsigned char* outChanMap;
double chipFreqBase, chipRateBase; int chipFreqBase, chipRateBase;
int delay, chipType, oplType, chans, melodicChans, totalChans, adpcmChan, sampleBank; int delay, chipType, oplType, chans, melodicChans, totalChans, adpcmChan, sampleBank;
unsigned char lastBusy; unsigned char lastBusy;
unsigned char drumState; unsigned char drumState;