2022-03-21 14:02:51 +00:00
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/**
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* Furnace Tracker - multi-system chiptune tracker
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* Copyright (C) 2021-2022 tildearrow and contributors
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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*/
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#include "pet.h"
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#include "../engine.h"
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#include <math.h>
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#define CHIP_DIVIDER 16
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#define SAMP_DIVIDER 4
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const char* regCheatSheet6522[]={
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"T2L", "08",
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2022-06-22 19:42:11 +00:00
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"T2H", "09",
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2022-03-21 14:02:51 +00:00
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"SR", "0A",
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"ACR", "0B",
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2022-06-22 19:42:11 +00:00
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"PCR", "0C",
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2022-03-21 14:02:51 +00:00
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NULL
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};
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const char** DivPlatformPET::getRegisterSheet() {
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return regCheatSheet6522;
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}
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const char* DivPlatformPET::getEffectName(unsigned char effect) {
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switch (effect) {
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case 0x10:
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return "10xx: Change waveform";
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break;
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}
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return NULL;
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}
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2022-06-22 19:42:11 +00:00
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// high-level emulation of 6522 shift register and driver software for now
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void DivPlatformPET::rWrite(unsigned int addr, unsigned char val) {
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bool hwSROutput=((regPool[11]>>2)&7)==4;
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switch (addr) {
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case 9:
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// simulate phase reset from switching between hw/sw shift registers
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if ((regPool[9]==0)^(val==0)) {
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chan.sreg=chan.wave;
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}
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break;
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case 10:
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chan.sreg=val;
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if (hwSROutput) chan.cnt=2;
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break;
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}
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regPool[addr]=val;
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}
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2022-03-21 14:02:51 +00:00
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void DivPlatformPET::acquire(short* bufL, short* bufR, size_t start, size_t len) {
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2022-06-22 19:42:11 +00:00
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bool hwSROutput=((regPool[11]>>2)&7)==4;
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if (chan.enable) {
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int reload=regPool[8]*2+4;
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if (!hwSROutput) {
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reload+=regPool[9]*512;
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}
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2022-03-21 14:02:51 +00:00
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for (size_t h=start; h<start+len; h++) {
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2022-06-22 19:42:11 +00:00
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if (SAMP_DIVIDER>chan.cnt) {
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chan.out=(chan.sreg&1)*32767;
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chan.sreg=(chan.sreg>>1)|((chan.sreg&1)<<7);
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chan.cnt+=reload-SAMP_DIVIDER;
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} else {
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chan.cnt-=SAMP_DIVIDER;
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2022-03-21 14:02:51 +00:00
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}
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bufL[h]=chan.out;
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bufR[h]=chan.out;
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per-channel oscilloscope, part 5
SAA1099 (SAASound and MAME), Lynx, MMC5, N163, PC Engine, PC Speaker,
PET, QSound, WonderSwan, VERA, VIC-20, VRC6 and X1-010!
2022-05-01 07:40:03 +00:00
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oscBuf->data[oscBuf->needle++]=chan.out;
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2022-03-21 14:02:51 +00:00
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}
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2022-06-22 19:42:11 +00:00
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// emulate driver writes to PCR
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if (!hwSROutput) regPool[12]=chan.out?0xe0:0xc0;
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2022-03-21 14:02:51 +00:00
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} else {
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chan.out=0;
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for (size_t h=start; h<start+len; h++) {
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bufL[h]=0;
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bufR[h]=0;
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per-channel oscilloscope, part 5
SAA1099 (SAASound and MAME), Lynx, MMC5, N163, PC Engine, PC Speaker,
PET, QSound, WonderSwan, VERA, VIC-20, VRC6 and X1-010!
2022-05-01 07:40:03 +00:00
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oscBuf->data[oscBuf->needle++]=0;
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2022-03-21 14:02:51 +00:00
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}
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}
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}
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void DivPlatformPET::writeOutVol() {
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if (chan.active && !isMuted && chan.outVol>0) {
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2022-06-22 19:42:11 +00:00
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chan.enable=true;
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rWrite(11,regPool[9]==0?16:0);
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2022-03-21 14:02:51 +00:00
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} else {
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2022-06-22 19:42:11 +00:00
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chan.enable=false;
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2022-03-21 14:02:51 +00:00
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rWrite(11,0);
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}
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}
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2022-04-15 20:01:11 +00:00
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void DivPlatformPET::tick(bool sysTick) {
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2022-03-21 14:02:51 +00:00
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chan.std.next();
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2022-04-10 05:01:55 +00:00
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if (chan.std.vol.had) {
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chan.outVol=chan.std.vol.val&chan.vol;
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2022-03-21 14:02:51 +00:00
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writeOutVol();
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}
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2022-04-10 05:01:55 +00:00
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if (chan.std.arp.had) {
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2022-03-21 14:02:51 +00:00
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if (!chan.inPorta) {
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2022-04-10 05:01:55 +00:00
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if (chan.std.arp.mode) {
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chan.baseFreq=NOTE_PERIODIC(chan.std.arp.val);
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2022-03-21 14:02:51 +00:00
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} else {
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2022-04-10 05:01:55 +00:00
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chan.baseFreq=NOTE_PERIODIC(chan.note+chan.std.arp.val);
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2022-03-21 14:02:51 +00:00
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}
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}
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chan.freqChanged=true;
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} else {
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2022-04-10 05:01:55 +00:00
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if (chan.std.arp.mode && chan.std.arp.finished) {
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2022-03-21 14:02:51 +00:00
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chan.baseFreq=NOTE_PERIODIC(chan.note);
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chan.freqChanged=true;
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}
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}
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2022-04-10 05:01:55 +00:00
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if (chan.std.wave.had) {
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if (chan.wave!=chan.std.wave.val) {
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chan.wave=chan.std.wave.val;
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2022-03-21 18:37:22 +00:00
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rWrite(10,chan.wave);
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2022-03-21 14:02:51 +00:00
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}
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}
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2022-04-16 06:39:40 +00:00
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if (chan.std.pitch.had) {
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2022-08-16 02:46:36 +00:00
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if (chan.std.pitch.mode) {
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chan.pitch2+=chan.std.pitch.val;
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CLAMP_VAR(chan.pitch2,-32768,32767);
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} else {
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chan.pitch2=chan.std.pitch.val;
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2022-04-16 06:39:40 +00:00
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}
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2022-08-16 02:46:36 +00:00
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chan.freqChanged=true;
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}
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2022-03-21 14:02:51 +00:00
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if (chan.freqChanged || chan.keyOn || chan.keyOff) {
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2022-06-22 19:42:11 +00:00
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chan.freq=parent->calcFreq(chan.baseFreq,chan.pitch,true,0,chan.pitch2,chipClock,CHIP_DIVIDER)-2;
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if (chan.freq>65535) chan.freq=65535;
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if (chan.freq<0) chan.freq=0;
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rWrite(8,chan.freq&0xff);
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rWrite(9,chan.freq>>8);
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2022-03-21 14:02:51 +00:00
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if (chan.keyOn) {
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2022-04-10 05:01:55 +00:00
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if (!chan.std.vol.will) {
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2022-03-21 14:02:51 +00:00
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chan.outVol=chan.vol;
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}
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chan.keyOn=false;
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}
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if (chan.keyOff) {
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chan.keyOff=false;
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}
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2022-06-22 19:42:11 +00:00
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// update mode setting and channel enable
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writeOutVol();
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2022-03-21 14:02:51 +00:00
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chan.freqChanged=false;
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}
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}
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int DivPlatformPET::dispatch(DivCommand c) {
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switch (c.cmd) {
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case DIV_CMD_NOTE_ON: {
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2022-04-21 07:24:06 +00:00
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DivInstrument* ins=parent->getIns(chan.ins,DIV_INS_PET);
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2022-03-21 14:02:51 +00:00
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if (c.value!=DIV_NOTE_NULL) {
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chan.baseFreq=NOTE_PERIODIC(c.value);
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chan.freqChanged=true;
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chan.note=c.value;
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}
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chan.active=true;
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chan.keyOn=true;
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2022-04-28 06:31:16 +00:00
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chan.macroInit(ins);
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2022-06-01 00:03:31 +00:00
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if (!parent->song.brokenOutVol && !chan.std.vol.will) {
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chan.outVol=chan.vol;
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}
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2022-03-21 14:02:51 +00:00
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break;
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}
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case DIV_CMD_NOTE_OFF:
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chan.active=false;
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chan.keyOff=true;
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2022-04-28 06:31:16 +00:00
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chan.macroInit(NULL);
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2022-03-21 14:02:51 +00:00
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break;
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case DIV_CMD_NOTE_OFF_ENV:
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case DIV_CMD_ENV_RELEASE:
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chan.std.release();
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break;
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case DIV_CMD_INSTRUMENT:
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if (chan.ins!=c.value || c.value2==1) {
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chan.ins=c.value;
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}
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break;
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case DIV_CMD_VOLUME:
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if (chan.vol!=c.value) {
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chan.vol=c.value;
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2022-04-10 05:01:55 +00:00
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if (!chan.std.vol.had) {
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2022-03-21 14:02:51 +00:00
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chan.outVol=chan.vol;
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writeOutVol();
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}
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}
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break;
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case DIV_CMD_GET_VOLUME:
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return chan.vol;
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break;
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case DIV_CMD_PITCH:
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chan.pitch=c.value;
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chan.freqChanged=true;
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break;
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case DIV_CMD_WAVE:
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chan.wave=c.value;
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2022-03-21 18:37:22 +00:00
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rWrite(10,chan.wave);
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2022-03-21 14:02:51 +00:00
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break;
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case DIV_CMD_NOTE_PORTA: {
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int destFreq=NOTE_PERIODIC(c.value2);
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bool return2=false;
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if (destFreq>chan.baseFreq) {
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chan.baseFreq+=c.value;
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if (chan.baseFreq>=destFreq) {
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chan.baseFreq=destFreq;
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return2=true;
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}
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} else {
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chan.baseFreq-=c.value;
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if (chan.baseFreq<=destFreq) {
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chan.baseFreq=destFreq;
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return2=true;
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}
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}
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chan.freqChanged=true;
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if (return2) {
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chan.inPorta=false;
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return 2;
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}
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break;
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}
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case DIV_CMD_LEGATO:
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2022-04-10 05:01:55 +00:00
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chan.baseFreq=NOTE_PERIODIC(c.value+((chan.std.arp.will && !chan.std.arp.mode)?(chan.std.arp.val):(0)));
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2022-03-21 14:02:51 +00:00
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chan.freqChanged=true;
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chan.note=c.value;
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break;
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case DIV_CMD_PRE_PORTA:
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if (chan.active && c.value2) {
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2022-04-28 06:31:16 +00:00
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if (parent->song.resetMacroOnPorta) chan.macroInit(parent->getIns(chan.ins,DIV_INS_PET));
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2022-03-21 14:02:51 +00:00
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}
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2022-07-04 06:43:59 +00:00
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if (!chan.inPorta && c.value && !parent->song.brokenPortaArp && chan.std.arp.will) chan.baseFreq=NOTE_PERIODIC(chan.note);
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2022-03-21 14:02:51 +00:00
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chan.inPorta=c.value;
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break;
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case DIV_CMD_GET_VOLMAX:
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return 1;
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break;
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case DIV_ALWAYS_SET_VOLUME:
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return 1;
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break;
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default:
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break;
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}
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return 1;
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}
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void DivPlatformPET::muteChannel(int ch, bool mute) {
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isMuted=mute;
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writeOutVol();
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}
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void DivPlatformPET::forceIns() {
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chan.insChanged=true;
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chan.freqChanged=true;
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writeOutVol();
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}
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void* DivPlatformPET::getChanState(int ch) {
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return &chan;
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}
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2022-06-05 23:17:00 +00:00
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DivMacroInt* DivPlatformPET::getChanMacroInt(int ch) {
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return &chan.std;
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}
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per-channel oscilloscope, part 5
SAA1099 (SAASound and MAME), Lynx, MMC5, N163, PC Engine, PC Speaker,
PET, QSound, WonderSwan, VERA, VIC-20, VRC6 and X1-010!
2022-05-01 07:40:03 +00:00
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DivDispatchOscBuffer* DivPlatformPET::getOscBuffer(int ch) {
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return oscBuf;
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}
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2022-03-21 14:02:51 +00:00
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unsigned char* DivPlatformPET::getRegisterPool() {
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return regPool;
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}
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int DivPlatformPET::getRegisterPoolSize() {
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return 16;
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}
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void DivPlatformPET::reset() {
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memset(regPool,0,16);
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chan=Channel();
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2022-04-15 10:37:23 +00:00
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chan.std.setEngine(parent);
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2022-03-21 14:02:51 +00:00
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}
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bool DivPlatformPET::isStereo() {
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return false;
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}
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void DivPlatformPET::notifyInsDeletion(void* ins) {
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chan.std.notifyInsDeletion((DivInstrument*)ins);
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}
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void DivPlatformPET::poke(unsigned int addr, unsigned short val) {
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rWrite(addr,val);
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}
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void DivPlatformPET::poke(std::vector<DivRegWrite>& wlist) {
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for (DivRegWrite& i: wlist) rWrite(i.addr,i.val);
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}
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int DivPlatformPET::init(DivEngine* p, int channels, int sugRate, unsigned int flags) {
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parent=p;
|
|
|
|
dumpWrites=false;
|
|
|
|
skipRegisterWrites=false;
|
|
|
|
chipClock=1000000;
|
|
|
|
rate=chipClock/SAMP_DIVIDER; // = 250000kHz
|
|
|
|
isMuted=false;
|
per-channel oscilloscope, part 5
SAA1099 (SAASound and MAME), Lynx, MMC5, N163, PC Engine, PC Speaker,
PET, QSound, WonderSwan, VERA, VIC-20, VRC6 and X1-010!
2022-05-01 07:40:03 +00:00
|
|
|
oscBuf=new DivDispatchOscBuffer;
|
|
|
|
oscBuf->rate=rate;
|
2022-03-21 14:02:51 +00:00
|
|
|
reset();
|
|
|
|
return 1;
|
|
|
|
}
|
|
|
|
|
per-channel oscilloscope, part 5
SAA1099 (SAASound and MAME), Lynx, MMC5, N163, PC Engine, PC Speaker,
PET, QSound, WonderSwan, VERA, VIC-20, VRC6 and X1-010!
2022-05-01 07:40:03 +00:00
|
|
|
void DivPlatformPET::quit() {
|
|
|
|
delete oscBuf;
|
|
|
|
}
|
|
|
|
|
2022-03-21 14:02:51 +00:00
|
|
|
DivPlatformPET::~DivPlatformPET() {
|
|
|
|
}
|