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94 lines
3.7 KiB
Markdown
94 lines
3.7 KiB
Markdown
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Performance Counters
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====================
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FFTW measures execution time in the planning stage, optionally taking advantage
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of hardware performance counters. This document describes the supported
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counters and additional steps needed to enable each on different architectures.
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See `./configure --help` for flags for enabling each supported counter.
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See [kernel/cycle.h](kernel/cycle.h) for the code that accesses the counters.
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ARMv7-A (armv7a)
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================
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`CNTVCT`: Virtual Count Register in VMSA
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--------------------------------------
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A 64-bit counter part of Virtual Memory System Architecture.
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Section B4.1.34 in ARM Architecture Reference Manual ARMv7-A/ARMv7-R
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For access from user mode, requires `CNTKCTL.PL0VCTEN == 1`, which must
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be set in kernel mode on each CPU:
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#define CNTKCTL_PL0VCTEN 0x2 /* B4.1.26 in ARM Architecture Rreference */
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uint32_t r;
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asm volatile("mrc p15, 0, %0, c14, c1, 0" : "=r"(r)); /* read */
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r |= CNTKCTL_PL0VCTEN;
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asm volatile("mcr p15, 0, %0, c14, c1, 0" :: "r"(r)); /* write */
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Kernel module source *which can be patched with the above code* available at:
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https://github.com/thoughtpolice/enable_arm_pmu
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`PMCCNTR`: Performance Monitors Cycle Count Register in VMSA
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----------------------------------------------------------
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A 32-bit counter part of Virtual Memory System Architecture.
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Section B4.1.113 in ARM Architecture Reference Manual ARMv7-A/ARMv7-R
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For access from user mode, requires user-mode access to PMU to be enabled
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(`PMUSERENR.EN == 1`), which must be done from kernel mode on each CPU:
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#define PERF_DEF_OPTS (1 | 16)
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/* enable user-mode access to counters */
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asm volatile("mcr p15, 0, %0, c9, c14, 0" :: "r"(1));
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/* Program PMU and enable all counters */
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asm volatile("mcr p15, 0, %0, c9, c12, 0" :: "r"(PERF_DEF_OPTS));
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asm volatile("mcr p15, 0, %0, c9, c12, 1" :: "r"(0x8000000f));
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Kernel module source with the above code available at:
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[GitHub thoughtpolice/enable\_arm\_pmu](https://github.com/thoughtpolice/enable_arm_pmu)
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More information:
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http://neocontra.blogspot.com/2013/05/user-mode-performance-counters-for.html
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ARMv8-A (aarch64)
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=================
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`CNTVCT_EL0`: Counter-timer Virtual Count Register
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------------------------------------------------
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A 64-bit counter, part of Generic Registers.
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Section D8.5.17 in ARM Architecture Reference Manual ARMv8-A
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For user-mode access, requires `CNTKCTL_EL1.EL0VCTEN == 1`, which
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must be set from kernel mode for each CPU:
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#define CNTKCTL_EL0VCTEN 0x2
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uint32_t r;
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asm volatile("mrs %0, CNTKCTL_EL1" : "=r"(r)); /* read */
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r |= CNTKCTL_EL0VCTEN;
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asm volatile("msr CNTKCTL_EL1, %0" :: "r"(r)); /* write */
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*WARNING*: Above code was not tested.
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`PMCCNTR_EL0`: Performance Monitors Cycle Count Register
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------------------------------------------------------
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A 64-bit counter, part of Performance Monitors.
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Section D8.4.2 in ARM Architecture Reference Manual ARMv8-A
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For access from user mode, requires user-mode access to PMU (`PMUSERENR_EL0.EN
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== 1`), which must be set from kernel mode for each CPU:
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#define PERF_DEF_OPTS (1 | 16)
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/* enable user-mode access to counters */
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asm volatile("msr PMUSERENR_EL0, %0" :: "r"(1));
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/* Program PMU and enable all counters */
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asm volatile("msr PMCR_EL0, %0" :: "r"(PERF_DEF_OPTS));
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asm volatile("msr PMCNTENSET_EL0, %0" :: "r"(0x8000000f));
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asm volatile("msr PMCCFILTR_EL0, %0" :: "r"(0));
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Kernel module source with the above code available at:
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[GitHub rdolbeau/enable\_arm\_pmu](https://github.com/rdolbeau/enable_arm_pmu)
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or in [Pull Request #2 at thoughtpolice/enable\_arm\_pmu](https://github.com/thoughtpolice/enable_arm_pmu/pull/2)
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