mirror of
https://github.com/tildearrow/furnace.git
synced 2024-12-04 18:27:25 +00:00
323 lines
9.9 KiB
C
323 lines
9.9 KiB
C
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/*
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* Copyright (c) 2003, 2007-14 Matteo Frigo
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* Copyright (c) 2003, 2007-14 Massachusetts Institute of Technology
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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*
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*/
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/* This file was automatically generated --- DO NOT EDIT */
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/* Generated on Tue Sep 14 10:45:49 EDT 2021 */
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#include "dft/codelet-dft.h"
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#if defined(ARCH_PREFERS_FMA) || defined(ISA_EXTENSION_PREFERS_FMA)
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/* Generated by: ../../../genfft/gen_twiddle_c.native -fma -simd -compact -variables 4 -pipeline-latency 8 -n 12 -name t1bv_12 -include dft/simd/t1b.h -sign 1 */
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/*
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* This function contains 59 FP additions, 42 FP multiplications,
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* (or, 41 additions, 24 multiplications, 18 fused multiply/add),
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* 28 stack variables, 2 constants, and 24 memory accesses
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*/
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#include "dft/simd/t1b.h"
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static void t1bv_12(R *ri, R *ii, const R *W, stride rs, INT mb, INT me, INT ms)
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{
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DVK(KP866025403, +0.866025403784438646763723170752936183471402627);
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DVK(KP500000000, +0.500000000000000000000000000000000000000000000);
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{
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INT m;
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R *x;
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x = ii;
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for (m = mb, W = W + (mb * ((TWVL / VL) * 22)); m < me; m = m + VL, x = x + (VL * ms), W = W + (TWVL * 22), MAKE_VOLATILE_STRIDE(12, rs)) {
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V T1, TK, T6, TA, Tq, TI, Tv, TE, T9, TL, Te, TB, Ti, TH, Tn;
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V TD;
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{
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V T5, T3, T4, T2;
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T1 = LD(&(x[0]), ms, &(x[0]));
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T4 = LD(&(x[WS(rs, 8)]), ms, &(x[0]));
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T5 = BYTW(&(W[TWVL * 14]), T4);
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T2 = LD(&(x[WS(rs, 4)]), ms, &(x[0]));
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T3 = BYTW(&(W[TWVL * 6]), T2);
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TK = VSUB(T3, T5);
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T6 = VADD(T3, T5);
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TA = VFNMS(LDK(KP500000000), T6, T1);
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}
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{
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V Tu, Ts, Tp, Tt, Tr;
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Tp = LD(&(x[WS(rs, 9)]), ms, &(x[WS(rs, 1)]));
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Tq = BYTW(&(W[TWVL * 16]), Tp);
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Tt = LD(&(x[WS(rs, 5)]), ms, &(x[WS(rs, 1)]));
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Tu = BYTW(&(W[TWVL * 8]), Tt);
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Tr = LD(&(x[WS(rs, 1)]), ms, &(x[WS(rs, 1)]));
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Ts = BYTW(&(W[0]), Tr);
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TI = VSUB(Tu, Ts);
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Tv = VADD(Ts, Tu);
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TE = VFNMS(LDK(KP500000000), Tv, Tq);
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}
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{
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V Td, Tb, T8, Tc, Ta;
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T8 = LD(&(x[WS(rs, 6)]), ms, &(x[0]));
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T9 = BYTW(&(W[TWVL * 10]), T8);
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Tc = LD(&(x[WS(rs, 2)]), ms, &(x[0]));
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Td = BYTW(&(W[TWVL * 2]), Tc);
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Ta = LD(&(x[WS(rs, 10)]), ms, &(x[0]));
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Tb = BYTW(&(W[TWVL * 18]), Ta);
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TL = VSUB(Tb, Td);
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Te = VADD(Tb, Td);
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TB = VFNMS(LDK(KP500000000), Te, T9);
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}
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{
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V Tm, Tk, Th, Tl, Tj;
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Th = LD(&(x[WS(rs, 3)]), ms, &(x[WS(rs, 1)]));
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Ti = BYTW(&(W[TWVL * 4]), Th);
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Tl = LD(&(x[WS(rs, 11)]), ms, &(x[WS(rs, 1)]));
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Tm = BYTW(&(W[TWVL * 20]), Tl);
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Tj = LD(&(x[WS(rs, 7)]), ms, &(x[WS(rs, 1)]));
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Tk = BYTW(&(W[TWVL * 12]), Tj);
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TH = VSUB(Tk, Tm);
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Tn = VADD(Tk, Tm);
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TD = VFNMS(LDK(KP500000000), Tn, Ti);
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}
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{
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V Tg, Ty, Tx, Tz;
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{
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V T7, Tf, To, Tw;
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T7 = VADD(T1, T6);
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Tf = VADD(T9, Te);
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Tg = VSUB(T7, Tf);
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Ty = VADD(T7, Tf);
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To = VADD(Ti, Tn);
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Tw = VADD(Tq, Tv);
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Tx = VSUB(To, Tw);
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Tz = VADD(To, Tw);
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}
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ST(&(x[WS(rs, 3)]), VFNMSI(Tx, Tg), ms, &(x[WS(rs, 1)]));
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ST(&(x[0]), VADD(Ty, Tz), ms, &(x[0]));
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ST(&(x[WS(rs, 9)]), VFMAI(Tx, Tg), ms, &(x[WS(rs, 1)]));
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ST(&(x[WS(rs, 6)]), VSUB(Ty, Tz), ms, &(x[0]));
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}
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{
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V TS, TW, TV, TX;
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{
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V TQ, TR, TT, TU;
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TQ = VSUB(TA, TB);
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TR = VADD(TH, TI);
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TS = VFNMS(LDK(KP866025403), TR, TQ);
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TW = VFMA(LDK(KP866025403), TR, TQ);
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TT = VSUB(TD, TE);
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TU = VSUB(TK, TL);
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TV = VFMA(LDK(KP866025403), TU, TT);
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TX = VFNMS(LDK(KP866025403), TU, TT);
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}
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ST(&(x[WS(rs, 1)]), VFMAI(TV, TS), ms, &(x[WS(rs, 1)]));
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ST(&(x[WS(rs, 7)]), VFNMSI(TX, TW), ms, &(x[WS(rs, 1)]));
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ST(&(x[WS(rs, 11)]), VFNMSI(TV, TS), ms, &(x[WS(rs, 1)]));
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ST(&(x[WS(rs, 5)]), VFMAI(TX, TW), ms, &(x[WS(rs, 1)]));
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}
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{
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V TG, TO, TN, TP;
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{
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V TC, TF, TJ, TM;
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TC = VADD(TA, TB);
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TF = VADD(TD, TE);
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TG = VSUB(TC, TF);
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TO = VADD(TC, TF);
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TJ = VSUB(TH, TI);
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TM = VADD(TK, TL);
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TN = VMUL(LDK(KP866025403), VSUB(TJ, TM));
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TP = VMUL(LDK(KP866025403), VADD(TM, TJ));
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}
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ST(&(x[WS(rs, 10)]), VFNMSI(TN, TG), ms, &(x[0]));
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ST(&(x[WS(rs, 4)]), VFMAI(TP, TO), ms, &(x[0]));
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ST(&(x[WS(rs, 2)]), VFMAI(TN, TG), ms, &(x[0]));
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ST(&(x[WS(rs, 8)]), VFNMSI(TP, TO), ms, &(x[0]));
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}
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}
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}
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VLEAVE();
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}
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static const tw_instr twinstr[] = {
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VTW(0, 1),
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VTW(0, 2),
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VTW(0, 3),
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VTW(0, 4),
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VTW(0, 5),
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VTW(0, 6),
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VTW(0, 7),
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VTW(0, 8),
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VTW(0, 9),
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VTW(0, 10),
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VTW(0, 11),
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{ TW_NEXT, VL, 0 }
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};
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static const ct_desc desc = { 12, XSIMD_STRING("t1bv_12"), twinstr, &GENUS, { 41, 24, 18, 0 }, 0, 0, 0 };
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void XSIMD(codelet_t1bv_12) (planner *p) {
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X(kdft_dit_register) (p, t1bv_12, &desc);
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}
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#else
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/* Generated by: ../../../genfft/gen_twiddle_c.native -simd -compact -variables 4 -pipeline-latency 8 -n 12 -name t1bv_12 -include dft/simd/t1b.h -sign 1 */
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/*
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* This function contains 59 FP additions, 30 FP multiplications,
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* (or, 55 additions, 26 multiplications, 4 fused multiply/add),
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* 28 stack variables, 2 constants, and 24 memory accesses
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*/
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#include "dft/simd/t1b.h"
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static void t1bv_12(R *ri, R *ii, const R *W, stride rs, INT mb, INT me, INT ms)
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{
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DVK(KP866025403, +0.866025403784438646763723170752936183471402627);
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DVK(KP500000000, +0.500000000000000000000000000000000000000000000);
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{
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INT m;
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R *x;
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x = ii;
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for (m = mb, W = W + (mb * ((TWVL / VL) * 22)); m < me; m = m + VL, x = x + (VL * ms), W = W + (TWVL * 22), MAKE_VOLATILE_STRIDE(12, rs)) {
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V T1, Tt, T6, T7, TB, Tq, TC, TD, T9, Tu, Te, Tf, Tx, Tl, Ty;
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V Tz;
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{
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V T5, T3, T4, T2;
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T1 = LD(&(x[0]), ms, &(x[0]));
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T4 = LD(&(x[WS(rs, 8)]), ms, &(x[0]));
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T5 = BYTW(&(W[TWVL * 14]), T4);
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T2 = LD(&(x[WS(rs, 4)]), ms, &(x[0]));
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T3 = BYTW(&(W[TWVL * 6]), T2);
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Tt = VSUB(T3, T5);
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T6 = VADD(T3, T5);
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T7 = VFNMS(LDK(KP500000000), T6, T1);
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}
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{
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V Tn, Tp, Tm, TA, To;
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Tm = LD(&(x[WS(rs, 1)]), ms, &(x[WS(rs, 1)]));
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Tn = BYTW(&(W[0]), Tm);
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TA = LD(&(x[WS(rs, 9)]), ms, &(x[WS(rs, 1)]));
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TB = BYTW(&(W[TWVL * 16]), TA);
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To = LD(&(x[WS(rs, 5)]), ms, &(x[WS(rs, 1)]));
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Tp = BYTW(&(W[TWVL * 8]), To);
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Tq = VSUB(Tn, Tp);
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TC = VADD(Tn, Tp);
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TD = VFNMS(LDK(KP500000000), TC, TB);
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}
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{
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V Td, Tb, T8, Tc, Ta;
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T8 = LD(&(x[WS(rs, 6)]), ms, &(x[0]));
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T9 = BYTW(&(W[TWVL * 10]), T8);
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Tc = LD(&(x[WS(rs, 2)]), ms, &(x[0]));
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Td = BYTW(&(W[TWVL * 2]), Tc);
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Ta = LD(&(x[WS(rs, 10)]), ms, &(x[0]));
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Tb = BYTW(&(W[TWVL * 18]), Ta);
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Tu = VSUB(Tb, Td);
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Te = VADD(Tb, Td);
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Tf = VFNMS(LDK(KP500000000), Te, T9);
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}
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{
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V Ti, Tk, Th, Tw, Tj;
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Th = LD(&(x[WS(rs, 7)]), ms, &(x[WS(rs, 1)]));
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Ti = BYTW(&(W[TWVL * 12]), Th);
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Tw = LD(&(x[WS(rs, 3)]), ms, &(x[WS(rs, 1)]));
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Tx = BYTW(&(W[TWVL * 4]), Tw);
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Tj = LD(&(x[WS(rs, 11)]), ms, &(x[WS(rs, 1)]));
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Tk = BYTW(&(W[TWVL * 20]), Tj);
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Tl = VSUB(Ti, Tk);
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Ty = VADD(Ti, Tk);
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Tz = VFNMS(LDK(KP500000000), Ty, Tx);
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}
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{
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V Ts, TG, TF, TH;
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{
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V Tg, Tr, Tv, TE;
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Tg = VSUB(T7, Tf);
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Tr = VMUL(LDK(KP866025403), VSUB(Tl, Tq));
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Ts = VSUB(Tg, Tr);
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TG = VADD(Tg, Tr);
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Tv = VMUL(LDK(KP866025403), VSUB(Tt, Tu));
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TE = VSUB(Tz, TD);
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TF = VBYI(VADD(Tv, TE));
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TH = VBYI(VSUB(TE, Tv));
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}
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ST(&(x[WS(rs, 11)]), VSUB(Ts, TF), ms, &(x[WS(rs, 1)]));
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ST(&(x[WS(rs, 5)]), VADD(TG, TH), ms, &(x[WS(rs, 1)]));
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ST(&(x[WS(rs, 1)]), VADD(Ts, TF), ms, &(x[WS(rs, 1)]));
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ST(&(x[WS(rs, 7)]), VSUB(TG, TH), ms, &(x[WS(rs, 1)]));
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}
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{
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V TS, TW, TV, TX;
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{
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V TQ, TR, TT, TU;
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TQ = VADD(T1, T6);
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TR = VADD(T9, Te);
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TS = VSUB(TQ, TR);
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TW = VADD(TQ, TR);
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TT = VADD(Tx, Ty);
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TU = VADD(TB, TC);
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TV = VBYI(VSUB(TT, TU));
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TX = VADD(TT, TU);
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}
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ST(&(x[WS(rs, 3)]), VSUB(TS, TV), ms, &(x[WS(rs, 1)]));
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ST(&(x[0]), VADD(TW, TX), ms, &(x[0]));
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ST(&(x[WS(rs, 9)]), VADD(TS, TV), ms, &(x[WS(rs, 1)]));
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ST(&(x[WS(rs, 6)]), VSUB(TW, TX), ms, &(x[0]));
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}
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{
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V TK, TO, TN, TP;
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{
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V TI, TJ, TL, TM;
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TI = VADD(Tl, Tq);
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TJ = VADD(Tt, Tu);
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TK = VBYI(VMUL(LDK(KP866025403), VSUB(TI, TJ)));
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TO = VBYI(VMUL(LDK(KP866025403), VADD(TJ, TI)));
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TL = VADD(T7, Tf);
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TM = VADD(Tz, TD);
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TN = VSUB(TL, TM);
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TP = VADD(TL, TM);
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}
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ST(&(x[WS(rs, 2)]), VADD(TK, TN), ms, &(x[0]));
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ST(&(x[WS(rs, 8)]), VSUB(TP, TO), ms, &(x[0]));
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ST(&(x[WS(rs, 10)]), VSUB(TN, TK), ms, &(x[0]));
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ST(&(x[WS(rs, 4)]), VADD(TO, TP), ms, &(x[0]));
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}
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}
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}
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VLEAVE();
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||
|
|
}
|
||
|
|
|
||
|
|
static const tw_instr twinstr[] = {
|
||
|
|
VTW(0, 1),
|
||
|
|
VTW(0, 2),
|
||
|
|
VTW(0, 3),
|
||
|
|
VTW(0, 4),
|
||
|
|
VTW(0, 5),
|
||
|
|
VTW(0, 6),
|
||
|
|
VTW(0, 7),
|
||
|
|
VTW(0, 8),
|
||
|
|
VTW(0, 9),
|
||
|
|
VTW(0, 10),
|
||
|
|
VTW(0, 11),
|
||
|
|
{ TW_NEXT, VL, 0 }
|
||
|
|
};
|
||
|
|
|
||
|
|
static const ct_desc desc = { 12, XSIMD_STRING("t1bv_12"), twinstr, &GENUS, { 55, 26, 4, 0 }, 0, 0, 0 };
|
||
|
|
|
||
|
|
void XSIMD(codelet_t1bv_12) (planner *p) {
|
||
|
|
X(kdft_dit_register) (p, t1bv_12, &desc);
|
||
|
|
}
|
||
|
|
#endif
|