mirror of
https://github.com/tildearrow/furnace.git
synced 2024-12-01 00:43:02 +00:00
263 lines
9.7 KiB
C
263 lines
9.7 KiB
C
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/*
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* Copyright (c) 2003, 2007-14 Matteo Frigo
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* Copyright (c) 2003, 2007-14 Massachusetts Institute of Technology
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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*
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*/
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/* This file was automatically generated --- DO NOT EDIT */
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/* Generated on Tue Sep 14 10:46:01 EDT 2021 */
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#include "dft/codelet-dft.h"
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#if defined(ARCH_PREFERS_FMA) || defined(ISA_EXTENSION_PREFERS_FMA)
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/* Generated by: ../../../genfft/gen_twidsq_c.native -fma -simd -compact -variables 4 -pipeline-latency 8 -n 4 -dif -name q1bv_4 -include dft/simd/q1b.h -sign 1 */
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/*
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* This function contains 44 FP additions, 32 FP multiplications,
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* (or, 36 additions, 24 multiplications, 8 fused multiply/add),
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* 22 stack variables, 0 constants, and 32 memory accesses
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*/
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#include "dft/simd/q1b.h"
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static void q1bv_4(R *ri, R *ii, const R *W, stride rs, stride vs, INT mb, INT me, INT ms)
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{
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{
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INT m;
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R *x;
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x = ii;
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for (m = mb, W = W + (mb * ((TWVL / VL) * 6)); m < me; m = m + VL, x = x + (VL * ms), W = W + (TWVL * 6), MAKE_VOLATILE_STRIDE(8, rs), MAKE_VOLATILE_STRIDE(8, vs)) {
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V T3, T9, TA, TG, TD, TH, T6, Ta, Te, Tk, Tp, Tv, Ts, Tw, Th;
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V Tl;
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{
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V T1, T2, Ty, Tz;
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T1 = LD(&(x[0]), ms, &(x[0]));
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T2 = LD(&(x[WS(rs, 2)]), ms, &(x[0]));
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T3 = VSUB(T1, T2);
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T9 = VADD(T1, T2);
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Ty = LD(&(x[WS(vs, 3)]), ms, &(x[WS(vs, 3)]));
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Tz = LD(&(x[WS(vs, 3) + WS(rs, 2)]), ms, &(x[WS(vs, 3)]));
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TA = VSUB(Ty, Tz);
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TG = VADD(Ty, Tz);
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}
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{
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V TB, TC, T4, T5;
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TB = LD(&(x[WS(vs, 3) + WS(rs, 1)]), ms, &(x[WS(vs, 3) + WS(rs, 1)]));
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TC = LD(&(x[WS(vs, 3) + WS(rs, 3)]), ms, &(x[WS(vs, 3) + WS(rs, 1)]));
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TD = VSUB(TB, TC);
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TH = VADD(TB, TC);
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T4 = LD(&(x[WS(rs, 1)]), ms, &(x[WS(rs, 1)]));
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T5 = LD(&(x[WS(rs, 3)]), ms, &(x[WS(rs, 1)]));
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T6 = VSUB(T4, T5);
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Ta = VADD(T4, T5);
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}
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{
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V Tc, Td, Tn, To;
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Tc = LD(&(x[WS(vs, 1)]), ms, &(x[WS(vs, 1)]));
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Td = LD(&(x[WS(vs, 1) + WS(rs, 2)]), ms, &(x[WS(vs, 1)]));
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Te = VSUB(Tc, Td);
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Tk = VADD(Tc, Td);
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Tn = LD(&(x[WS(vs, 2)]), ms, &(x[WS(vs, 2)]));
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To = LD(&(x[WS(vs, 2) + WS(rs, 2)]), ms, &(x[WS(vs, 2)]));
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Tp = VSUB(Tn, To);
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Tv = VADD(Tn, To);
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}
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{
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V Tq, Tr, Tf, Tg;
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Tq = LD(&(x[WS(vs, 2) + WS(rs, 1)]), ms, &(x[WS(vs, 2) + WS(rs, 1)]));
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Tr = LD(&(x[WS(vs, 2) + WS(rs, 3)]), ms, &(x[WS(vs, 2) + WS(rs, 1)]));
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Ts = VSUB(Tq, Tr);
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Tw = VADD(Tq, Tr);
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Tf = LD(&(x[WS(vs, 1) + WS(rs, 1)]), ms, &(x[WS(vs, 1) + WS(rs, 1)]));
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Tg = LD(&(x[WS(vs, 1) + WS(rs, 3)]), ms, &(x[WS(vs, 1) + WS(rs, 1)]));
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Th = VSUB(Tf, Tg);
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Tl = VADD(Tf, Tg);
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}
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ST(&(x[0]), VADD(T9, Ta), ms, &(x[0]));
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ST(&(x[WS(rs, 1)]), VADD(Tk, Tl), ms, &(x[WS(rs, 1)]));
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ST(&(x[WS(rs, 2)]), VADD(Tv, Tw), ms, &(x[0]));
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ST(&(x[WS(rs, 3)]), VADD(TG, TH), ms, &(x[WS(rs, 1)]));
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{
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V T7, Ti, Tt, TE;
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T7 = BYTW(&(W[TWVL * 4]), VFNMSI(T6, T3));
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ST(&(x[WS(vs, 3)]), T7, ms, &(x[WS(vs, 3)]));
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Ti = BYTW(&(W[TWVL * 4]), VFNMSI(Th, Te));
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ST(&(x[WS(vs, 3) + WS(rs, 1)]), Ti, ms, &(x[WS(vs, 3) + WS(rs, 1)]));
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Tt = BYTW(&(W[TWVL * 4]), VFNMSI(Ts, Tp));
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ST(&(x[WS(vs, 3) + WS(rs, 2)]), Tt, ms, &(x[WS(vs, 3)]));
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TE = BYTW(&(W[TWVL * 4]), VFNMSI(TD, TA));
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ST(&(x[WS(vs, 3) + WS(rs, 3)]), TE, ms, &(x[WS(vs, 3) + WS(rs, 1)]));
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}
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{
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V T8, Tj, Tu, TF;
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T8 = BYTW(&(W[0]), VFMAI(T6, T3));
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ST(&(x[WS(vs, 1)]), T8, ms, &(x[WS(vs, 1)]));
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Tj = BYTW(&(W[0]), VFMAI(Th, Te));
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ST(&(x[WS(vs, 1) + WS(rs, 1)]), Tj, ms, &(x[WS(vs, 1) + WS(rs, 1)]));
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Tu = BYTW(&(W[0]), VFMAI(Ts, Tp));
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ST(&(x[WS(vs, 1) + WS(rs, 2)]), Tu, ms, &(x[WS(vs, 1)]));
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TF = BYTW(&(W[0]), VFMAI(TD, TA));
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ST(&(x[WS(vs, 1) + WS(rs, 3)]), TF, ms, &(x[WS(vs, 1) + WS(rs, 1)]));
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}
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{
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V Tb, Tm, Tx, TI;
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Tb = BYTW(&(W[TWVL * 2]), VSUB(T9, Ta));
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ST(&(x[WS(vs, 2)]), Tb, ms, &(x[WS(vs, 2)]));
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Tm = BYTW(&(W[TWVL * 2]), VSUB(Tk, Tl));
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ST(&(x[WS(vs, 2) + WS(rs, 1)]), Tm, ms, &(x[WS(vs, 2) + WS(rs, 1)]));
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Tx = BYTW(&(W[TWVL * 2]), VSUB(Tv, Tw));
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ST(&(x[WS(vs, 2) + WS(rs, 2)]), Tx, ms, &(x[WS(vs, 2)]));
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TI = BYTW(&(W[TWVL * 2]), VSUB(TG, TH));
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ST(&(x[WS(vs, 2) + WS(rs, 3)]), TI, ms, &(x[WS(vs, 2) + WS(rs, 1)]));
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}
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}
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}
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VLEAVE();
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}
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static const tw_instr twinstr[] = {
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VTW(0, 1),
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VTW(0, 2),
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VTW(0, 3),
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{ TW_NEXT, VL, 0 }
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};
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static const ct_desc desc = { 4, XSIMD_STRING("q1bv_4"), twinstr, &GENUS, { 36, 24, 8, 0 }, 0, 0, 0 };
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void XSIMD(codelet_q1bv_4) (planner *p) {
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X(kdft_difsq_register) (p, q1bv_4, &desc);
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}
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#else
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/* Generated by: ../../../genfft/gen_twidsq_c.native -simd -compact -variables 4 -pipeline-latency 8 -n 4 -dif -name q1bv_4 -include dft/simd/q1b.h -sign 1 */
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/*
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* This function contains 44 FP additions, 24 FP multiplications,
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* (or, 44 additions, 24 multiplications, 0 fused multiply/add),
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* 22 stack variables, 0 constants, and 32 memory accesses
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*/
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#include "dft/simd/q1b.h"
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static void q1bv_4(R *ri, R *ii, const R *W, stride rs, stride vs, INT mb, INT me, INT ms)
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{
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{
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INT m;
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R *x;
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x = ii;
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for (m = mb, W = W + (mb * ((TWVL / VL) * 6)); m < me; m = m + VL, x = x + (VL * ms), W = W + (TWVL * 6), MAKE_VOLATILE_STRIDE(8, rs), MAKE_VOLATILE_STRIDE(8, vs)) {
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V T3, T9, TA, TG, TD, TH, T6, Ta, Te, Tk, Tp, Tv, Ts, Tw, Th;
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V Tl;
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{
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V T1, T2, Ty, Tz;
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T1 = LD(&(x[0]), ms, &(x[0]));
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T2 = LD(&(x[WS(rs, 2)]), ms, &(x[0]));
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T3 = VSUB(T1, T2);
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T9 = VADD(T1, T2);
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Ty = LD(&(x[WS(vs, 3)]), ms, &(x[WS(vs, 3)]));
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Tz = LD(&(x[WS(vs, 3) + WS(rs, 2)]), ms, &(x[WS(vs, 3)]));
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TA = VSUB(Ty, Tz);
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TG = VADD(Ty, Tz);
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}
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{
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V TB, TC, T4, T5;
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TB = LD(&(x[WS(vs, 3) + WS(rs, 1)]), ms, &(x[WS(vs, 3) + WS(rs, 1)]));
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TC = LD(&(x[WS(vs, 3) + WS(rs, 3)]), ms, &(x[WS(vs, 3) + WS(rs, 1)]));
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TD = VBYI(VSUB(TB, TC));
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TH = VADD(TB, TC);
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T4 = LD(&(x[WS(rs, 1)]), ms, &(x[WS(rs, 1)]));
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T5 = LD(&(x[WS(rs, 3)]), ms, &(x[WS(rs, 1)]));
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T6 = VBYI(VSUB(T4, T5));
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Ta = VADD(T4, T5);
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}
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{
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V Tc, Td, Tn, To;
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Tc = LD(&(x[WS(vs, 1)]), ms, &(x[WS(vs, 1)]));
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Td = LD(&(x[WS(vs, 1) + WS(rs, 2)]), ms, &(x[WS(vs, 1)]));
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Te = VSUB(Tc, Td);
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Tk = VADD(Tc, Td);
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Tn = LD(&(x[WS(vs, 2)]), ms, &(x[WS(vs, 2)]));
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To = LD(&(x[WS(vs, 2) + WS(rs, 2)]), ms, &(x[WS(vs, 2)]));
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Tp = VSUB(Tn, To);
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Tv = VADD(Tn, To);
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}
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{
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V Tq, Tr, Tf, Tg;
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Tq = LD(&(x[WS(vs, 2) + WS(rs, 1)]), ms, &(x[WS(vs, 2) + WS(rs, 1)]));
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Tr = LD(&(x[WS(vs, 2) + WS(rs, 3)]), ms, &(x[WS(vs, 2) + WS(rs, 1)]));
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Ts = VBYI(VSUB(Tq, Tr));
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Tw = VADD(Tq, Tr);
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Tf = LD(&(x[WS(vs, 1) + WS(rs, 1)]), ms, &(x[WS(vs, 1) + WS(rs, 1)]));
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Tg = LD(&(x[WS(vs, 1) + WS(rs, 3)]), ms, &(x[WS(vs, 1) + WS(rs, 1)]));
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Th = VBYI(VSUB(Tf, Tg));
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Tl = VADD(Tf, Tg);
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}
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ST(&(x[0]), VADD(T9, Ta), ms, &(x[0]));
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ST(&(x[WS(rs, 1)]), VADD(Tk, Tl), ms, &(x[WS(rs, 1)]));
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ST(&(x[WS(rs, 2)]), VADD(Tv, Tw), ms, &(x[0]));
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ST(&(x[WS(rs, 3)]), VADD(TG, TH), ms, &(x[WS(rs, 1)]));
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{
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V T7, Ti, Tt, TE;
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T7 = BYTW(&(W[TWVL * 4]), VSUB(T3, T6));
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ST(&(x[WS(vs, 3)]), T7, ms, &(x[WS(vs, 3)]));
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Ti = BYTW(&(W[TWVL * 4]), VSUB(Te, Th));
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ST(&(x[WS(vs, 3) + WS(rs, 1)]), Ti, ms, &(x[WS(vs, 3) + WS(rs, 1)]));
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Tt = BYTW(&(W[TWVL * 4]), VSUB(Tp, Ts));
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ST(&(x[WS(vs, 3) + WS(rs, 2)]), Tt, ms, &(x[WS(vs, 3)]));
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TE = BYTW(&(W[TWVL * 4]), VSUB(TA, TD));
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ST(&(x[WS(vs, 3) + WS(rs, 3)]), TE, ms, &(x[WS(vs, 3) + WS(rs, 1)]));
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}
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{
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V T8, Tj, Tu, TF;
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T8 = BYTW(&(W[0]), VADD(T3, T6));
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ST(&(x[WS(vs, 1)]), T8, ms, &(x[WS(vs, 1)]));
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Tj = BYTW(&(W[0]), VADD(Te, Th));
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ST(&(x[WS(vs, 1) + WS(rs, 1)]), Tj, ms, &(x[WS(vs, 1) + WS(rs, 1)]));
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Tu = BYTW(&(W[0]), VADD(Tp, Ts));
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ST(&(x[WS(vs, 1) + WS(rs, 2)]), Tu, ms, &(x[WS(vs, 1)]));
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TF = BYTW(&(W[0]), VADD(TA, TD));
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ST(&(x[WS(vs, 1) + WS(rs, 3)]), TF, ms, &(x[WS(vs, 1) + WS(rs, 1)]));
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}
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{
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V Tb, Tm, Tx, TI;
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Tb = BYTW(&(W[TWVL * 2]), VSUB(T9, Ta));
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ST(&(x[WS(vs, 2)]), Tb, ms, &(x[WS(vs, 2)]));
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Tm = BYTW(&(W[TWVL * 2]), VSUB(Tk, Tl));
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ST(&(x[WS(vs, 2) + WS(rs, 1)]), Tm, ms, &(x[WS(vs, 2) + WS(rs, 1)]));
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Tx = BYTW(&(W[TWVL * 2]), VSUB(Tv, Tw));
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ST(&(x[WS(vs, 2) + WS(rs, 2)]), Tx, ms, &(x[WS(vs, 2)]));
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TI = BYTW(&(W[TWVL * 2]), VSUB(TG, TH));
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ST(&(x[WS(vs, 2) + WS(rs, 3)]), TI, ms, &(x[WS(vs, 2) + WS(rs, 1)]));
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}
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}
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}
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VLEAVE();
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}
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static const tw_instr twinstr[] = {
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VTW(0, 1),
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VTW(0, 2),
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VTW(0, 3),
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{ TW_NEXT, VL, 0 }
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};
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static const ct_desc desc = { 4, XSIMD_STRING("q1bv_4"), twinstr, &GENUS, { 44, 24, 0, 0 }, 0, 0, 0 };
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void XSIMD(codelet_q1bv_4) (planner *p) {
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X(kdft_difsq_register) (p, q1bv_4, &desc);
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}
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#endif
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