forked from etc/pineapple-src
early-access version 2596
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parent
d7301c48b1
commit
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8 changed files with 5 additions and 113 deletions
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@ -1,7 +1,7 @@
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yuzu emulator early access
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=============
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This is the source code for early-access 2595.
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This is the source code for early-access 2596.
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## Legal Notice
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@ -322,7 +322,7 @@ struct Memory::Impl {
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}
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if (Settings::IsFastmemEnabled()) {
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const bool is_read_enable = !Settings::IsGPULevelExtreme() || !cached;
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const bool is_read_enable = Settings::IsGPULevelHigh() || !cached;
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system.DeviceMemory().buffer.Protect(vaddr, size, is_read_enable, !cached);
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}
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@ -327,7 +327,7 @@ void Inst::AddPhiOperand(Block* predecessor, const Value& value) {
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}
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void Inst::ErasePhiOperand(size_t index) {
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const auto operand_it{phi_args.begin() + static_cast<u32>(index)};
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const auto operand_it{phi_args.begin() + static_cast<ptrdiff_t>(index)};
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phi_args.erase(operand_it);
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}
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@ -212,7 +212,7 @@ public:
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void FlushCachedWrites() noexcept {
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flags &= ~BufferFlagBits::CachedWrites;
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const u64 num_words = NumWords();
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const u64* const cached_words = Array<Type::CachedCPU>();
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u64* const cached_words = Array<Type::CachedCPU>();
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u64* const untracked_words = Array<Type::Untracked>();
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u64* const cpu_words = Array<Type::CPU>();
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for (u64 word_index = 0; word_index < num_words; ++word_index) {
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@ -220,6 +220,7 @@ public:
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NotifyRasterizer<false>(word_index, untracked_words[word_index], cached_bits);
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untracked_words[word_index] |= cached_bits;
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cpu_words[word_index] |= cached_bits;
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cached_words[word_index] = 0;
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}
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}
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@ -2,13 +2,9 @@
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#include <algorithm>
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#include <cstring>
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#include <optional>
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#include "common/alignment.h"
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#include "common/assert.h"
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#include "common/settings.h"
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#include "core/core.h"
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#include "core/core_timing.h"
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#include "video_core/dirty_flags.h"
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@ -30,7 +26,6 @@ Maxwell3D::Maxwell3D(Core::System& system_, MemoryManager& memory_manager_)
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upload_state{memory_manager, regs.upload} {
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dirty.flags.flip();
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InitializeRegisterDefaults();
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accelerated_reads = Settings::IsFastmemEnabled();
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}
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Maxwell3D::~Maxwell3D() = default;
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@ -218,9 +213,6 @@ void Maxwell3D::ProcessMethodCall(u32 method, u32 argument, u32 nonshadow_argume
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regs.index_array.count = regs.small_index.count;
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regs.index_array.first = regs.small_index.first;
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dirty.flags[VideoCommon::Dirty::IndexBuffer] = true;
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if (!Settings::IsGPULevelExtreme()) {
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RecalculateVertexArrayLimit();
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}
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return DrawArrays();
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case MAXWELL3D_REG_INDEX(topology_override):
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use_topology_override = true;
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rasterizer->Clear();
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}
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void Maxwell3D::RecalculateVertexArrayLimit() {
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GPUVAddr start_address = regs.index_array.StartAddress();
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auto& vn_state = vertex_num_approx_state;
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if (start_address != vn_state.last_index_array_start ||
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vn_state.current_min_index != regs.index_array.first) {
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vn_state.last_index_array_start = start_address;
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vn_state.current_max_index = regs.index_array.first;
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vn_state.current_min_index = regs.index_array.first;
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vn_state.current_num_vertices = 0;
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}
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const u32 index_count = regs.index_array.first + regs.index_array.count;
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if (index_count <= vn_state.current_max_index) {
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return;
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}
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const u32 max_base = std::max(regs.index_array.first, vn_state.current_max_index);
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const u32 num_indices = index_count - max_base;
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const size_t size_index = regs.index_array.FormatSizeInBytes();
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const size_t expected_size = num_indices * size_index;
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const size_t offset = max_base * size_index;
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auto maybe_ptr = memory_manager.GpuToHostPointer(start_address + offset);
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u8* ptr;
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if (accelerated_reads && maybe_ptr) {
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ptr = *maybe_ptr;
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} else {
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vn_state.index_buffer_cache.resize(Common::DivideUp(expected_size, sizeof(u32)));
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ptr = reinterpret_cast<u8*>(vn_state.index_buffer_cache.data());
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memory_manager.ReadBlockUnsafe(start_address + offset, ptr, expected_size);
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}
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vn_state.current_max_index = index_count;
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u32 new_num_vertices{};
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switch (regs.index_array.format) {
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case Regs::IndexFormat::UnsignedByte: {
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std::span<const u8> span{ptr, num_indices};
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const auto max = std::max_element(span.begin(), span.end());
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new_num_vertices = *max + 1;
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break;
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}
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case Regs::IndexFormat::UnsignedShort: {
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std::span<const u16> span{reinterpret_cast<const u16*>(ptr), num_indices};
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const auto max = std::max_element(span.begin(), span.end());
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new_num_vertices = *max + 1;
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break;
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}
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case Regs::IndexFormat::UnsignedInt: {
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std::span<const u32> span{reinterpret_cast<const u32*>(ptr), num_indices};
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const auto max = std::max_element(span.begin(), span.end());
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new_num_vertices = *max + 1;
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break;
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}
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}
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if (new_num_vertices > vn_state.current_num_vertices) {
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vn_state.current_num_vertices = new_num_vertices;
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for (size_t i = 0; i < Regs::NumVertexArrays; i++) {
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if (!regs.vertex_array[i].enable) {
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continue;
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}
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const u32 stride = regs.vertex_array[i].stride;
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const GPUVAddr gpu_addr_begin = regs.vertex_array[i].StartAddress();
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const GPUVAddr gpu_addr_end = gpu_addr_begin + new_num_vertices * stride - 1;
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regs.vertex_array_limit[i].SetAddress(gpu_addr_end);
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dirty.flags[VideoCommon::Dirty::VertexBuffer0 + i] = true;
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}
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}
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}
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} // namespace Tegra::Engines
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return static_cast<GPUVAddr>((static_cast<GPUVAddr>(limit_high) << 32) |
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limit_low);
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}
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void SetAddress(GPUVAddr address) {
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limit_low = static_cast<u32>(address);
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limit_high = static_cast<u32>(address >> 32);
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}
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} vertex_array_limit[NumVertexArrays];
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struct {
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Tables tables{};
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} dirty;
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struct VertexNumApproxState {
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GPUVAddr last_index_array_start;
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u32 current_max_index;
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u32 current_min_index;
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u32 current_num_vertices;
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std::vector<u32> index_buffer_cache;
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} vertex_num_approx_state;
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bool accelerated_reads{};
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private:
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void InitializeRegisterDefaults();
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// Handles a instance drawcall from MME
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void StepInstance(MMEDrawMode expected_mode, u32 count);
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void RecalculateVertexArrayLimit();
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/// Returns a query's value or an empty object if the value will be deferred through a cache.
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std::optional<u64> GetQueryResult();
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#include "common/alignment.h"
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#include "common/assert.h"
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#include "common/host_memory.h"
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#include "common/logging/log.h"
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#include "core/core.h"
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#include "core/hle/kernel/k_page_table.h"
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return page_entry.ToAddress() + (gpu_addr & page_mask);
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}
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std::optional<u8*> MemoryManager::GpuToHostPointer(GPUVAddr gpu_addr) const {
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auto cpu_addr = GpuToCpuAddress(gpu_addr);
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if (!cpu_addr) {
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return std::nullopt;
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}
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auto& device_memory = system.DeviceMemory();
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auto base = device_memory.buffer.VirtualBasePointer();
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if (!base) {
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return std::nullopt;
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}
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return base + *cpu_addr;
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}
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std::optional<VAddr> MemoryManager::GpuToCpuAddress(GPUVAddr addr, std::size_t size) const {
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size_t page_index{addr >> page_bits};
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const size_t page_last{(addr + size + page_size - 1) >> page_bits};
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[[nodiscard]] std::optional<VAddr> GpuToCpuAddress(GPUVAddr addr) const;
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[[nodiscard]] std::optional<u8*> GpuToHostPointer(GPUVAddr addr) const;
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[[nodiscard]] std::optional<VAddr> GpuToCpuAddress(GPUVAddr addr, std::size_t size) const;
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template <typename T>
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