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early-access version 2176

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pineappleEA 2021-11-02 02:07:09 +01:00
parent b129443b21
commit 2b3decfff3
4 changed files with 5 additions and 27 deletions
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2
README.md
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@ -1,7 +1,7 @@
yuzu emulator early access yuzu emulator early access
============= =============
This is the source code for early-access 2175. This is the source code for early-access 2176.
## Legal Notice ## Legal Notice

20
src/core/hle/service/nvdrv/devices/nvhost_ctrl.cpp
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@ -2,10 +2,6 @@
// Licensed under GPLv2 or any later version // Licensed under GPLv2 or any later version
// Refer to the license.txt file included. // Refer to the license.txt file included.
// SPDX-License-Identifier: MPL-2.0
// Copyright 2021 Skyline Team and Contributors (https://github.com/skyline-emu/)
// Copyright 2019-2020 Ryujinx Team and Contributors
#include <cstdlib> #include <cstdlib>
#include <cstring> #include <cstring>
@ -42,8 +38,6 @@ NvResult nvhost_ctrl::Ioctl1(DeviceFD fd, Ioctl command, const std::vector<u8>&
return IocCtrlEventRegister(input, output); return IocCtrlEventRegister(input, output);
case 0x20: case 0x20:
return IocCtrlEventUnregister(input, output); return IocCtrlEventUnregister(input, output);
case 0x21:
return IocCtrlFreeEventBatch(input, output);
} }
break; break;
default: default:
@ -227,18 +221,4 @@ NvResult nvhost_ctrl::IocCtrlClearEventWait(const std::vector<u8>& input, std::v
return NvResult::Success; return NvResult::Success;
} }
NvResult nvhost_ctrl::IocCtrlFreeEventBatch(const std::vector<u8>& input, std::vector<u8>& output) {
IocCtrlFreeEventBatchParams params{};
std::memcpy(&params, input.data(), sizeof(params));
LOG_DEBUG(Service_NVDRV, "called, bit_mask={}", params.bit_mask);
for (u32 event_id = 0; event_id < MaxNvEvents; ++event_id) {
if (params.bit_mask & (1ULL << event_id)) {
events_interface.UnregisterEvent(event_id);
}
}
return NvResult::Success;
}
} // namespace Service::Nvidia::Devices } // namespace Service::Nvidia::Devices

8
src/core/hle/service/nvdrv/devices/nvhost_ctrl.h
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@ -119,18 +119,16 @@ private:
static_assert(sizeof(IocCtrlEventUnregisterParams) == 4, static_assert(sizeof(IocCtrlEventUnregisterParams) == 4,
"IocCtrlEventUnregisterParams is incorrect size"); "IocCtrlEventUnregisterParams is incorrect size");
struct IocCtrlFreeEventBatchParams { struct IocCtrlEventKill {
u64_le bit_mask{}; u64_le user_events{};
}; };
static_assert(sizeof(IocCtrlFreeEventBatchParams) == 8, static_assert(sizeof(IocCtrlEventKill) == 8, "IocCtrlEventKill is incorrect size");
"IocCtrlFreeEventBatchParams is incorrect size");
NvResult NvOsGetConfigU32(const std::vector<u8>& input, std::vector<u8>& output); NvResult NvOsGetConfigU32(const std::vector<u8>& input, std::vector<u8>& output);
NvResult IocCtrlEventWait(const std::vector<u8>& input, std::vector<u8>& output, bool is_async); NvResult IocCtrlEventWait(const std::vector<u8>& input, std::vector<u8>& output, bool is_async);
NvResult IocCtrlEventRegister(const std::vector<u8>& input, std::vector<u8>& output); NvResult IocCtrlEventRegister(const std::vector<u8>& input, std::vector<u8>& output);
NvResult IocCtrlEventUnregister(const std::vector<u8>& input, std::vector<u8>& output); NvResult IocCtrlEventUnregister(const std::vector<u8>& input, std::vector<u8>& output);
NvResult IocCtrlClearEventWait(const std::vector<u8>& input, std::vector<u8>& output); NvResult IocCtrlClearEventWait(const std::vector<u8>& input, std::vector<u8>& output);
NvResult IocCtrlFreeEventBatch(const std::vector<u8>& input, std::vector<u8>& output);
EventInterface& events_interface; EventInterface& events_interface;
SyncpointManager& syncpoint_manager; SyncpointManager& syncpoint_manager;

2
src/shader_recompiler/backend/glasm/emit_glasm_not_implemented.cpp
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@ -18,7 +18,7 @@ namespace Shader::Backend::GLASM {
#define NotImplemented() throw NotImplementedException("GLASM instruction {}", __LINE__) #define NotImplemented() throw NotImplementedException("GLASM instruction {}", __LINE__)
static void DefinePhi(EmitContext& ctx, IR::Inst& phi) { static void DefinePhi(EmitContext& ctx, IR::Inst& phi) {
switch (phi.Arg(0).Type()) { switch (phi.Type()) {
case IR::Type::U1: case IR::Type::U1:
case IR::Type::U32: case IR::Type::U32:
case IR::Type::F32: case IR::Type::F32: