256 lines
8.1 KiB
C++
256 lines
8.1 KiB
C++
// Copyright 2018 yuzu Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#pragma once
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#include <array>
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#include <unordered_map>
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#include <vector>
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#include "common/bit_field.h"
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#include "common/common_funcs.h"
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#include "common/common_types.h"
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#include "video_core/memory_manager.h"
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namespace Tegra {
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namespace Engines {
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class Maxwell3D final {
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public:
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explicit Maxwell3D(MemoryManager& memory_manager);
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~Maxwell3D() = default;
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/// Write the value to the register identified by method.
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void WriteReg(u32 method, u32 value, u32 remaining_params);
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/// Uploads the code for a GPU macro program associated with the specified entry.
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void SubmitMacroCode(u32 entry, std::vector<u32> code);
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/// Register structure of the Maxwell3D engine.
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/// TODO(Subv): This structure will need to be made bigger as more registers are discovered.
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struct Regs {
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static constexpr size_t NUM_REGS = 0xE36;
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static constexpr size_t NumCBData = 16;
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static constexpr size_t NumVertexArrays = 32;
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static constexpr size_t MaxShaderProgram = 6;
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static constexpr size_t MaxShaderStage = 5;
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// Maximum number of const buffers per shader stage.
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static constexpr size_t MaxConstBuffers = 16;
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enum class QueryMode : u32 {
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Write = 0,
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Sync = 1,
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};
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enum class ShaderProgram : u32 {
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VertexA = 0,
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VertexB = 1,
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TesselationControl = 2,
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TesselationEval = 3,
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Geometry = 4,
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Fragment = 5,
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};
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enum class ShaderStage : u32 {
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Vertex = 0,
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TesselationControl = 1,
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TesselationEval = 2,
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Geometry = 3,
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Fragment = 4,
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};
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union {
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struct {
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INSERT_PADDING_WORDS(0x582);
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struct {
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u32 code_address_high;
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u32 code_address_low;
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GPUVAddr CodeAddress() const {
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return static_cast<GPUVAddr>(
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(static_cast<GPUVAddr>(code_address_high) << 32) | code_address_low);
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}
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} code_address;
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INSERT_PADDING_WORDS(1);
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struct {
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u32 vertex_end_gl;
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u32 vertex_begin_gl;
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} draw;
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INSERT_PADDING_WORDS(0x139);
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struct {
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u32 query_address_high;
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u32 query_address_low;
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u32 query_sequence;
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union {
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u32 raw;
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BitField<0, 2, QueryMode> mode;
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BitField<4, 1, u32> fence;
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BitField<12, 4, u32> unit;
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} query_get;
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GPUVAddr QueryAddress() const {
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return static_cast<GPUVAddr>(
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(static_cast<GPUVAddr>(query_address_high) << 32) | query_address_low);
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}
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} query;
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INSERT_PADDING_WORDS(0x3C);
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struct {
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union {
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BitField<0, 12, u32> stride;
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BitField<12, 1, u32> enable;
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};
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u32 start_high;
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u32 start_low;
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u32 divisor;
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GPUVAddr StartAddress() const {
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return static_cast<GPUVAddr>((static_cast<GPUVAddr>(start_high) << 32) |
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start_low);
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}
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} vertex_array[NumVertexArrays];
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INSERT_PADDING_WORDS(0x40);
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struct {
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u32 limit_high;
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u32 limit_low;
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GPUVAddr LimitAddress() const {
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return static_cast<GPUVAddr>((static_cast<GPUVAddr>(limit_high) << 32) |
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limit_low);
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}
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} vertex_array_limit[NumVertexArrays];
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struct {
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union {
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BitField<0, 1, u32> enable;
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BitField<4, 4, ShaderProgram> program;
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};
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u32 start_id;
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INSERT_PADDING_WORDS(1);
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u32 gpr_alloc;
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ShaderStage type;
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INSERT_PADDING_WORDS(9);
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} shader_config[MaxShaderProgram];
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INSERT_PADDING_WORDS(0x8C);
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struct {
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u32 cb_size;
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u32 cb_address_high;
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u32 cb_address_low;
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u32 cb_pos;
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u32 cb_data[NumCBData];
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GPUVAddr BufferAddress() const {
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return static_cast<GPUVAddr>(
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(static_cast<GPUVAddr>(cb_address_high) << 32) | cb_address_low);
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}
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} const_buffer;
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INSERT_PADDING_WORDS(0x10);
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struct {
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union {
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u32 raw_config;
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BitField<0, 1, u32> valid;
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BitField<4, 5, u32> index;
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};
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INSERT_PADDING_WORDS(7);
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} cb_bind[MaxShaderStage];
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INSERT_PADDING_WORDS(0x56);
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u32 tex_cb_index;
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INSERT_PADDING_WORDS(0x4B3);
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};
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std::array<u32, NUM_REGS> reg_array;
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};
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} regs{};
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static_assert(sizeof(Regs) == Regs::NUM_REGS * sizeof(u32), "Maxwell3D Regs has wrong size");
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struct State {
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struct ConstBufferInfo {
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GPUVAddr address;
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u32 index;
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u32 size;
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bool enabled;
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};
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struct ShaderProgramInfo {
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Regs::ShaderStage stage;
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Regs::ShaderProgram program;
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GPUVAddr address;
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};
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struct ShaderStageInfo {
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std::array<ConstBufferInfo, Regs::MaxConstBuffers> const_buffers;
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};
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std::array<ShaderStageInfo, Regs::MaxShaderStage> shader_stages;
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std::array<ShaderProgramInfo, Regs::MaxShaderProgram> shader_programs;
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};
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State state{};
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private:
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MemoryManager& memory_manager;
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std::unordered_map<u32, std::vector<u32>> uploaded_macros;
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/// Macro method that is currently being executed / being fed parameters.
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u32 executing_macro = 0;
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/// Parameters that have been submitted to the macro call so far.
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std::vector<u32> macro_params;
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/**
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* Call a macro on this engine.
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* @param method Method to call
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* @param parameters Arguments to the method call
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*/
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void CallMacroMethod(u32 method, const std::vector<u32>& parameters);
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/// Handles a write to the QUERY_GET register.
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void ProcessQueryGet();
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/// Handles a write to the CB_BIND register.
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void ProcessCBBind(Regs::ShaderStage stage);
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/// Handles a write to the VERTEX_END_GL register, triggering a draw.
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void DrawArrays();
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/// Method call handlers
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void SetShader(const std::vector<u32>& parameters);
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struct MethodInfo {
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const char* name;
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u32 arguments;
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void (Maxwell3D::*handler)(const std::vector<u32>& parameters);
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};
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static const std::unordered_map<u32, MethodInfo> method_handlers;
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};
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#define ASSERT_REG_POSITION(field_name, position) \
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static_assert(offsetof(Maxwell3D::Regs, field_name) == position * 4, \
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"Field " #field_name " has invalid position")
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ASSERT_REG_POSITION(code_address, 0x582);
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ASSERT_REG_POSITION(draw, 0x585);
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ASSERT_REG_POSITION(query, 0x6C0);
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ASSERT_REG_POSITION(vertex_array[0], 0x700);
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ASSERT_REG_POSITION(vertex_array_limit[0], 0x7C0);
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ASSERT_REG_POSITION(shader_config[0], 0x800);
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ASSERT_REG_POSITION(const_buffer, 0x8E0);
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ASSERT_REG_POSITION(cb_bind[0], 0x904);
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ASSERT_REG_POSITION(tex_cb_index, 0x982);
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#undef ASSERT_REG_POSITION
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} // namespace Engines
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} // namespace Tegra
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