264 lines
7.2 KiB
C++
264 lines
7.2 KiB
C++
// SPDX-FileCopyrightText: Copyright 2022 yuzu Emulator Project
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// SPDX-License-Identifier: GPL-2.0-or-later
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#pragma once
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#include "common/common_types.h"
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namespace Tegra {
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// https://github.com/NVIDIA/open-gpu-doc/blob/master/manuals/volta/gv100/dev_mmu.ref.txt
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enum class PTEKind : u8 {
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INVALID = 0xff,
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PITCH = 0x00,
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Z16 = 0x01,
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Z16_2C = 0x02,
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Z16_MS2_2C = 0x03,
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Z16_MS4_2C = 0x04,
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Z16_MS8_2C = 0x05,
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Z16_MS16_2C = 0x06,
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Z16_2Z = 0x07,
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Z16_MS2_2Z = 0x08,
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Z16_MS4_2Z = 0x09,
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Z16_MS8_2Z = 0x0a,
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Z16_MS16_2Z = 0x0b,
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Z16_2CZ = 0x36,
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Z16_MS2_2CZ = 0x37,
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Z16_MS4_2CZ = 0x38,
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Z16_MS8_2CZ = 0x39,
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Z16_MS16_2CZ = 0x5f,
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Z16_4CZ = 0x0c,
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Z16_MS2_4CZ = 0x0d,
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Z16_MS4_4CZ = 0x0e,
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Z16_MS8_4CZ = 0x0f,
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Z16_MS16_4CZ = 0x10,
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S8Z24 = 0x11,
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S8Z24_1Z = 0x12,
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S8Z24_MS2_1Z = 0x13,
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S8Z24_MS4_1Z = 0x14,
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S8Z24_MS8_1Z = 0x15,
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S8Z24_MS16_1Z = 0x16,
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S8Z24_2CZ = 0x17,
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S8Z24_MS2_2CZ = 0x18,
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S8Z24_MS4_2CZ = 0x19,
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S8Z24_MS8_2CZ = 0x1a,
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S8Z24_MS16_2CZ = 0x1b,
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S8Z24_2CS = 0x1c,
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S8Z24_MS2_2CS = 0x1d,
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S8Z24_MS4_2CS = 0x1e,
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S8Z24_MS8_2CS = 0x1f,
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S8Z24_MS16_2CS = 0x20,
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S8Z24_4CSZV = 0x21,
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S8Z24_MS2_4CSZV = 0x22,
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S8Z24_MS4_4CSZV = 0x23,
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S8Z24_MS8_4CSZV = 0x24,
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S8Z24_MS16_4CSZV = 0x25,
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V8Z24_MS4_VC12 = 0x26,
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V8Z24_MS4_VC4 = 0x27,
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V8Z24_MS8_VC8 = 0x28,
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V8Z24_MS8_VC24 = 0x29,
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V8Z24_MS4_VC12_1ZV = 0x2e,
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V8Z24_MS4_VC4_1ZV = 0x2f,
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V8Z24_MS8_VC8_1ZV = 0x30,
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V8Z24_MS8_VC24_1ZV = 0x31,
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V8Z24_MS4_VC12_2CS = 0x32,
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V8Z24_MS4_VC4_2CS = 0x33,
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V8Z24_MS8_VC8_2CS = 0x34,
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V8Z24_MS8_VC24_2CS = 0x35,
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V8Z24_MS4_VC12_2CZV = 0x3a,
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V8Z24_MS4_VC4_2CZV = 0x3b,
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V8Z24_MS8_VC8_2CZV = 0x3c,
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V8Z24_MS8_VC24_2CZV = 0x3d,
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V8Z24_MS4_VC12_2ZV = 0x3e,
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V8Z24_MS4_VC4_2ZV = 0x3f,
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V8Z24_MS8_VC8_2ZV = 0x40,
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V8Z24_MS8_VC24_2ZV = 0x41,
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V8Z24_MS4_VC12_4CSZV = 0x42,
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V8Z24_MS4_VC4_4CSZV = 0x43,
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V8Z24_MS8_VC8_4CSZV = 0x44,
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V8Z24_MS8_VC24_4CSZV = 0x45,
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Z24S8 = 0x46,
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Z24S8_1Z = 0x47,
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Z24S8_MS2_1Z = 0x48,
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Z24S8_MS4_1Z = 0x49,
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Z24S8_MS8_1Z = 0x4a,
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Z24S8_MS16_1Z = 0x4b,
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Z24S8_2CS = 0x4c,
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Z24S8_MS2_2CS = 0x4d,
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Z24S8_MS4_2CS = 0x4e,
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Z24S8_MS8_2CS = 0x4f,
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Z24S8_MS16_2CS = 0x50,
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Z24S8_2CZ = 0x51,
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Z24S8_MS2_2CZ = 0x52,
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Z24S8_MS4_2CZ = 0x53,
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Z24S8_MS8_2CZ = 0x54,
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Z24S8_MS16_2CZ = 0x55,
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Z24S8_4CSZV = 0x56,
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Z24S8_MS2_4CSZV = 0x57,
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Z24S8_MS4_4CSZV = 0x58,
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Z24S8_MS8_4CSZV = 0x59,
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Z24S8_MS16_4CSZV = 0x5a,
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Z24V8_MS4_VC12 = 0x5b,
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Z24V8_MS4_VC4 = 0x5c,
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Z24V8_MS8_VC8 = 0x5d,
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Z24V8_MS8_VC24 = 0x5e,
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YUV_B8C1_2Y = 0x60,
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YUV_B8C2_2Y = 0x61,
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YUV_B10C1_2Y = 0x62,
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YUV_B10C2_2Y = 0x6b,
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YUV_B12C1_2Y = 0x6c,
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YUV_B12C2_2Y = 0x6d,
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Z24V8_MS4_VC12_1ZV = 0x63,
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Z24V8_MS4_VC4_1ZV = 0x64,
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Z24V8_MS8_VC8_1ZV = 0x65,
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Z24V8_MS8_VC24_1ZV = 0x66,
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Z24V8_MS4_VC12_2CS = 0x67,
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Z24V8_MS4_VC4_2CS = 0x68,
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Z24V8_MS8_VC8_2CS = 0x69,
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Z24V8_MS8_VC24_2CS = 0x6a,
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Z24V8_MS4_VC12_2CZV = 0x6f,
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Z24V8_MS4_VC4_2CZV = 0x70,
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Z24V8_MS8_VC8_2CZV = 0x71,
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Z24V8_MS8_VC24_2CZV = 0x72,
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Z24V8_MS4_VC12_2ZV = 0x73,
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Z24V8_MS4_VC4_2ZV = 0x74,
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Z24V8_MS8_VC8_2ZV = 0x75,
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Z24V8_MS8_VC24_2ZV = 0x76,
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Z24V8_MS4_VC12_4CSZV = 0x77,
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Z24V8_MS4_VC4_4CSZV = 0x78,
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Z24V8_MS8_VC8_4CSZV = 0x79,
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Z24V8_MS8_VC24_4CSZV = 0x7a,
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ZF32 = 0x7b,
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ZF32_1Z = 0x7c,
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ZF32_MS2_1Z = 0x7d,
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ZF32_MS4_1Z = 0x7e,
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ZF32_MS8_1Z = 0x7f,
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ZF32_MS16_1Z = 0x80,
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ZF32_2CS = 0x81,
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ZF32_MS2_2CS = 0x82,
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ZF32_MS4_2CS = 0x83,
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ZF32_MS8_2CS = 0x84,
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ZF32_MS16_2CS = 0x85,
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ZF32_2CZ = 0x86,
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ZF32_MS2_2CZ = 0x87,
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ZF32_MS4_2CZ = 0x88,
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ZF32_MS8_2CZ = 0x89,
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ZF32_MS16_2CZ = 0x8a,
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X8Z24_X16V8S8_MS4_VC12 = 0x8b,
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X8Z24_X16V8S8_MS4_VC4 = 0x8c,
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X8Z24_X16V8S8_MS8_VC8 = 0x8d,
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X8Z24_X16V8S8_MS8_VC24 = 0x8e,
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X8Z24_X16V8S8_MS4_VC12_1CS = 0x8f,
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X8Z24_X16V8S8_MS4_VC4_1CS = 0x90,
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X8Z24_X16V8S8_MS8_VC8_1CS = 0x91,
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X8Z24_X16V8S8_MS8_VC24_1CS = 0x92,
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X8Z24_X16V8S8_MS4_VC12_1ZV = 0x97,
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X8Z24_X16V8S8_MS4_VC4_1ZV = 0x98,
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X8Z24_X16V8S8_MS8_VC8_1ZV = 0x99,
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X8Z24_X16V8S8_MS8_VC24_1ZV = 0x9a,
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X8Z24_X16V8S8_MS4_VC12_1CZV = 0x9b,
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X8Z24_X16V8S8_MS4_VC4_1CZV = 0x9c,
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X8Z24_X16V8S8_MS8_VC8_1CZV = 0x9d,
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X8Z24_X16V8S8_MS8_VC24_1CZV = 0x9e,
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X8Z24_X16V8S8_MS4_VC12_2CS = 0x9f,
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X8Z24_X16V8S8_MS4_VC4_2CS = 0xa0,
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X8Z24_X16V8S8_MS8_VC8_2CS = 0xa1,
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X8Z24_X16V8S8_MS8_VC24_2CS = 0xa2,
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X8Z24_X16V8S8_MS4_VC12_2CSZV = 0xa3,
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X8Z24_X16V8S8_MS4_VC4_2CSZV = 0xa4,
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X8Z24_X16V8S8_MS8_VC8_2CSZV = 0xa5,
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X8Z24_X16V8S8_MS8_VC24_2CSZV = 0xa6,
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ZF32_X16V8S8_MS4_VC12 = 0xa7,
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ZF32_X16V8S8_MS4_VC4 = 0xa8,
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ZF32_X16V8S8_MS8_VC8 = 0xa9,
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ZF32_X16V8S8_MS8_VC24 = 0xaa,
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ZF32_X16V8S8_MS4_VC12_1CS = 0xab,
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ZF32_X16V8S8_MS4_VC4_1CS = 0xac,
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ZF32_X16V8S8_MS8_VC8_1CS = 0xad,
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ZF32_X16V8S8_MS8_VC24_1CS = 0xae,
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ZF32_X16V8S8_MS4_VC12_1ZV = 0xb3,
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ZF32_X16V8S8_MS4_VC4_1ZV = 0xb4,
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ZF32_X16V8S8_MS8_VC8_1ZV = 0xb5,
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ZF32_X16V8S8_MS8_VC24_1ZV = 0xb6,
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ZF32_X16V8S8_MS4_VC12_1CZV = 0xb7,
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ZF32_X16V8S8_MS4_VC4_1CZV = 0xb8,
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ZF32_X16V8S8_MS8_VC8_1CZV = 0xb9,
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ZF32_X16V8S8_MS8_VC24_1CZV = 0xba,
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ZF32_X16V8S8_MS4_VC12_2CS = 0xbb,
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ZF32_X16V8S8_MS4_VC4_2CS = 0xbc,
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ZF32_X16V8S8_MS8_VC8_2CS = 0xbd,
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ZF32_X16V8S8_MS8_VC24_2CS = 0xbe,
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ZF32_X16V8S8_MS4_VC12_2CSZV = 0xbf,
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ZF32_X16V8S8_MS4_VC4_2CSZV = 0xc0,
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ZF32_X16V8S8_MS8_VC8_2CSZV = 0xc1,
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ZF32_X16V8S8_MS8_VC24_2CSZV = 0xc2,
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ZF32_X24S8 = 0xc3,
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ZF32_X24S8_1CS = 0xc4,
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ZF32_X24S8_MS2_1CS = 0xc5,
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ZF32_X24S8_MS4_1CS = 0xc6,
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ZF32_X24S8_MS8_1CS = 0xc7,
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ZF32_X24S8_MS16_1CS = 0xc8,
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ZF32_X24S8_2CSZV = 0xce,
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ZF32_X24S8_MS2_2CSZV = 0xcf,
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ZF32_X24S8_MS4_2CSZV = 0xd0,
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ZF32_X24S8_MS8_2CSZV = 0xd1,
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ZF32_X24S8_MS16_2CSZV = 0xd2,
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ZF32_X24S8_2CS = 0xd3,
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ZF32_X24S8_MS2_2CS = 0xd4,
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ZF32_X24S8_MS4_2CS = 0xd5,
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ZF32_X24S8_MS8_2CS = 0xd6,
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ZF32_X24S8_MS16_2CS = 0xd7,
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S8 = 0x2a,
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S8_2S = 0x2b,
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GENERIC_16BX2 = 0xfe,
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C32_2C = 0xd8,
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C32_2CBR = 0xd9,
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C32_2CBA = 0xda,
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C32_2CRA = 0xdb,
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C32_2BRA = 0xdc,
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C32_MS2_2C = 0xdd,
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C32_MS2_2CBR = 0xde,
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C32_MS2_4CBRA = 0xcc,
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C32_MS4_2C = 0xdf,
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C32_MS4_2CBR = 0xe0,
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C32_MS4_2CBA = 0xe1,
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C32_MS4_2CRA = 0xe2,
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C32_MS4_2BRA = 0xe3,
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C32_MS4_4CBRA = 0x2c,
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C32_MS8_MS16_2C = 0xe4,
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C32_MS8_MS16_2CRA = 0xe5,
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C64_2C = 0xe6,
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C64_2CBR = 0xe7,
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C64_2CBA = 0xe8,
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C64_2CRA = 0xe9,
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C64_2BRA = 0xea,
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C64_MS2_2C = 0xeb,
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C64_MS2_2CBR = 0xec,
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C64_MS2_4CBRA = 0xcd,
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C64_MS4_2C = 0xed,
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C64_MS4_2CBR = 0xee,
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C64_MS4_2CBA = 0xef,
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C64_MS4_2CRA = 0xf0,
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C64_MS4_2BRA = 0xf1,
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C64_MS4_4CBRA = 0x2d,
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C64_MS8_MS16_2C = 0xf2,
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C64_MS8_MS16_2CRA = 0xf3,
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C128_2C = 0xf4,
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C128_2CR = 0xf5,
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C128_MS2_2C = 0xf6,
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C128_MS2_2CR = 0xf7,
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C128_MS4_2C = 0xf8,
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C128_MS4_2CR = 0xf9,
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C128_MS8_MS16_2C = 0xfa,
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C128_MS8_MS16_2CR = 0xfb,
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X8C24 = 0xfc,
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PITCH_NO_SWIZZLE = 0xfd,
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SMSKED_MESSAGE = 0xca,
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SMHOST_MESSAGE = 0xcb,
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};
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constexpr bool IsPitchKind(PTEKind kind) {
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return kind == PTEKind::PITCH || kind == PTEKind::PITCH_NO_SWIZZLE;
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}
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} // namespace Tegra
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