327 lines
7.4 KiB
C++
327 lines
7.4 KiB
C++
// Copyright 2018 yuzu Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#pragma once
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#include <map>
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#include <string>
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#include "common/bit_field.h"
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namespace Tegra {
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namespace Shader {
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struct Register {
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Register() = default;
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constexpr Register(u64 value) : value(value) {}
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constexpr u64 GetIndex() const {
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return value;
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}
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constexpr operator u64() const {
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return value;
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}
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template <typename T>
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constexpr u64 operator-(const T& oth) const {
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return value - oth;
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}
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template <typename T>
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constexpr u64 operator&(const T& oth) const {
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return value & oth;
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}
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constexpr u64 operator&(const Register& oth) const {
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return value & oth.value;
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}
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constexpr u64 operator~() const {
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return ~value;
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}
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private:
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u64 value;
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};
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union Attribute {
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Attribute() = default;
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constexpr Attribute(u64 value) : value(value) {}
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enum class Index : u64 {
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Position = 7,
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Attribute_0 = 8,
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};
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union {
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BitField<22, 2, u64> element;
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BitField<24, 6, Index> index;
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BitField<47, 3, u64> size;
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} fmt20;
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union {
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BitField<30, 2, u64> element;
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BitField<32, 6, Index> index;
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} fmt28;
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BitField<39, 8, u64> reg;
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u64 value;
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};
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union Uniform {
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BitField<20, 14, u64> offset;
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BitField<34, 5, u64> index;
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};
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union OpCode {
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enum class Id : u64 {
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TEXS = 0x6C,
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IPA = 0xE0,
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FFMA_IMM = 0x65,
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FFMA_CR = 0x93,
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FFMA_RC = 0xA3,
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FFMA_RR = 0xB3,
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FADD_C = 0x98B,
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FMUL_C = 0x98D,
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MUFU = 0xA10,
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FADD_R = 0xB8B,
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FMUL_R = 0xB8D,
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LD_A = 0x1DFB,
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ST_A = 0x1DFE,
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FSETP_R = 0x5BB,
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FSETP_C = 0x4BB,
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EXIT = 0xE30,
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KIL = 0xE33,
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FMUL_IMM = 0x70D,
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FMUL_IMM_x = 0x72D,
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FADD_IMM = 0x70B,
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FADD_IMM_x = 0x72B,
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};
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enum class Type {
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Trivial,
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Arithmetic,
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Ffma,
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Flow,
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Memory,
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Unknown,
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};
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struct Info {
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Type type;
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std::string name;
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};
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OpCode() = default;
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constexpr OpCode(Id value) : value(static_cast<u64>(value)) {}
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constexpr OpCode(u64 value) : value{value} {}
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constexpr Id EffectiveOpCode() const {
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switch (op1) {
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case Id::TEXS:
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return op1;
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}
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switch (op2) {
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case Id::IPA:
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return op2;
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}
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switch (op3) {
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case Id::FFMA_IMM:
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case Id::FFMA_CR:
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case Id::FFMA_RC:
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case Id::FFMA_RR:
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return op3;
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}
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switch (op4) {
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case Id::EXIT:
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case Id::FSETP_R:
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case Id::FSETP_C:
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case Id::KIL:
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return op4;
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}
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switch (op5) {
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case Id::MUFU:
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case Id::LD_A:
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case Id::ST_A:
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case Id::FADD_R:
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case Id::FADD_C:
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case Id::FMUL_R:
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case Id::FMUL_C:
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return op5;
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case Id::FMUL_IMM:
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case Id::FMUL_IMM_x:
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return Id::FMUL_IMM;
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case Id::FADD_IMM:
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case Id::FADD_IMM_x:
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return Id::FADD_IMM;
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}
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return static_cast<Id>(value);
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}
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static const Info& GetInfo(const OpCode& opcode) {
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static const std::map<Id, Info> info_table{BuildInfoTable()};
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const auto& search{info_table.find(opcode.EffectiveOpCode())};
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if (search != info_table.end()) {
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return search->second;
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}
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static const Info unknown{Type::Unknown, "UNK"};
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return unknown;
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}
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constexpr operator Id() const {
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return static_cast<Id>(value);
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}
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constexpr OpCode operator<<(size_t bits) const {
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return value << bits;
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}
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constexpr OpCode operator>>(size_t bits) const {
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return value >> bits;
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}
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template <typename T>
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constexpr u64 operator-(const T& oth) const {
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return value - oth;
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}
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constexpr u64 operator&(const OpCode& oth) const {
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return value & oth.value;
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}
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constexpr u64 operator~() const {
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return ~value;
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}
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static std::map<Id, Info> BuildInfoTable() {
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std::map<Id, Info> info_table;
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info_table[Id::TEXS] = {Type::Memory, "texs"};
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info_table[Id::LD_A] = {Type::Memory, "ld_a"};
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info_table[Id::ST_A] = {Type::Memory, "st_a"};
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info_table[Id::MUFU] = {Type::Arithmetic, "mufu"};
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info_table[Id::FFMA_IMM] = {Type::Ffma, "ffma_imm"};
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info_table[Id::FFMA_CR] = {Type::Ffma, "ffma_cr"};
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info_table[Id::FFMA_RC] = {Type::Ffma, "ffma_rc"};
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info_table[Id::FFMA_RR] = {Type::Ffma, "ffma_rr"};
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info_table[Id::FADD_R] = {Type::Arithmetic, "fadd_r"};
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info_table[Id::FADD_C] = {Type::Arithmetic, "fadd_c"};
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info_table[Id::FADD_IMM] = {Type::Arithmetic, "fadd_imm"};
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info_table[Id::FMUL_R] = {Type::Arithmetic, "fmul_r"};
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info_table[Id::FMUL_C] = {Type::Arithmetic, "fmul_c"};
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info_table[Id::FMUL_IMM] = {Type::Arithmetic, "fmul_imm"};
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info_table[Id::FSETP_C] = {Type::Arithmetic, "fsetp_c"};
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info_table[Id::FSETP_R] = {Type::Arithmetic, "fsetp_r"};
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info_table[Id::EXIT] = {Type::Trivial, "exit"};
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info_table[Id::IPA] = {Type::Trivial, "ipa"};
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info_table[Id::KIL] = {Type::Flow, "kil"};
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return info_table;
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}
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BitField<57, 7, Id> op1;
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BitField<56, 8, Id> op2;
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BitField<55, 9, Id> op3;
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BitField<52, 12, Id> op4;
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BitField<51, 13, Id> op5;
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u64 value;
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};
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static_assert(sizeof(OpCode) == 0x8, "Incorrect structure size");
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} // namespace Shader
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} // namespace Tegra
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namespace std {
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// TODO(bunne): The below is forbidden by the C++ standard, but works fine. See #330.
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template <>
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struct make_unsigned<Tegra::Shader::Attribute> {
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using type = Tegra::Shader::Attribute;
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};
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template <>
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struct make_unsigned<Tegra::Shader::Register> {
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using type = Tegra::Shader::Register;
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};
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template <>
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struct make_unsigned<Tegra::Shader::OpCode> {
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using type = Tegra::Shader::OpCode;
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};
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} // namespace std
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namespace Tegra {
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namespace Shader {
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enum class Pred : u64 {
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UnusedIndex = 0x7,
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NeverExecute = 0xf,
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};
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enum class SubOp : u64 {
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Cos = 0x0,
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Sin = 0x1,
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Ex2 = 0x2,
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Lg2 = 0x3,
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Rcp = 0x4,
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Rsq = 0x5,
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};
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union Instruction {
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Instruction& operator=(const Instruction& instr) {
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hex = instr.hex;
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return *this;
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}
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OpCode opcode;
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BitField<0, 8, Register> gpr0;
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BitField<8, 8, Register> gpr8;
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BitField<16, 4, Pred> pred;
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BitField<20, 8, Register> gpr20;
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BitField<20, 7, SubOp> sub_op;
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BitField<28, 8, Register> gpr28;
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BitField<36, 13, u64> imm36;
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BitField<39, 8, Register> gpr39;
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union {
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BitField<45, 1, u64> negate_b;
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BitField<46, 1, u64> abs_a;
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BitField<48, 1, u64> negate_a;
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BitField<49, 1, u64> abs_b;
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BitField<50, 1, u64> abs_d;
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} alu;
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union {
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BitField<48, 1, u64> negate_b;
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BitField<49, 1, u64> negate_c;
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} ffma;
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BitField<60, 1, u64> is_b_gpr;
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BitField<59, 1, u64> is_c_gpr;
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Attribute attribute;
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Uniform uniform;
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u64 hex;
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};
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static_assert(sizeof(Instruction) == 0x8, "Incorrect structure size");
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static_assert(std::is_standard_layout<Instruction>::value,
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"Structure does not have standard layout");
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} // namespace Shader
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} // namespace Tegra
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