maxwell_3d: Fix depth clamping register
Using deko3d as reference:
4e47ba0013/source/maxwell/gpu_3d_state.cpp (L42)
We were using bits 3 and 4 to determine depth clamping, but these are
the same both enabled and disabled:
state->depthClampEnable ? 0x101A : 0x181D
The same happens on Nvidia's OpenGL driver, where they do something like
this (default capabilities, GL 4.5 compatibility):
(state & DEPTH_CLAMP) != 0 ? 0x201a : 0x281c
There's always a difference between the first bits in this register, but
bit 11 is consistently disabled on both deko3d/NVN and OpenGL. This
commit changes yuzu's behaviour to use bit 11 to determine depth
clamping.
- Fixes depth issues on Super Mario Odyssey's intro.
This commit is contained in:
parent
1517cba8ca
commit
bb1ed66d99
5 changed files with 5 additions and 8 deletions
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@ -1179,6 +1179,7 @@ public:
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BitField<0, 1, u32> depth_range_0_1;
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BitField<3, 1, u32> depth_clamp_near;
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BitField<4, 1, u32> depth_clamp_far;
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BitField<11, 1, u32> depth_clamp_disabled;
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} view_volume_clip_control;
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INSERT_UNION_PADDING_WORDS(0x1F);
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@ -999,11 +999,7 @@ void RasterizerOpenGL::SyncDepthClamp() {
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}
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flags[Dirty::DepthClampEnabled] = false;
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const auto& state = gpu.regs.view_volume_clip_control;
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UNIMPLEMENTED_IF_MSG(state.depth_clamp_far != state.depth_clamp_near,
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"Unimplemented depth clamp separation!");
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oglEnable(GL_DEPTH_CLAMP, state.depth_clamp_far || state.depth_clamp_near);
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oglEnable(GL_DEPTH_CLAMP, gpu.regs.view_volume_clip_control.depth_clamp_disabled == 0);
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}
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void RasterizerOpenGL::SyncClipEnabled(u32 clip_mask) {
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@ -81,7 +81,7 @@ void FixedPipelineState::Rasterizer::Fill(const Maxwell& regs) noexcept {
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primitive_restart_enable.Assign(regs.primitive_restart.enabled != 0 ? 1 : 0);
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cull_enable.Assign(regs.cull_test_enabled != 0 ? 1 : 0);
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depth_bias_enable.Assign(enabled_lut[POLYGON_OFFSET_ENABLE_LUT[topology_index]] != 0 ? 1 : 0);
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depth_clamp_enable.Assign(clip.depth_clamp_near == 1 || clip.depth_clamp_far == 1 ? 1 : 0);
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depth_clamp_disabled.Assign(regs.view_volume_clip_control.depth_clamp_disabled.Value());
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ndc_minus_one_to_one.Assign(regs.depth_mode == Maxwell::DepthMode::MinusOneToOne ? 1 : 0);
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cull_face.Assign(PackCullFace(regs.cull_face));
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front_face.Assign(packed_front_face);
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@ -153,7 +153,7 @@ struct FixedPipelineState {
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BitField<4, 1, u32> primitive_restart_enable;
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BitField<5, 1, u32> cull_enable;
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BitField<6, 1, u32> depth_bias_enable;
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BitField<7, 1, u32> depth_clamp_enable;
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BitField<7, 1, u32> depth_clamp_disabled;
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BitField<8, 1, u32> ndc_minus_one_to_one;
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BitField<9, 2, u32> cull_face;
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BitField<11, 1, u32> front_face;
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@ -249,7 +249,7 @@ vk::Pipeline VKGraphicsPipeline::CreatePipeline(const RenderPassParams& renderpa
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rasterization_ci.sType = VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_STATE_CREATE_INFO;
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rasterization_ci.pNext = nullptr;
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rasterization_ci.flags = 0;
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rasterization_ci.depthClampEnable = rs.depth_clamp_enable;
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rasterization_ci.depthClampEnable = rs.depth_clamp_disabled == 0 ? VK_TRUE : VK_FALSE;
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rasterization_ci.rasterizerDiscardEnable = VK_FALSE;
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rasterization_ci.polygonMode = VK_POLYGON_MODE_FILL;
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rasterization_ci.cullMode =
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