shader_bytecode: Make use of [[nodiscard]] where applicable
Ensures that all queried values are made use of.
This commit is contained in:
Lioncash
parent
56ecafc204
commit
b7cd5d742e
1 changed files with 79 additions and 73 deletions
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@ -34,29 +34,29 @@ struct Register {
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constexpr Register(u64 value_) : value(value_) {}
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constexpr operator u64() const {
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[[nodiscard]] constexpr operator u64() const {
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return value;
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}
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template <typename T>
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constexpr u64 operator-(const T& oth) const {
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[[nodiscard]] constexpr u64 operator-(const T& oth) const {
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return value - oth;
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}
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template <typename T>
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constexpr u64 operator&(const T& oth) const {
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[[nodiscard]] constexpr u64 operator&(const T& oth) const {
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return value & oth;
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}
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constexpr u64 operator&(const Register& oth) const {
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[[nodiscard]] constexpr u64 operator&(const Register& oth) const {
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return value & oth.value;
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}
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constexpr u64 operator~() const {
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[[nodiscard]] constexpr u64 operator~() const {
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return ~value;
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}
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u64 GetSwizzledIndex(u64 elem) const {
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[[nodiscard]] u64 GetSwizzledIndex(u64 elem) const {
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elem = (value + elem) & 3;
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return (value & ~3) + elem;
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}
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@ -107,7 +107,7 @@ union Attribute {
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BitField<31, 1, u64> patch;
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BitField<47, 3, AttributeSize> size;
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bool IsPhysical() const {
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[[nodiscard]] bool IsPhysical() const {
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return patch == 0 && element == 0 && static_cast<u64>(index.Value()) == 0;
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}
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} fmt20;
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@ -505,14 +505,14 @@ struct IpaMode {
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IpaInterpMode interpolation_mode;
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IpaSampleMode sampling_mode;
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bool operator==(const IpaMode& a) const {
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[[nodiscard]] bool operator==(const IpaMode& a) const {
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return std::tie(interpolation_mode, sampling_mode) ==
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std::tie(a.interpolation_mode, a.sampling_mode);
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}
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bool operator!=(const IpaMode& a) const {
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[[nodiscard]] bool operator!=(const IpaMode& a) const {
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return !operator==(a);
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}
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bool operator<(const IpaMode& a) const {
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[[nodiscard]] bool operator<(const IpaMode& a) const {
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return std::tie(interpolation_mode, sampling_mode) <
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std::tie(a.interpolation_mode, a.sampling_mode);
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}
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@ -661,7 +661,7 @@ union Instruction {
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constexpr Instruction(u64 value_) : value{value_} {}
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constexpr Instruction(const Instruction& instr) : value(instr.value) {}
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constexpr bool Bit(u64 offset) const {
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[[nodiscard]] constexpr bool Bit(u64 offset) const {
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return ((value >> offset) & 1) != 0;
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}
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@ -746,34 +746,34 @@ union Instruction {
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BitField<28, 8, u64> imm_lut28;
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BitField<48, 8, u64> imm_lut48;
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u32 GetImmLut28() const {
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[[nodiscard]] u32 GetImmLut28() const {
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return static_cast<u32>(imm_lut28);
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}
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u32 GetImmLut48() const {
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[[nodiscard]] u32 GetImmLut48() const {
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return static_cast<u32>(imm_lut48);
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}
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} lop3;
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u16 GetImm20_16() const {
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[[nodiscard]] u16 GetImm20_16() const {
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return static_cast<u16>(imm20_16);
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}
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u32 GetImm20_19() const {
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[[nodiscard]] u32 GetImm20_19() const {
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u32 imm{static_cast<u32>(imm20_19)};
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imm <<= 12;
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imm |= negate_imm ? 0x80000000 : 0;
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return imm;
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}
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u32 GetImm20_32() const {
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[[nodiscard]] u32 GetImm20_32() const {
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return static_cast<u32>(imm20_32);
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}
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s32 GetSignedImm20_20() const {
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u32 immediate = static_cast<u32>(imm20_19 | (negate_imm << 19));
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[[nodiscard]] s32 GetSignedImm20_20() const {
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const auto immediate = static_cast<u32>(imm20_19 | (negate_imm << 19));
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// Sign extend the 20-bit value.
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u32 mask = 1U << (20 - 1);
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const auto mask = 1U << (20 - 1);
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return static_cast<s32>((immediate ^ mask) - mask);
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}
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} alu;
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@ -857,7 +857,7 @@ union Instruction {
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BitField<56, 1, u64> second_negate;
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BitField<30, 9, u64> second;
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u32 PackImmediates() const {
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[[nodiscard]] u32 PackImmediates() const {
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// Immediates are half floats shifted.
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constexpr u32 imm_shift = 6;
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return static_cast<u32>((first << imm_shift) | (second << (16 + imm_shift)));
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@ -1033,7 +1033,7 @@ union Instruction {
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BitField<28, 2, AtomicType> type;
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BitField<30, 22, s64> offset;
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s32 GetImmediateOffset() const {
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[[nodiscard]] s32 GetImmediateOffset() const {
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return static_cast<s32>(offset << 2);
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}
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} atoms;
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@ -1215,7 +1215,7 @@ union Instruction {
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BitField<39, 4, u64> rounding;
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// H0, H1 extract for F16 missing
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BitField<41, 1, u64> selector; // Guessed as some games set it, TODO: reverse this value
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F2fRoundingOp GetRoundingMode() const {
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[[nodiscard]] F2fRoundingOp GetRoundingMode() const {
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constexpr u64 rounding_mask = 0x0B;
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return static_cast<F2fRoundingOp>(rounding.Value() & rounding_mask);
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}
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@ -1239,15 +1239,15 @@ union Instruction {
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BitField<54, 1, u64> aoffi_flag;
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BitField<55, 3, TextureProcessMode> process_mode;
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bool IsComponentEnabled(std::size_t component) const {
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return ((1ull << component) & component_mask) != 0;
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[[nodiscard]] bool IsComponentEnabled(std::size_t component) const {
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return ((1ULL << component) & component_mask) != 0;
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}
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TextureProcessMode GetTextureProcessMode() const {
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[[nodiscard]] TextureProcessMode GetTextureProcessMode() const {
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return process_mode;
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}
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bool UsesMiscMode(TextureMiscMode mode) const {
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[[nodiscard]] bool UsesMiscMode(TextureMiscMode mode) const {
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switch (mode) {
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case TextureMiscMode::DC:
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return dc_flag != 0;
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@ -1271,15 +1271,15 @@ union Instruction {
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BitField<36, 1, u64> aoffi_flag;
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BitField<37, 3, TextureProcessMode> process_mode;
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bool IsComponentEnabled(std::size_t component) const {
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[[nodiscard]] bool IsComponentEnabled(std::size_t component) const {
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return ((1ULL << component) & component_mask) != 0;
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}
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TextureProcessMode GetTextureProcessMode() const {
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[[nodiscard]] TextureProcessMode GetTextureProcessMode() const {
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return process_mode;
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}
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bool UsesMiscMode(TextureMiscMode mode) const {
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[[nodiscard]] bool UsesMiscMode(TextureMiscMode mode) const {
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switch (mode) {
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case TextureMiscMode::DC:
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return dc_flag != 0;
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@ -1299,7 +1299,7 @@ union Instruction {
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BitField<31, 4, u64> component_mask;
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BitField<49, 1, u64> nodep_flag;
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bool UsesMiscMode(TextureMiscMode mode) const {
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[[nodiscard]] bool UsesMiscMode(TextureMiscMode mode) const {
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switch (mode) {
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case TextureMiscMode::NODEP:
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return nodep_flag != 0;
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@ -1309,7 +1309,7 @@ union Instruction {
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return false;
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}
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bool IsComponentEnabled(std::size_t component) const {
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[[nodiscard]] bool IsComponentEnabled(std::size_t component) const {
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return ((1ULL << component) & component_mask) != 0;
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}
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} txq;
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@ -1321,11 +1321,11 @@ union Instruction {
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BitField<35, 1, u64> ndv_flag;
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BitField<49, 1, u64> nodep_flag;
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bool IsComponentEnabled(std::size_t component) const {
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return ((1ull << component) & component_mask) != 0;
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[[nodiscard]] bool IsComponentEnabled(std::size_t component) const {
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return ((1ULL << component) & component_mask) != 0;
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}
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bool UsesMiscMode(TextureMiscMode mode) const {
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[[nodiscard]] bool UsesMiscMode(TextureMiscMode mode) const {
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switch (mode) {
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case TextureMiscMode::NDV:
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return (ndv_flag != 0);
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@ -1347,7 +1347,7 @@ union Instruction {
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BitField<54, 2, u64> offset_mode;
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BitField<56, 2, u64> component;
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bool UsesMiscMode(TextureMiscMode mode) const {
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[[nodiscard]] bool UsesMiscMode(TextureMiscMode mode) const {
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switch (mode) {
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case TextureMiscMode::NDV:
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return ndv_flag != 0;
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@ -1373,7 +1373,7 @@ union Instruction {
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BitField<33, 2, u64> offset_mode;
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BitField<37, 2, u64> component;
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bool UsesMiscMode(TextureMiscMode mode) const {
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[[nodiscard]] bool UsesMiscMode(TextureMiscMode mode) const {
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switch (mode) {
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case TextureMiscMode::NDV:
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return ndv_flag != 0;
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@ -1399,7 +1399,7 @@ union Instruction {
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BitField<52, 2, u64> component;
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BitField<55, 1, u64> fp16_flag;
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bool UsesMiscMode(TextureMiscMode mode) const {
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[[nodiscard]] bool UsesMiscMode(TextureMiscMode mode) const {
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switch (mode) {
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case TextureMiscMode::DC:
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return dc_flag != 0;
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@ -1422,16 +1422,20 @@ union Instruction {
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BitField<53, 4, u64> texture_info;
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BitField<59, 1, u64> fp32_flag;
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TextureType GetTextureType() const {
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[[nodiscard]] TextureType GetTextureType() const {
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// The TEXS instruction has a weird encoding for the texture type.
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if (texture_info == 0)
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if (texture_info == 0) {
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return TextureType::Texture1D;
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if (texture_info >= 1 && texture_info <= 9)
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}
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if (texture_info >= 1 && texture_info <= 9) {
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return TextureType::Texture2D;
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if (texture_info >= 10 && texture_info <= 11)
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}
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if (texture_info >= 10 && texture_info <= 11) {
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return TextureType::Texture3D;
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if (texture_info >= 12 && texture_info <= 13)
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}
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if (texture_info >= 12 && texture_info <= 13) {
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return TextureType::TextureCube;
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}
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LOG_CRITICAL(HW_GPU, "Unhandled texture_info: {}",
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static_cast<u32>(texture_info.Value()));
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@ -1439,7 +1443,7 @@ union Instruction {
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return TextureType::Texture1D;
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}
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TextureProcessMode GetTextureProcessMode() const {
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[[nodiscard]] TextureProcessMode GetTextureProcessMode() const {
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switch (texture_info) {
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case 0:
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case 2:
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@ -1458,7 +1462,7 @@ union Instruction {
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return TextureProcessMode::None;
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}
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bool UsesMiscMode(TextureMiscMode mode) const {
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[[nodiscard]] bool UsesMiscMode(TextureMiscMode mode) const {
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switch (mode) {
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case TextureMiscMode::DC:
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return (texture_info >= 4 && texture_info <= 6) || texture_info == 9;
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@ -1470,16 +1474,16 @@ union Instruction {
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return false;
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}
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bool IsArrayTexture() const {
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[[nodiscard]] bool IsArrayTexture() const {
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// TEXS only supports Texture2D arrays.
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return texture_info >= 7 && texture_info <= 9;
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}
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bool HasTwoDestinations() const {
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[[nodiscard]] bool HasTwoDestinations() const {
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return gpr28.Value() != Register::ZeroIndex;
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}
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bool IsComponentEnabled(std::size_t component) const {
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[[nodiscard]] bool IsComponentEnabled(std::size_t component) const {
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static constexpr std::array<std::array<u32, 8>, 4> mask_lut{{
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{},
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{0x1, 0x2, 0x4, 0x8, 0x3, 0x9, 0xa, 0xc},
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@ -1506,7 +1510,7 @@ union Instruction {
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BitField<54, 1, u64> cl;
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BitField<55, 1, u64> process_mode;
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TextureProcessMode GetTextureProcessMode() const {
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[[nodiscard]] TextureProcessMode GetTextureProcessMode() const {
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return process_mode == 0 ? TextureProcessMode::LZ : TextureProcessMode::LL;
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}
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} tld;
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@ -1516,7 +1520,7 @@ union Instruction {
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BitField<53, 4, u64> texture_info;
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BitField<59, 1, u64> fp32_flag;
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TextureType GetTextureType() const {
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[[nodiscard]] TextureType GetTextureType() const {
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// The TLDS instruction has a weird encoding for the texture type.
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if (texture_info <= 1) {
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return TextureType::Texture1D;
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@ -1535,13 +1539,14 @@ union Instruction {
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return TextureType::Texture1D;
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}
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TextureProcessMode GetTextureProcessMode() const {
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if (texture_info == 1 || texture_info == 5 || texture_info == 12)
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[[nodiscard]] TextureProcessMode GetTextureProcessMode() const {
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if (texture_info == 1 || texture_info == 5 || texture_info == 12) {
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return TextureProcessMode::LL;
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}
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return TextureProcessMode::LZ;
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}
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bool UsesMiscMode(TextureMiscMode mode) const {
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[[nodiscard]] bool UsesMiscMode(TextureMiscMode mode) const {
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switch (mode) {
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case TextureMiscMode::AOFFI:
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return texture_info == 12 || texture_info == 4;
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@ -1555,7 +1560,7 @@ union Instruction {
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return false;
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}
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bool IsArrayTexture() const {
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[[nodiscard]] bool IsArrayTexture() const {
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// TEXS only supports Texture2D arrays.
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return texture_info == 8;
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}
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@ -1567,7 +1572,7 @@ union Instruction {
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BitField<35, 1, u64> aoffi_flag;
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BitField<49, 1, u64> nodep_flag;
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bool UsesMiscMode(TextureMiscMode mode) const {
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[[nodiscard]] bool UsesMiscMode(TextureMiscMode mode) const {
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switch (mode) {
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case TextureMiscMode::AOFFI:
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return aoffi_flag != 0;
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@ -1591,7 +1596,7 @@ union Instruction {
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BitField<20, 3, StoreType> store_data_layout;
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BitField<20, 4, u64> component_mask_selector;
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bool IsComponentEnabled(std::size_t component) const {
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[[nodiscard]] bool IsComponentEnabled(std::size_t component) const {
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ASSERT(mode == SurfaceDataMode::P);
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constexpr u8 R = 0b0001;
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constexpr u8 G = 0b0010;
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@ -1604,7 +1609,7 @@ union Instruction {
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return std::bitset<4>{mask.at(component_mask_selector)}.test(component);
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}
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StoreType GetStoreDataLayout() const {
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[[nodiscard]] StoreType GetStoreDataLayout() const {
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ASSERT(mode == SurfaceDataMode::D_BA);
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return store_data_layout;
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}
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@ -1622,7 +1627,7 @@ union Instruction {
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BitField<20, 24, u64> target;
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BitField<5, 1, u64> constant_buffer;
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s32 GetBranchTarget() const {
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[[nodiscard]] s32 GetBranchTarget() const {
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// Sign extend the branch target offset
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const auto mask = 1U << (24 - 1);
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const auto target_value = static_cast<u32>(target);
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@ -1638,7 +1643,7 @@ union Instruction {
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BitField<20, 24, u64> target;
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BitField<5, 1, u64> constant_buffer;
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s32 GetBranchExtend() const {
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[[nodiscard]] s32 GetBranchExtend() const {
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// Sign extend the branch target offset
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const auto mask = 1U << (24 - 1);
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const auto target_value = static_cast<u32>(target);
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@ -1699,7 +1704,7 @@ union Instruction {
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BitField<50, 1, u64> is_op_b_register;
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BitField<51, 3, VmnmxOperation> operation;
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VmnmxType SourceFormatA() const {
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[[nodiscard]] VmnmxType SourceFormatA() const {
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switch (src_format_a) {
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case 0b11:
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return VmnmxType::Bits32;
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@ -1710,7 +1715,7 @@ union Instruction {
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}
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}
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VmnmxType SourceFormatB() const {
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[[nodiscard]] VmnmxType SourceFormatB() const {
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switch (src_format_b) {
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case 0b11:
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return VmnmxType::Bits32;
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@ -1741,7 +1746,7 @@ union Instruction {
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BitField<20, 14, u64> shifted_offset;
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BitField<34, 5, u64> index;
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u64 GetOffset() const {
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[[nodiscard]] u64 GetOffset() const {
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return shifted_offset * 4;
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}
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} cbuf34;
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@ -1750,7 +1755,7 @@ union Instruction {
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BitField<20, 16, s64> offset;
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BitField<36, 5, u64> index;
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s64 GetOffset() const {
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||||
[[nodiscard]] s64 GetOffset() const {
|
||||
return offset;
|
||||
}
|
||||
} cbuf36;
|
||||
|
|
@ -1999,7 +2004,7 @@ public:
|
|||
|
||||
/// Returns whether an opcode has an execution predicate field or not (ie, whether it can be
|
||||
/// conditionally executed).
|
||||
static bool IsPredicatedInstruction(Id opcode) {
|
||||
[[nodiscard]] static bool IsPredicatedInstruction(Id opcode) {
|
||||
// TODO(Subv): Add the rest of unpredicated instructions.
|
||||
return opcode != Id::SSY && opcode != Id::PBK;
|
||||
}
|
||||
|
|
@ -2009,19 +2014,19 @@ public:
|
|||
constexpr Matcher(const char* const name_, u16 mask_, u16 expected_, Id id_, Type type_)
|
||||
: name{name_}, mask{mask_}, expected{expected_}, id{id_}, type{type_} {}
|
||||
|
||||
constexpr const char* GetName() const {
|
||||
[[nodiscard]] constexpr const char* GetName() const {
|
||||
return name;
|
||||
}
|
||||
|
||||
constexpr u16 GetMask() const {
|
||||
[[nodiscard]] constexpr u16 GetMask() const {
|
||||
return mask;
|
||||
}
|
||||
|
||||
constexpr Id GetId() const {
|
||||
[[nodiscard]] constexpr Id GetId() const {
|
||||
return id;
|
||||
}
|
||||
|
||||
constexpr Type GetType() const {
|
||||
[[nodiscard]] constexpr Type GetType() const {
|
||||
return type;
|
||||
}
|
||||
|
||||
|
|
@ -2030,7 +2035,7 @@ public:
|
|||
* @param instruction The instruction to test
|
||||
* @returns true if the given instruction matches.
|
||||
*/
|
||||
constexpr bool Matches(u16 instruction) const {
|
||||
[[nodiscard]] constexpr bool Matches(u16 instruction) const {
|
||||
return (instruction & mask) == expected;
|
||||
}
|
||||
|
||||
|
|
@ -2042,7 +2047,8 @@ public:
|
|||
Type type;
|
||||
};
|
||||
|
||||
static std::optional<std::reference_wrapper<const Matcher>> Decode(Instruction instr) {
|
||||
using DecodeResult = std::optional<std::reference_wrapper<const Matcher>>;
|
||||
[[nodiscard]] static DecodeResult Decode(Instruction instr) {
|
||||
static const auto table{GetDecodeTable()};
|
||||
|
||||
const auto matches_instruction = [instr](const auto& matcher) {
|
||||
|
|
@ -2064,7 +2070,7 @@ private:
|
|||
* A '0' in a bitstring indicates that a zero must be present at that bit position.
|
||||
* A '1' in a bitstring indicates that a one must be present at that bit position.
|
||||
*/
|
||||
static constexpr auto GetMaskAndExpect(const char* const bitstring) {
|
||||
[[nodiscard]] static constexpr auto GetMaskAndExpect(const char* const bitstring) {
|
||||
u16 mask = 0, expect = 0;
|
||||
for (std::size_t i = 0; i < opcode_bitsize; i++) {
|
||||
const std::size_t bit_position = opcode_bitsize - i - 1;
|
||||
|
|
@ -2086,14 +2092,14 @@ private:
|
|||
|
||||
public:
|
||||
/// Creates a matcher that can match and parse instructions based on bitstring.
|
||||
static constexpr auto GetMatcher(const char* const bitstring, Id op, Type type,
|
||||
const char* const name) {
|
||||
[[nodiscard]] static constexpr auto GetMatcher(const char* const bitstring, Id op,
|
||||
Type type, const char* const name) {
|
||||
const auto [mask, expected] = GetMaskAndExpect(bitstring);
|
||||
return Matcher(name, mask, expected, op, type);
|
||||
}
|
||||
};
|
||||
|
||||
static std::vector<Matcher> GetDecodeTable() {
|
||||
[[nodiscard]] static std::vector<Matcher> GetDecodeTable() {
|
||||
std::vector<Matcher> table = {
|
||||
#define INST(bitstring, op, type, name) Detail::GetMatcher(bitstring, op, type, name)
|
||||
INST("111000110011----", Id::KIL, Type::Flow, "KIL"),
|
||||
|
|
|
|||
Loading…
Reference in a new issue