dyncom: Various cleanups to match coding style, no functional changes.
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bunnei
parent
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commit
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5 changed files with 5705 additions and 6830 deletions
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/* Copyright (C)
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// Copyright 2012 Michael Kang, 2014 Citra Emulator Project
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* 2012 - Michael.Kang blackfin.kang@gmail.com
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// Licensed under GPLv2 or any later version
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* This program is free software; you can redistribute it and/or
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// Refer to the license.txt file included.
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*
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*/
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/**
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* @file arm_dyncom_dec.cpp
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* @brief Some common utility for arm decoder
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* @author Michael.Kang blackfin.kang@gmail.com
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* @version 7849
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* @date 2012-03-15
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*/
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#include "core/arm/skyeye_common/arm_regformat.h"
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#include "core/arm/skyeye_common/arm_regformat.h"
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#include "core/arm/skyeye_common/armdefs.h"
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#include "core/arm/skyeye_common/armdefs.h"
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#include "core/arm/dyncom/arm_dyncom_dec.h"
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#include "core/arm/dyncom/arm_dyncom_dec.h"
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const ISEITEM arm_instruction[] = {
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const ISEITEM arm_instruction[] = {
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{"vmla", 4, ARMVFP2, 23, 27, 0x1C, 20, 21, 0x0, 9, 11, 0x5, 4, 4, 0},
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{ "vmla", 4, ARMVFP2, 23, 27, 0x1C, 20, 21, 0x0, 9, 11, 0x5, 4, 4, 0 },
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{"vmls", 7, ARMVFP2, 28, 31, 0xF, 25, 27, 0x1, 23, 23, 1, 11, 11, 0, 8, 9, 0x2, 6, 6, 1, 4, 4, 0},
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{ "vmls", 7, ARMVFP2, 28, 31, 0xF, 25, 27, 0x1, 23, 23, 1, 11, 11, 0, 8, 9, 0x2, 6, 6, 1, 4, 4, 0 },
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{"vnmla", 4, ARMVFP2, 23, 27, 0x1C, 20, 21, 0x1, 9, 11, 0x5, 4, 4, 0},
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{ "vnmla", 4, ARMVFP2, 23, 27, 0x1C, 20, 21, 0x1, 9, 11, 0x5, 4, 4, 0 },
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{"vnmla", 5, ARMVFP2, 23, 27, 0x1C, 20, 21, 0x2, 9, 11, 0x5, 6, 6, 1, 4, 4, 0},
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{ "vnmla", 5, ARMVFP2, 23, 27, 0x1C, 20, 21, 0x2, 9, 11, 0x5, 6, 6, 1, 4, 4, 0 },
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{"vnmls", 5, ARMVFP2, 23, 27, 0x1C, 20, 21, 0x1, 9, 11, 0x5, 6, 6, 0, 4, 4, 0},
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{ "vnmls", 5, ARMVFP2, 23, 27, 0x1C, 20, 21, 0x1, 9, 11, 0x5, 6, 6, 0, 4, 4, 0 },
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{"vnmul", 5, ARMVFP2, 23, 27, 0x1C, 20, 21, 0x2, 9, 11, 0x5, 6, 6, 1, 4, 4, 0},
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{ "vnmul", 5, ARMVFP2, 23, 27, 0x1C, 20, 21, 0x2, 9, 11, 0x5, 6, 6, 1, 4, 4, 0 },
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{"vmul", 5, ARMVFP2, 23, 27, 0x1C, 20, 21, 0x2, 9, 11, 0x5, 6, 6, 0, 4, 4, 0},
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{ "vmul", 5, ARMVFP2, 23, 27, 0x1C, 20, 21, 0x2, 9, 11, 0x5, 6, 6, 0, 4, 4, 0 },
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{"vadd", 5, ARMVFP2, 23, 27, 0x1C, 20, 21, 0x3, 9, 11, 0x5, 6, 6, 0, 4, 4, 0},
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{ "vadd", 5, ARMVFP2, 23, 27, 0x1C, 20, 21, 0x3, 9, 11, 0x5, 6, 6, 0, 4, 4, 0 },
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{"vsub", 5, ARMVFP2, 23, 27, 0x1C, 20, 21, 0x3, 9, 11, 0x5, 6, 6, 1, 4, 4, 0},
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{ "vsub", 5, ARMVFP2, 23, 27, 0x1C, 20, 21, 0x3, 9, 11, 0x5, 6, 6, 1, 4, 4, 0 },
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{"vdiv", 5, ARMVFP2, 23, 27, 0x1D, 20, 21, 0x0, 9, 11, 0x5, 6, 6, 0, 4, 4, 0},
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{ "vdiv", 5, ARMVFP2, 23, 27, 0x1D, 20, 21, 0x0, 9, 11, 0x5, 6, 6, 0, 4, 4, 0 },
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{"vmov(i)", 4, ARMVFP3, 23, 27, 0x1D, 20, 21, 0x3, 9, 11, 0x5, 4, 7, 0},
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{ "vmov(i)", 4, ARMVFP3, 23, 27, 0x1D, 20, 21, 0x3, 9, 11, 0x5, 4, 7, 0 },
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{"vmov(r)", 5, ARMVFP3, 23, 27, 0x1D, 16, 21, 0x30, 9, 11, 0x5, 6, 7, 1, 4, 4, 0},
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{ "vmov(r)", 5, ARMVFP3, 23, 27, 0x1D, 16, 21, 0x30, 9, 11, 0x5, 6, 7, 1, 4, 4, 0 },
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{"vabs", 5, ARMVFP2, 23, 27, 0x1D, 16, 21, 0x30, 9, 11, 0x5, 6, 7, 3, 4, 4, 0},
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{ "vabs", 5, ARMVFP2, 23, 27, 0x1D, 16, 21, 0x30, 9, 11, 0x5, 6, 7, 3, 4, 4, 0 },
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{"vneg", 5, ARMVFP2, 23, 27, 0x1D, 17, 21, 0x18, 9, 11, 0x5, 6, 7, 1, 4, 4, 0},
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{ "vneg", 5, ARMVFP2, 23, 27, 0x1D, 17, 21, 0x18, 9, 11, 0x5, 6, 7, 1, 4, 4, 0 },
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{"vsqrt", 5, ARMVFP2, 23, 27, 0x1D, 16, 21, 0x31, 9, 11, 0x5, 6, 7, 3, 4, 4, 0},
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{ "vsqrt", 5, ARMVFP2, 23, 27, 0x1D, 16, 21, 0x31, 9, 11, 0x5, 6, 7, 3, 4, 4, 0 },
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{"vcmp", 5, ARMVFP2, 23, 27, 0x1D, 16, 21, 0x34, 9, 11, 0x5, 6, 6, 1, 4, 4, 0},
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{ "vcmp", 5, ARMVFP2, 23, 27, 0x1D, 16, 21, 0x34, 9, 11, 0x5, 6, 6, 1, 4, 4, 0 },
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{"vcmp2", 5, ARMVFP2, 23, 27, 0x1D, 16, 21, 0x35, 9, 11, 0x5, 0, 6, 0x40},
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{ "vcmp2", 5, ARMVFP2, 23, 27, 0x1D, 16, 21, 0x35, 9, 11, 0x5, 0, 6, 0x40 },
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{"vcvt(bds)", 5, ARMVFP2, 23, 27, 0x1D, 16, 21, 0x37, 9, 11, 0x5, 6, 7, 3, 4, 4, 0},
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{ "vcvt(bds)", 5, ARMVFP2, 23, 27, 0x1D, 16, 21, 0x37, 9, 11, 0x5, 6, 7, 3, 4, 4, 0 },
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{"vcvt(bff)", 6, ARMVFP3, 23, 27, 0x1D, 19, 21, 0x7, 17, 17, 0x1, 9, 11,5, 6, 6, 1},
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{ "vcvt(bff)", 6, ARMVFP3, 23, 27, 0x1D, 19, 21, 0x7, 17, 17, 0x1, 9, 11, 5, 6, 6, 1 },
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{"vcvt(bfi)", 5, ARMVFP2, 23, 27, 0x1D, 19, 21, 0x7, 9, 11, 0x5, 6, 6, 1, 4, 4, 0},
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{ "vcvt(bfi)", 5, ARMVFP2, 23, 27, 0x1D, 19, 21, 0x7, 9, 11, 0x5, 6, 6, 1, 4, 4, 0 },
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{"vmovbrs", 3, ARMVFP2, 21, 27, 0x70, 8, 11, 0xA, 0, 6, 0x10},
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{ "vmovbrs", 3, ARMVFP2, 21, 27, 0x70, 8, 11, 0xA, 0, 6, 0x10 },
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{"vmsr", 2, ARMVFP2, 20, 27, 0xEE, 0, 11, 0xA10},
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{ "vmsr", 2, ARMVFP2, 20, 27, 0xEE, 0, 11, 0xA10 },
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{"vmovbrc", 4, ARMVFP2, 23, 27, 0x1C, 20, 20, 0x0, 8, 11, 0xB, 0,4,0x10},
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{ "vmovbrc", 4, ARMVFP2, 23, 27, 0x1C, 20, 20, 0x0, 8, 11, 0xB, 0, 4, 0x10 },
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{"vmrs", 2, ARMVFP2, 20, 27, 0xEF, 0, 11, 0xA10},
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{ "vmrs", 2, ARMVFP2, 20, 27, 0xEF, 0, 11, 0xA10 },
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{"vmovbcr", 4, ARMVFP2, 24, 27, 0xE, 20, 20, 1, 8, 11, 0xB, 0,4,0x10},
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{ "vmovbcr", 4, ARMVFP2, 24, 27, 0xE, 20, 20, 1, 8, 11, 0xB, 0, 4, 0x10 },
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{"vmovbrrss", 3, ARMVFP2, 21, 27, 0x62, 8, 11, 0xA, 4, 4, 1},
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{ "vmovbrrss", 3, ARMVFP2, 21, 27, 0x62, 8, 11, 0xA, 4, 4, 1 },
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{"vmovbrrd", 3, ARMVFP2, 21, 27, 0x62, 6, 11, 0x2C, 4, 4, 1},
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{ "vmovbrrd", 3, ARMVFP2, 21, 27, 0x62, 6, 11, 0x2C, 4, 4, 1 },
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{"vstr", 3, ARMVFP2, 24, 27, 0xD, 20, 21, 0, 9, 11,5},
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{ "vstr", 3, ARMVFP2, 24, 27, 0xD, 20, 21, 0, 9, 11, 5 },
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{"vpush", 3, ARMVFP2, 23, 27, 0x1A, 16, 21, 0x2D, 9, 11,5},
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{ "vpush", 3, ARMVFP2, 23, 27, 0x1A, 16, 21, 0x2D, 9, 11, 5 },
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{"vstm", 3, ARMVFP2, 25, 27, 0x6, 20, 20, 0, 9, 11,5},
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{ "vstm", 3, ARMVFP2, 25, 27, 0x6, 20, 20, 0, 9, 11, 5 },
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{"vpop", 3, ARMVFP2, 23, 27, 0x19, 16, 21, 0x3D, 9, 11,5},
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{ "vpop", 3, ARMVFP2, 23, 27, 0x19, 16, 21, 0x3D, 9, 11, 5 },
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{"vldr", 3, ARMVFP2, 24, 27, 0xD, 20, 21, 1, 9, 11,5},
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{ "vldr", 3, ARMVFP2, 24, 27, 0xD, 20, 21, 1, 9, 11, 5 },
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{"vldm", 3, ARMVFP2, 25, 27, 0x6, 20, 20, 1, 9, 11,5},
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{ "vldm", 3, ARMVFP2, 25, 27, 0x6, 20, 20, 1, 9, 11, 5 },
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{"srs" , 4 , 6 , 25, 31, 0x0000007c, 22, 22, 0x00000001, 16, 20, 0x0000000d, 8, 11, 0x00000005},
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{ "srs", 4, 6, 25, 31, 0x0000007c, 22, 22, 0x00000001, 16, 20, 0x0000000d, 8, 11, 0x00000005 },
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{"rfe" , 4 , 6 , 25, 31, 0x0000007c, 22, 22, 0x00000000, 20, 20, 0x00000001, 8, 11, 0x0000000a},
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{ "rfe", 4, 6, 25, 31, 0x0000007c, 22, 22, 0x00000000, 20, 20, 0x00000001, 8, 11, 0x0000000a },
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{"bkpt" , 2 , 3 , 20, 31, 0x00000e12, 4, 7, 0x00000007},
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{ "bkpt", 2, 3, 20, 31, 0x00000e12, 4, 7, 0x00000007 },
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{"blx" , 1 , 3 , 25, 31, 0x0000007d},
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{ "blx", 1, 3, 25, 31, 0x0000007d },
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{"cps" , 3 , 6 , 20, 31, 0x00000f10, 16, 16, 0x00000000, 5, 5, 0x00000000},
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{ "cps", 3, 6, 20, 31, 0x00000f10, 16, 16, 0x00000000, 5, 5, 0x00000000 },
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{"pld" , 4 , 4 , 26, 31, 0x0000003d, 24, 24, 0x00000001, 20, 22, 0x00000005, 12, 15, 0x0000000f},
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{ "pld", 4, 4, 26, 31, 0x0000003d, 24, 24, 0x00000001, 20, 22, 0x00000005, 12, 15, 0x0000000f },
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{"setend" , 2 , 6 , 16, 31, 0x0000f101, 4, 7, 0x00000000},
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{ "setend", 2, 6, 16, 31, 0x0000f101, 4, 7, 0x00000000 },
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{"clrex" , 1 , 6 , 0, 31, 0xf57ff01f},
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{ "clrex", 1, 6, 0, 31, 0xf57ff01f },
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{"rev16" , 2 , 6 , 16, 27, 0x000006bf, 4, 11, 0x000000fb},
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{ "rev16", 2, 6, 16, 27, 0x000006bf, 4, 11, 0x000000fb },
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{"usad8" , 3 , 6 , 20, 27, 0x00000078, 12, 15, 0x0000000f, 4, 7, 0x00000001},
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{ "usad8", 3, 6, 20, 27, 0x00000078, 12, 15, 0x0000000f, 4, 7, 0x00000001 },
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{"sxtb" , 2 , 6 , 16, 27, 0x000006af, 4, 7, 0x00000007},
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{ "sxtb", 2, 6, 16, 27, 0x000006af, 4, 7, 0x00000007 },
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{"uxtb" , 2 , 6 , 16, 27, 0x000006ef, 4, 7, 0x00000007},
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{ "uxtb", 2, 6, 16, 27, 0x000006ef, 4, 7, 0x00000007 },
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{"sxth" , 2 , 6 , 16, 27, 0x000006bf, 4, 7, 0x00000007},
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{ "sxth", 2, 6, 16, 27, 0x000006bf, 4, 7, 0x00000007 },
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{"sxtb16" , 2 , 6 , 16, 27, 0x0000068f, 4, 7, 0x00000007},
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{ "sxtb16", 2, 6, 16, 27, 0x0000068f, 4, 7, 0x00000007 },
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{"uxth" , 2 , 6 , 16, 27, 0x000006ff, 4, 7, 0x00000007},
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{ "uxth", 2, 6, 16, 27, 0x000006ff, 4, 7, 0x00000007 },
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{"uxtb16" , 2 , 6 , 16, 27, 0x000006cf, 4, 7, 0x00000007},
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{ "uxtb16", 2, 6, 16, 27, 0x000006cf, 4, 7, 0x00000007 },
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{"cpy" , 2 , 6 , 20, 27, 0x0000001a, 4, 11, 0x00000000},
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{ "cpy", 2, 6, 20, 27, 0x0000001a, 4, 11, 0x00000000 },
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{"uxtab" , 2 , 6 , 20, 27, 0x0000006e, 4, 9, 0x00000007},
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{ "uxtab", 2, 6, 20, 27, 0x0000006e, 4, 9, 0x00000007 },
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{"ssub8" , 2 , 6 , 20, 27, 0x00000061, 4, 7, 0x0000000f},
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{ "ssub8", 2, 6, 20, 27, 0x00000061, 4, 7, 0x0000000f },
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{"shsub8" , 2 , 6 , 20, 27, 0x00000063, 4, 7, 0x0000000f},
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{ "shsub8", 2, 6, 20, 27, 0x00000063, 4, 7, 0x0000000f },
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{"ssubaddx" , 2 , 6 , 20, 27, 0x00000061, 4, 7, 0x00000005},
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{ "ssubaddx", 2, 6, 20, 27, 0x00000061, 4, 7, 0x00000005 },
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{"strex" , 2 , 6 , 20, 27, 0x00000018, 4, 7, 0x00000009},
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{ "strex", 2, 6, 20, 27, 0x00000018, 4, 7, 0x00000009 },
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{"strexb" , 2 , 7 , 20, 27, 0x0000001c, 4, 7, 0x00000009},
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{ "strexb", 2, 7, 20, 27, 0x0000001c, 4, 7, 0x00000009 },
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{"swp" , 2 , 0 , 20, 27, 0x00000010, 4, 7, 0x00000009},
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{ "swp", 2, 0, 20, 27, 0x00000010, 4, 7, 0x00000009 },
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{"swpb" , 2 , 0 , 20, 27, 0x00000014, 4, 7, 0x00000009},
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{ "swpb", 2, 0, 20, 27, 0x00000014, 4, 7, 0x00000009 },
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{"ssub16" , 2 , 6 , 20, 27, 0x00000061, 4, 7, 0x00000007},
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{ "ssub16", 2, 6, 20, 27, 0x00000061, 4, 7, 0x00000007 },
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{"ssat16" , 2 , 6 , 20, 27, 0x0000006a, 4, 7, 0x00000003},
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{ "ssat16", 2, 6, 20, 27, 0x0000006a, 4, 7, 0x00000003 },
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{"shsubaddx" , 2 , 6 , 20, 27, 0x00000063, 4, 7, 0x00000005},
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{ "shsubaddx", 2, 6, 20, 27, 0x00000063, 4, 7, 0x00000005 },
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{"qsubaddx" , 2 , 6 , 20, 27, 0x00000062, 4, 7, 0x00000005},
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{ "qsubaddx", 2, 6, 20, 27, 0x00000062, 4, 7, 0x00000005 },
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{"shaddsubx" , 2 , 6 , 20, 27, 0x00000063, 4, 7, 0x00000003},
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{ "shaddsubx", 2, 6, 20, 27, 0x00000063, 4, 7, 0x00000003 },
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{"shadd8" , 2 , 6 , 20, 27, 0x00000063, 4, 7, 0x00000009},
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{ "shadd8", 2, 6, 20, 27, 0x00000063, 4, 7, 0x00000009 },
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{"shadd16" , 2 , 6 , 20, 27, 0x00000063, 4, 7, 0x00000001},
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{ "shadd16", 2, 6, 20, 27, 0x00000063, 4, 7, 0x00000001 },
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{"sel" , 2 , 6 , 20, 27, 0x00000068, 4, 7, 0x0000000b},
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{ "sel", 2, 6, 20, 27, 0x00000068, 4, 7, 0x0000000b },
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{"saddsubx" , 2 , 6 , 20, 27, 0x00000061, 4, 7, 0x00000003},
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{ "saddsubx", 2, 6, 20, 27, 0x00000061, 4, 7, 0x00000003 },
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{"sadd8" , 2 , 6 , 20, 27, 0x00000061, 4, 7, 0x00000009},
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{ "sadd8", 2, 6, 20, 27, 0x00000061, 4, 7, 0x00000009 },
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{"sadd16" , 2 , 6 , 20, 27, 0x00000061, 4, 7, 0x00000001},
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{ "sadd16", 2, 6, 20, 27, 0x00000061, 4, 7, 0x00000001 },
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{"shsub16" , 2 , 6 , 20, 27, 0x00000063, 4, 7, 0x00000007},
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{ "shsub16", 2, 6, 20, 27, 0x00000063, 4, 7, 0x00000007 },
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{"umaal" , 2 , 6 , 20, 27, 0x00000004, 4, 7, 0x00000009},
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{ "umaal", 2, 6, 20, 27, 0x00000004, 4, 7, 0x00000009 },
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{"uxtab16" , 2 , 6 , 20, 27, 0x0000006c, 4, 7, 0x00000007},
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{ "uxtab16", 2, 6, 20, 27, 0x0000006c, 4, 7, 0x00000007 },
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{"usubaddx" , 2 , 6 , 20, 27, 0x00000065, 4, 7, 0x00000005},
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{ "usubaddx", 2, 6, 20, 27, 0x00000065, 4, 7, 0x00000005 },
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{"usub8" , 2 , 6 , 20, 27, 0x00000065, 4, 7, 0x0000000f},
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{ "usub8", 2, 6, 20, 27, 0x00000065, 4, 7, 0x0000000f },
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{"usub16" , 2 , 6 , 20, 27, 0x00000065, 4, 7, 0x00000007},
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{ "usub16", 2, 6, 20, 27, 0x00000065, 4, 7, 0x00000007 },
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{"usat16" , 2 , 6 , 20, 27, 0x0000006e, 4, 7, 0x00000003},
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{ "usat16", 2, 6, 20, 27, 0x0000006e, 4, 7, 0x00000003 },
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{"usada8" , 2 , 6 , 20, 27, 0x00000078, 4, 7, 0x00000001},
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{ "usada8", 2, 6, 20, 27, 0x00000078, 4, 7, 0x00000001 },
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{"uqsubaddx" , 2 , 6 , 20, 27, 0x00000066, 4, 7, 0x00000005},
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{ "uqsubaddx", 2, 6, 20, 27, 0x00000066, 4, 7, 0x00000005 },
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{"uqsub8" , 2 , 6 , 20, 27, 0x00000066, 4, 7, 0x0000000f},
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{ "uqsub8", 2, 6, 20, 27, 0x00000066, 4, 7, 0x0000000f },
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{"uqsub16" , 2 , 6 , 20, 27, 0x00000066, 4, 7, 0x00000007},
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{ "uqsub16", 2, 6, 20, 27, 0x00000066, 4, 7, 0x00000007 },
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{"uqaddsubx" , 2 , 6 , 20, 27, 0x00000066, 4, 7, 0x00000003},
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{ "uqaddsubx", 2, 6, 20, 27, 0x00000066, 4, 7, 0x00000003 },
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{"uqadd8" , 2 , 6 , 20, 27, 0x00000066, 4, 7, 0x00000009},
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{ "uqadd8", 2, 6, 20, 27, 0x00000066, 4, 7, 0x00000009 },
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{"uqadd16" , 2 , 6 , 20, 27, 0x00000066, 4, 7, 0x00000001},
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{ "uqadd16", 2, 6, 20, 27, 0x00000066, 4, 7, 0x00000001 },
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{"sxtab" , 2 , 6 , 20, 27, 0x0000006a, 4, 7, 0x00000007},
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{ "sxtab", 2, 6, 20, 27, 0x0000006a, 4, 7, 0x00000007 },
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{"uhsubaddx" , 2 , 6 , 20, 27, 0x00000067, 4, 7, 0x00000005},
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{ "uhsubaddx", 2, 6, 20, 27, 0x00000067, 4, 7, 0x00000005 },
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{"uhsub8" , 2 , 6 , 20, 27, 0x00000067, 4, 7, 0x0000000f},
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{ "uhsub8", 2, 6, 20, 27, 0x00000067, 4, 7, 0x0000000f },
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{"uhsub16" , 2 , 6 , 20, 27, 0x00000067, 4, 7, 0x00000007},
|
{ "uhsub16", 2, 6, 20, 27, 0x00000067, 4, 7, 0x00000007 },
|
||||||
{"uhaddsubx" , 2 , 6 , 20, 27, 0x00000067, 4, 7, 0x00000003},
|
{ "uhaddsubx", 2, 6, 20, 27, 0x00000067, 4, 7, 0x00000003 },
|
||||||
{"uhadd8" , 2 , 6 , 20, 27, 0x00000067, 4, 7, 0x00000009},
|
{ "uhadd8", 2, 6, 20, 27, 0x00000067, 4, 7, 0x00000009 },
|
||||||
{"uhadd16" , 2 , 6 , 20, 27, 0x00000067, 4, 7, 0x00000001},
|
{ "uhadd16", 2, 6, 20, 27, 0x00000067, 4, 7, 0x00000001 },
|
||||||
{"uaddsubx" , 2 , 6 , 20, 27, 0x00000065, 4, 7, 0x00000003},
|
{ "uaddsubx", 2, 6, 20, 27, 0x00000065, 4, 7, 0x00000003 },
|
||||||
{"uadd8" , 2 , 6 , 20, 27, 0x00000065, 4, 7, 0x00000009},
|
{ "uadd8", 2, 6, 20, 27, 0x00000065, 4, 7, 0x00000009 },
|
||||||
{"uadd16" , 2 , 6 , 20, 27, 0x00000065, 4, 7, 0x00000001},
|
{ "uadd16", 2, 6, 20, 27, 0x00000065, 4, 7, 0x00000001 },
|
||||||
{"sxtah" , 2 , 6 , 20, 27, 0x0000006b, 4, 7, 0x00000007},
|
{ "sxtah", 2, 6, 20, 27, 0x0000006b, 4, 7, 0x00000007 },
|
||||||
{"sxtab16" , 2 , 6 , 20, 27, 0x00000068, 4, 7, 0x00000007},
|
{ "sxtab16", 2, 6, 20, 27, 0x00000068, 4, 7, 0x00000007 },
|
||||||
{"qadd8" , 2 , 6 , 20, 27, 0x00000062, 4, 7, 0x00000009},
|
{ "qadd8", 2, 6, 20, 27, 0x00000062, 4, 7, 0x00000009 },
|
||||||
{"bxj" , 2 , 5 , 20, 27, 0x00000012, 4, 7, 0x00000002},
|
{ "bxj", 2, 5, 20, 27, 0x00000012, 4, 7, 0x00000002 },
|
||||||
{"clz" , 2 , 3 , 20, 27, 0x00000016, 4, 7, 0x00000001},
|
{ "clz", 2, 3, 20, 27, 0x00000016, 4, 7, 0x00000001 },
|
||||||
{"uxtah" , 2 , 6 , 20, 27, 0x0000006f, 4, 7, 0x00000007},
|
{ "uxtah", 2, 6, 20, 27, 0x0000006f, 4, 7, 0x00000007 },
|
||||||
{"bx" , 2 , 2 , 20, 27, 0x00000012, 4, 7, 0x00000001},
|
{ "bx", 2, 2, 20, 27, 0x00000012, 4, 7, 0x00000001 },
|
||||||
{"rev" , 2 , 6 , 20, 27, 0x0000006b, 4, 7, 0x00000003},
|
{ "rev", 2, 6, 20, 27, 0x0000006b, 4, 7, 0x00000003 },
|
||||||
{"blx" , 2 , 3 , 20, 27, 0x00000012, 4, 7, 0x00000003},
|
{ "blx", 2, 3, 20, 27, 0x00000012, 4, 7, 0x00000003 },
|
||||||
{"revsh" , 2 , 6 , 20, 27, 0x0000006f, 4, 7, 0x0000000b},
|
{ "revsh", 2, 6, 20, 27, 0x0000006f, 4, 7, 0x0000000b },
|
||||||
{"qadd" , 2 , 4 , 20, 27, 0x00000010, 4, 7, 0x00000005},
|
{ "qadd", 2, 4, 20, 27, 0x00000010, 4, 7, 0x00000005 },
|
||||||
{"qadd16" , 2 , 6 , 20, 27, 0x00000062, 4, 7, 0x00000001},
|
{ "qadd16", 2, 6, 20, 27, 0x00000062, 4, 7, 0x00000001 },
|
||||||
{"qaddsubx" , 2 , 6 , 20, 27, 0x00000062, 4, 7, 0x00000003},
|
{ "qaddsubx", 2, 6, 20, 27, 0x00000062, 4, 7, 0x00000003 },
|
||||||
{"ldrex" , 2 , 0 , 20, 27, 0x00000019, 4, 7, 0x00000009},
|
{ "ldrex", 2, 0, 20, 27, 0x00000019, 4, 7, 0x00000009 },
|
||||||
{"qdadd" , 2 , 4 , 20, 27, 0x00000014, 4, 7, 0x00000005},
|
{ "qdadd", 2, 4, 20, 27, 0x00000014, 4, 7, 0x00000005 },
|
||||||
{"qdsub" , 2 , 4 , 20, 27, 0x00000016, 4, 7, 0x00000005},
|
{ "qdsub", 2, 4, 20, 27, 0x00000016, 4, 7, 0x00000005 },
|
||||||
{"qsub" , 2 , 4 , 20, 27, 0x00000012, 4, 7, 0x00000005},
|
{ "qsub", 2, 4, 20, 27, 0x00000012, 4, 7, 0x00000005 },
|
||||||
{"ldrexb" , 2 , 7 , 20, 27, 0x0000001d, 4, 7, 0x00000009},
|
{ "ldrexb", 2, 7, 20, 27, 0x0000001d, 4, 7, 0x00000009 },
|
||||||
{"qsub8" , 2 , 6 , 20, 27, 0x00000062, 4, 7, 0x0000000f},
|
{ "qsub8", 2, 6, 20, 27, 0x00000062, 4, 7, 0x0000000f },
|
||||||
{"qsub16" , 2 , 6 , 20, 27, 0x00000062, 4, 7, 0x00000007},
|
{ "qsub16", 2, 6, 20, 27, 0x00000062, 4, 7, 0x00000007 },
|
||||||
{"smuad" , 4 , 6 , 20, 27, 0x00000070, 12, 15, 0x0000000f, 6, 7, 0x00000000, 4, 4, 0x00000001},
|
{ "smuad", 4, 6, 20, 27, 0x00000070, 12, 15, 0x0000000f, 6, 7, 0x00000000, 4, 4, 0x00000001 },
|
||||||
{"smmul" , 4 , 6 , 20, 27, 0x00000075, 12, 15, 0x0000000f, 6, 7, 0x00000000, 4, 4, 0x00000001},
|
{ "smmul", 4, 6, 20, 27, 0x00000075, 12, 15, 0x0000000f, 6, 7, 0x00000000, 4, 4, 0x00000001 },
|
||||||
{"smusd" , 4 , 6 , 20, 27, 0x00000070, 12, 15, 0x0000000f, 6, 7, 0x00000001, 4, 4, 0x00000001},
|
{ "smusd", 4, 6, 20, 27, 0x00000070, 12, 15, 0x0000000f, 6, 7, 0x00000001, 4, 4, 0x00000001 },
|
||||||
{"smlsd" , 3 , 6 , 20, 27, 0x00000070, 6, 7, 0x00000001, 4, 4, 0x00000001},
|
{ "smlsd", 3, 6, 20, 27, 0x00000070, 6, 7, 0x00000001, 4, 4, 0x00000001 },
|
||||||
{"smlsld" , 3 , 6 , 20, 27, 0x00000074, 6, 7, 0x00000001, 4, 4, 0x00000001},
|
{ "smlsld", 3, 6, 20, 27, 0x00000074, 6, 7, 0x00000001, 4, 4, 0x00000001 },
|
||||||
{"smmla" , 3 , 6 , 20, 27, 0x00000075, 6, 7, 0x00000000, 4, 4, 0x00000001},
|
{ "smmla", 3, 6, 20, 27, 0x00000075, 6, 7, 0x00000000, 4, 4, 0x00000001 },
|
||||||
{"smmls" , 3 , 6 , 20, 27, 0x00000075, 6, 7, 0x00000003, 4, 4, 0x00000001},
|
{ "smmls", 3, 6, 20, 27, 0x00000075, 6, 7, 0x00000003, 4, 4, 0x00000001 },
|
||||||
{"smlald" , 3 , 6 , 20, 27, 0x00000074, 6, 7, 0x00000000, 4, 4, 0x00000001},
|
{ "smlald", 3, 6, 20, 27, 0x00000074, 6, 7, 0x00000000, 4, 4, 0x00000001 },
|
||||||
{"smlad" , 3 , 6 , 20, 27, 0x00000070, 6, 7, 0x00000000, 4, 4, 0x00000001},
|
{ "smlad", 3, 6, 20, 27, 0x00000070, 6, 7, 0x00000000, 4, 4, 0x00000001 },
|
||||||
{"smlaw" , 3 , 4 , 20, 27, 0x00000012, 7, 7, 0x00000001, 4, 5, 0x00000000},
|
{ "smlaw", 3, 4, 20, 27, 0x00000012, 7, 7, 0x00000001, 4, 5, 0x00000000 },
|
||||||
{"smulw" , 3 , 4 , 20, 27, 0x00000012, 7, 7, 0x00000001, 4, 5, 0x00000002},
|
{ "smulw", 3, 4, 20, 27, 0x00000012, 7, 7, 0x00000001, 4, 5, 0x00000002 },
|
||||||
{"pkhtb" , 2 , 6 , 20, 27, 0x00000068, 4, 6, 0x00000005},
|
{ "pkhtb", 2, 6, 20, 27, 0x00000068, 4, 6, 0x00000005 },
|
||||||
{"pkhbt" , 2 , 6 , 20, 27, 0x00000068, 4, 6, 0x00000001},
|
{ "pkhbt", 2, 6, 20, 27, 0x00000068, 4, 6, 0x00000001 },
|
||||||
{"smul" , 3 , 4 , 20, 27, 0x00000016, 7, 7, 0x00000001, 4, 4, 0x00000000},
|
{ "smul", 3, 4, 20, 27, 0x00000016, 7, 7, 0x00000001, 4, 4, 0x00000000 },
|
||||||
{"smlalxy" , 3 , 4 , 20, 27, 0x00000014, 7, 7, 0x00000001, 4, 4, 0x00000000},
|
{ "smlalxy", 3, 4, 20, 27, 0x00000014, 7, 7, 0x00000001, 4, 4, 0x00000000 },
|
||||||
// {"smlal" , 2 , 4 , 21, 27, 0x00000007, 4, 7, 0x00000009},
|
// {"smlal" , 2 , 4 , 21, 27, 0x00000007, 4, 7, 0x00000009},
|
||||||
{"smla" , 3 , 4 , 20, 27, 0x00000010, 7, 7, 0x00000001, 4, 4, 0x00000000},
|
{ "smla", 3, 4, 20, 27, 0x00000010, 7, 7, 0x00000001, 4, 4, 0x00000000 },
|
||||||
{"mcrr" , 1 , 6 , 20, 27, 0x000000c4},
|
{ "mcrr", 1, 6, 20, 27, 0x000000c4 },
|
||||||
{"mrrc" , 1 , 6 , 20, 27, 0x000000c5},
|
{ "mrrc", 1, 6, 20, 27, 0x000000c5 },
|
||||||
{"cmp" , 2 , 0 , 26, 27, 0x00000000, 20, 24, 0x00000015},
|
{ "cmp", 2, 0, 26, 27, 0x00000000, 20, 24, 0x00000015 },
|
||||||
{"tst" , 2 , 0 , 26, 27, 0x00000000, 20, 24, 0x00000011},
|
{ "tst", 2, 0, 26, 27, 0x00000000, 20, 24, 0x00000011 },
|
||||||
{"teq" , 2 , 0 , 26, 27, 0x00000000, 20, 24, 0x00000013},
|
{ "teq", 2, 0, 26, 27, 0x00000000, 20, 24, 0x00000013 },
|
||||||
{"cmn" , 2 , 0 , 26, 27, 0x00000000, 20, 24, 0x00000017},
|
{ "cmn", 2, 0, 26, 27, 0x00000000, 20, 24, 0x00000017 },
|
||||||
{"smull" , 2 , 0 , 21, 27, 0x00000006, 4, 7, 0x00000009},
|
{ "smull", 2, 0, 21, 27, 0x00000006, 4, 7, 0x00000009 },
|
||||||
{"umull" , 2 , 0 , 21, 27, 0x00000004, 4, 7, 0x00000009},
|
{ "umull", 2, 0, 21, 27, 0x00000004, 4, 7, 0x00000009 },
|
||||||
{"umlal" , 2 , 0 , 21, 27, 0x00000005, 4, 7, 0x00000009},
|
{ "umlal", 2, 0, 21, 27, 0x00000005, 4, 7, 0x00000009 },
|
||||||
{"smlal" , 2 , 0 , 21, 27, 0x00000007, 4, 7, 0x00000009},
|
{ "smlal", 2, 0, 21, 27, 0x00000007, 4, 7, 0x00000009 },
|
||||||
{"mul" , 2 , 0 , 21, 27, 0x00000000, 4, 7, 0x00000009},
|
{ "mul", 2, 0, 21, 27, 0x00000000, 4, 7, 0x00000009 },
|
||||||
{"mla" , 2 , 0 , 21, 27, 0x00000001, 4, 7, 0x00000009},
|
{ "mla", 2, 0, 21, 27, 0x00000001, 4, 7, 0x00000009 },
|
||||||
{"ssat" , 2 , 6 , 21, 27, 0x00000035, 4, 5, 0x00000001},
|
{ "ssat", 2, 6, 21, 27, 0x00000035, 4, 5, 0x00000001 },
|
||||||
{"usat" , 2 , 6 , 21, 27, 0x00000037, 4, 5, 0x00000001},
|
{ "usat", 2, 6, 21, 27, 0x00000037, 4, 5, 0x00000001 },
|
||||||
{"mrs" , 4 , 0 , 23, 27, 0x00000002, 20, 21, 0x00000000, 16, 19, 0x0000000f, 0, 11, 0x00000000},
|
{ "mrs", 4, 0, 23, 27, 0x00000002, 20, 21, 0x00000000, 16, 19, 0x0000000f, 0, 11, 0x00000000 },
|
||||||
{"msr" , 3 , 0 , 23, 27, 0x00000002, 20, 21, 0x00000002, 4, 7, 0x00000000},
|
{ "msr", 3, 0, 23, 27, 0x00000002, 20, 21, 0x00000002, 4, 7, 0x00000000 },
|
||||||
{"and" , 2 , 0 , 26, 27, 0x00000000, 21, 24, 0x00000000},
|
{ "and", 2, 0, 26, 27, 0x00000000, 21, 24, 0x00000000 },
|
||||||
{"bic" , 2 , 0 , 26, 27, 0x00000000, 21, 24, 0x0000000e},
|
{ "bic", 2, 0, 26, 27, 0x00000000, 21, 24, 0x0000000e },
|
||||||
{"ldm" , 3 , 0 , 25, 27, 0x00000004, 20, 22, 0x00000005, 15, 15, 0x00000000},
|
{ "ldm", 3, 0, 25, 27, 0x00000004, 20, 22, 0x00000005, 15, 15, 0x00000000 },
|
||||||
{"eor" , 2 , 0 , 26, 27, 0x00000000, 21, 24, 0x00000001},
|
{ "eor", 2, 0, 26, 27, 0x00000000, 21, 24, 0x00000001 },
|
||||||
{"add" , 2 , 0 , 26, 27, 0x00000000, 21, 24, 0x00000004},
|
{ "add", 2, 0, 26, 27, 0x00000000, 21, 24, 0x00000004 },
|
||||||
{"rsb" , 2 , 0 , 26, 27, 0x00000000, 21, 24, 0x00000003},
|
{ "rsb", 2, 0, 26, 27, 0x00000000, 21, 24, 0x00000003 },
|
||||||
{"rsc" , 2 , 0 , 26, 27, 0x00000000, 21, 24, 0x00000007},
|
{ "rsc", 2, 0, 26, 27, 0x00000000, 21, 24, 0x00000007 },
|
||||||
{"sbc" , 2 , 0 , 26, 27, 0x00000000, 21, 24, 0x00000006},
|
{ "sbc", 2, 0, 26, 27, 0x00000000, 21, 24, 0x00000006 },
|
||||||
{"adc" , 2 , 0 , 26, 27, 0x00000000, 21, 24, 0x00000005},
|
{ "adc", 2, 0, 26, 27, 0x00000000, 21, 24, 0x00000005 },
|
||||||
{"sub" , 2 , 0 , 26, 27, 0x00000000, 21, 24, 0x00000002},
|
{ "sub", 2, 0, 26, 27, 0x00000000, 21, 24, 0x00000002 },
|
||||||
{"orr" , 2 , 0 , 26, 27, 0x00000000, 21, 24, 0x0000000c},
|
{ "orr", 2, 0, 26, 27, 0x00000000, 21, 24, 0x0000000c },
|
||||||
{"mvn" , 2 , 0 , 26, 27, 0x00000000, 21, 24, 0x0000000f},
|
{ "mvn", 2, 0, 26, 27, 0x00000000, 21, 24, 0x0000000f },
|
||||||
{"mov" , 2 , 0 , 26, 27, 0x00000000, 21, 24, 0x0000000d},
|
{ "mov", 2, 0, 26, 27, 0x00000000, 21, 24, 0x0000000d },
|
||||||
{"stm" , 2 , 0 , 25, 27, 0x00000004, 20, 22, 0x00000004},
|
{ "stm", 2, 0, 25, 27, 0x00000004, 20, 22, 0x00000004 },
|
||||||
{"ldm" , 4 , 0 , 25, 27, 0x00000004, 22, 22, 0x00000001, 20, 20, 0x00000001, 15, 15, 0x00000001},
|
{ "ldm", 4, 0, 25, 27, 0x00000004, 22, 22, 0x00000001, 20, 20, 0x00000001, 15, 15, 0x00000001 },
|
||||||
{"ldrsh" , 3 , 2 , 25, 27, 0x00000000, 20, 20, 0x00000001, 4, 7, 0x0000000f},
|
{ "ldrsh", 3, 2, 25, 27, 0x00000000, 20, 20, 0x00000001, 4, 7, 0x0000000f },
|
||||||
{"stm" , 3 , 0 , 25, 27, 0x00000004, 22, 22, 0x00000000, 20, 20, 0x00000000},
|
{ "stm", 3, 0, 25, 27, 0x00000004, 22, 22, 0x00000000, 20, 20, 0x00000000 },
|
||||||
{"ldm" , 3 , 0 , 25, 27, 0x00000004, 22, 22, 0x00000000, 20, 20, 0x00000001},
|
{ "ldm", 3, 0, 25, 27, 0x00000004, 22, 22, 0x00000000, 20, 20, 0x00000001 },
|
||||||
{"ldrsb" , 3 , 2 , 25, 27, 0x00000000, 20, 20, 0x00000001, 4, 7, 0x0000000d},
|
{ "ldrsb", 3, 2, 25, 27, 0x00000000, 20, 20, 0x00000001, 4, 7, 0x0000000d },
|
||||||
{"strd" , 3 , 4 , 25, 27, 0x00000000, 20, 20, 0x00000000, 4, 7, 0x0000000f},
|
{ "strd", 3, 4, 25, 27, 0x00000000, 20, 20, 0x00000000, 4, 7, 0x0000000f },
|
||||||
{"ldrh" , 3 , 0 , 25, 27, 0x00000000, 20, 20, 0x00000001, 4, 7, 0x0000000b},
|
{ "ldrh", 3, 0, 25, 27, 0x00000000, 20, 20, 0x00000001, 4, 7, 0x0000000b },
|
||||||
{"strh" , 3 , 0 , 25, 27, 0x00000000, 20, 20, 0x00000000, 4, 7, 0x0000000b},
|
{ "strh", 3, 0, 25, 27, 0x00000000, 20, 20, 0x00000000, 4, 7, 0x0000000b },
|
||||||
{"ldrd" , 3 , 4 , 25, 27, 0x00000000, 20, 20, 0x00000000, 4, 7, 0x0000000d},
|
{ "ldrd", 3, 4, 25, 27, 0x00000000, 20, 20, 0x00000000, 4, 7, 0x0000000d },
|
||||||
{"strt" , 3 , 0 , 26, 27, 0x00000001, 24, 24, 0x00000000, 20, 22, 0x00000002},
|
{ "strt", 3, 0, 26, 27, 0x00000001, 24, 24, 0x00000000, 20, 22, 0x00000002 },
|
||||||
{"strbt" , 3 , 0 , 26, 27, 0x00000001, 24, 24, 0x00000000, 20, 22, 0x00000006},
|
{ "strbt", 3, 0, 26, 27, 0x00000001, 24, 24, 0x00000000, 20, 22, 0x00000006 },
|
||||||
{"ldrbt" , 3 , 0 , 26, 27, 0x00000001, 24, 24, 0x00000000, 20, 22, 0x00000007},
|
{ "ldrbt", 3, 0, 26, 27, 0x00000001, 24, 24, 0x00000000, 20, 22, 0x00000007 },
|
||||||
{"ldrt" , 3 , 0 , 26, 27, 0x00000001, 24, 24, 0x00000000, 20, 22, 0x00000003},
|
{ "ldrt", 3, 0, 26, 27, 0x00000001, 24, 24, 0x00000000, 20, 22, 0x00000003 },
|
||||||
{"mrc" , 3 , 6 , 24, 27, 0x0000000e, 20, 20, 0x00000001, 4, 4, 0x00000001},
|
{ "mrc", 3, 6, 24, 27, 0x0000000e, 20, 20, 0x00000001, 4, 4, 0x00000001 },
|
||||||
{"mcr" , 3 , 0 , 24, 27, 0x0000000e, 20, 20, 0x00000000, 4, 4, 0x00000001},
|
{ "mcr", 3, 0, 24, 27, 0x0000000e, 20, 20, 0x00000000, 4, 4, 0x00000001 },
|
||||||
{"msr" , 2 , 0 , 23, 27, 0x00000006, 20, 21, 0x00000002},
|
{ "msr", 2, 0, 23, 27, 0x00000006, 20, 21, 0x00000002 },
|
||||||
{"ldrb" , 3 , 0 , 26, 27, 0x00000001, 22, 22, 0x00000001, 20, 20, 0x00000001},
|
{ "ldrb", 3, 0, 26, 27, 0x00000001, 22, 22, 0x00000001, 20, 20, 0x00000001 },
|
||||||
{"strb" , 3 , 0 , 26, 27, 0x00000001, 22, 22, 0x00000001, 20, 20, 0x00000000},
|
{ "strb", 3, 0, 26, 27, 0x00000001, 22, 22, 0x00000001, 20, 20, 0x00000000 },
|
||||||
{"ldr" , 4 , 0 , 28, 31, 0x0000000e, 26, 27, 0x00000001, 22, 22, 0x00000000, 20, 20, 0x00000001},
|
{ "ldr", 4, 0, 28, 31, 0x0000000e, 26, 27, 0x00000001, 22, 22, 0x00000000, 20, 20, 0x00000001 },
|
||||||
{"ldrcond" , 3 , 0 , 26, 27, 0x00000001, 22, 22, 0x00000000, 20, 20, 0x00000001},
|
{ "ldrcond", 3, 0, 26, 27, 0x00000001, 22, 22, 0x00000000, 20, 20, 0x00000001 },
|
||||||
{"str" , 3 , 0 , 26, 27, 0x00000001, 22, 22, 0x00000000, 20, 20, 0x00000000},
|
{ "str", 3, 0, 26, 27, 0x00000001, 22, 22, 0x00000000, 20, 20, 0x00000000 },
|
||||||
{"cdp" , 2 , 0 , 24, 27, 0x0000000e, 4, 4, 0x00000000},
|
{ "cdp", 2, 0, 24, 27, 0x0000000e, 4, 4, 0x00000000 },
|
||||||
{"stc" , 2 , 0 , 25, 27, 0x00000006, 20, 20, 0x00000000},
|
{ "stc", 2, 0, 25, 27, 0x00000006, 20, 20, 0x00000000 },
|
||||||
{"ldc" , 2 , 0 , 25, 27, 0x00000006, 20, 20, 0x00000001},
|
{ "ldc", 2, 0, 25, 27, 0x00000006, 20, 20, 0x00000001 },
|
||||||
{"swi" , 1 , 0 , 24, 27, 0x0000000f},
|
{ "swi", 1, 0, 24, 27, 0x0000000f },
|
||||||
{"bbl" , 1 , 0 , 25, 27, 0x00000005},
|
{ "bbl", 1, 0, 25, 27, 0x00000005 },
|
||||||
};
|
};
|
||||||
|
|
||||||
const ISEITEM arm_exclusion_code[] = {
|
const ISEITEM arm_exclusion_code[] = {
|
||||||
{"vmla", 0, ARMVFP2, 0},
|
{ "vmla", 0, ARMVFP2, 0 },
|
||||||
{"vmls", 0, ARMVFP2, 0},
|
{ "vmls", 0, ARMVFP2, 0 },
|
||||||
{"vnmla", 0, ARMVFP2, 0},
|
{ "vnmla", 0, ARMVFP2, 0 },
|
||||||
{"vnmla", 0, ARMVFP2, 0},
|
{ "vnmla", 0, ARMVFP2, 0 },
|
||||||
{"vnmls", 0, ARMVFP2, 0},
|
{ "vnmls", 0, ARMVFP2, 0 },
|
||||||
{"vnmul", 0, ARMVFP2, 0},
|
{ "vnmul", 0, ARMVFP2, 0 },
|
||||||
{"vmul", 0, ARMVFP2, 0},
|
{ "vmul", 0, ARMVFP2, 0 },
|
||||||
{"vadd", 0, ARMVFP2, 0},
|
{ "vadd", 0, ARMVFP2, 0 },
|
||||||
{"vsub", 0, ARMVFP2, 0},
|
{ "vsub", 0, ARMVFP2, 0 },
|
||||||
{"vdiv", 0, ARMVFP2, 0},
|
{ "vdiv", 0, ARMVFP2, 0 },
|
||||||
{"vmov(i)", 0, ARMVFP3, 0},
|
{ "vmov(i)", 0, ARMVFP3, 0 },
|
||||||
{"vmov(r)", 0, ARMVFP3, 0},
|
{ "vmov(r)", 0, ARMVFP3, 0 },
|
||||||
{"vabs", 0, ARMVFP2, 0},
|
{ "vabs", 0, ARMVFP2, 0 },
|
||||||
{"vneg", 0, ARMVFP2, 0},
|
{ "vneg", 0, ARMVFP2, 0 },
|
||||||
{"vsqrt", 0, ARMVFP2, 0},
|
{ "vsqrt", 0, ARMVFP2, 0 },
|
||||||
{"vcmp", 0, ARMVFP2, 0},
|
{ "vcmp", 0, ARMVFP2, 0 },
|
||||||
{"vcmp2", 0, ARMVFP2, 0},
|
{ "vcmp2", 0, ARMVFP2, 0 },
|
||||||
{"vcvt(bff)", 0, ARMVFP3, 4, 4, 1},
|
{ "vcvt(bff)", 0, ARMVFP3, 4, 4, 1 },
|
||||||
{"vcvt(bds)", 0, ARMVFP2, 0},
|
{ "vcvt(bds)", 0, ARMVFP2, 0 },
|
||||||
{"vcvt(bfi)", 0, ARMVFP2, 0},
|
{ "vcvt(bfi)", 0, ARMVFP2, 0 },
|
||||||
{"vmovbrs", 0, ARMVFP2, 0},
|
{ "vmovbrs", 0, ARMVFP2, 0 },
|
||||||
{"vmsr", 0, ARMVFP2, 0},
|
{ "vmsr", 0, ARMVFP2, 0 },
|
||||||
{"vmovbrc", 0, ARMVFP2, 0},
|
{ "vmovbrc", 0, ARMVFP2, 0 },
|
||||||
{"vmrs", 0, ARMVFP2, 0},
|
{ "vmrs", 0, ARMVFP2, 0 },
|
||||||
{"vmovbcr", 0, ARMVFP2, 0},
|
{ "vmovbcr", 0, ARMVFP2, 0 },
|
||||||
{"vmovbrrss", 0, ARMVFP2, 0},
|
{ "vmovbrrss", 0, ARMVFP2, 0 },
|
||||||
{"vmovbrrd", 0, ARMVFP2, 0},
|
{ "vmovbrrd", 0, ARMVFP2, 0 },
|
||||||
{"vstr", 0, ARMVFP2, 0},
|
{ "vstr", 0, ARMVFP2, 0 },
|
||||||
{"vpush", 0, ARMVFP2, 0},
|
{ "vpush", 0, ARMVFP2, 0 },
|
||||||
{"vstm", 0, ARMVFP2, 0},
|
{ "vstm", 0, ARMVFP2, 0 },
|
||||||
{"vpop", 0, ARMVFP2, 0},
|
{ "vpop", 0, ARMVFP2, 0 },
|
||||||
{"vldr", 0, ARMVFP2, 0},
|
{ "vldr", 0, ARMVFP2, 0 },
|
||||||
{"vldm", 0, ARMVFP2, 0},
|
{ "vldm", 0, ARMVFP2, 0 },
|
||||||
|
|
||||||
{"srs" , 0 , 6 , 0},
|
{ "srs", 0, 6, 0 },
|
||||||
{"rfe" , 0 , 6 , 0},
|
{ "rfe", 0, 6, 0 },
|
||||||
{"bkpt" , 0 , 3 , 0},
|
{ "bkpt", 0, 3, 0 },
|
||||||
{"blx" , 0 , 3 , 0},
|
{ "blx", 0, 3, 0 },
|
||||||
{"cps" , 0 , 6 , 0},
|
{ "cps", 0, 6, 0 },
|
||||||
{"pld" , 0 , 4 , 0},
|
{ "pld", 0, 4, 0 },
|
||||||
{"setend" , 0 , 6 , 0},
|
{ "setend", 0, 6, 0 },
|
||||||
{"clrex" , 0 , 6 , 0},
|
{ "clrex", 0, 6, 0 },
|
||||||
{"rev16" , 0 , 6 , 0},
|
{ "rev16", 0, 6, 0 },
|
||||||
{"usad8" , 0 , 6 , 0},
|
{ "usad8", 0, 6, 0 },
|
||||||
{"sxtb" , 0 , 6 , 0},
|
{ "sxtb", 0, 6, 0 },
|
||||||
{"uxtb" , 0 , 6 , 0},
|
{ "uxtb", 0, 6, 0 },
|
||||||
{"sxth" , 0 , 6 , 0},
|
{ "sxth", 0, 6, 0 },
|
||||||
{"sxtb16" , 0 , 6 , 0},
|
{ "sxtb16", 0, 6, 0 },
|
||||||
{"uxth" , 0 , 6 , 0},
|
{ "uxth", 0, 6, 0 },
|
||||||
{"uxtb16" , 0 , 6 , 0},
|
{ "uxtb16", 0, 6, 0 },
|
||||||
{"cpy" , 0 , 6 , 0},
|
{ "cpy", 0, 6, 0 },
|
||||||
{"uxtab" , 0 , 6 , 0},
|
{ "uxtab", 0, 6, 0 },
|
||||||
{"ssub8" , 0 , 6 , 0},
|
{ "ssub8", 0, 6, 0 },
|
||||||
{"shsub8" , 0 , 6 , 0},
|
{ "shsub8", 0, 6, 0 },
|
||||||
{"ssubaddx" , 0 , 6 , 0},
|
{ "ssubaddx", 0, 6, 0 },
|
||||||
{"strex" , 0 , 6 , 0},
|
{ "strex", 0, 6, 0 },
|
||||||
{"strexb" , 0 , 7 , 0},
|
{ "strexb", 0, 7, 0 },
|
||||||
{"swp" , 0 , 0 , 0},
|
{ "swp", 0, 0, 0 },
|
||||||
{"swpb" , 0 , 0 , 0},
|
{ "swpb", 0, 0, 0 },
|
||||||
{"ssub16" , 0 , 6 , 0},
|
{ "ssub16", 0, 6, 0 },
|
||||||
{"ssat16" , 0 , 6 , 0},
|
{ "ssat16", 0, 6, 0 },
|
||||||
{"shsubaddx" , 0 , 6 , 0},
|
{ "shsubaddx", 0, 6, 0 },
|
||||||
{"qsubaddx" , 0 , 6 , 0},
|
{ "qsubaddx", 0, 6, 0 },
|
||||||
{"shaddsubx" , 0 , 6 , 0},
|
{ "shaddsubx", 0, 6, 0 },
|
||||||
{"shadd8" , 0 , 6 , 0},
|
{ "shadd8", 0, 6, 0 },
|
||||||
{"shadd16" , 0 , 6 , 0},
|
{ "shadd16", 0, 6, 0 },
|
||||||
{"sel" , 0 , 6 , 0},
|
{ "sel", 0, 6, 0 },
|
||||||
{"saddsubx" , 0 , 6 , 0},
|
{ "saddsubx", 0, 6, 0 },
|
||||||
{"sadd8" , 0 , 6 , 0},
|
{ "sadd8", 0, 6, 0 },
|
||||||
{"sadd16" , 0 , 6 , 0},
|
{ "sadd16", 0, 6, 0 },
|
||||||
{"shsub16" , 0 , 6 , 0},
|
{ "shsub16", 0, 6, 0 },
|
||||||
{"umaal" , 0 , 6 , 0},
|
{ "umaal", 0, 6, 0 },
|
||||||
{"uxtab16" , 0 , 6 , 0},
|
{ "uxtab16", 0, 6, 0 },
|
||||||
{"usubaddx" , 0 , 6 , 0},
|
{ "usubaddx", 0, 6, 0 },
|
||||||
{"usub8" , 0 , 6 , 0},
|
{ "usub8", 0, 6, 0 },
|
||||||
{"usub16" , 0 , 6 , 0},
|
{ "usub16", 0, 6, 0 },
|
||||||
{"usat16" , 0 , 6 , 0},
|
{ "usat16", 0, 6, 0 },
|
||||||
{"usada8" , 0 , 6 , 0},
|
{ "usada8", 0, 6, 0 },
|
||||||
{"uqsubaddx" , 0 , 6 , 0},
|
{ "uqsubaddx", 0, 6, 0 },
|
||||||
{"uqsub8" , 0 , 6 , 0},
|
{ "uqsub8", 0, 6, 0 },
|
||||||
{"uqsub16" , 0 , 6 , 0},
|
{ "uqsub16", 0, 6, 0 },
|
||||||
{"uqaddsubx" , 0 , 6 , 0},
|
{ "uqaddsubx", 0, 6, 0 },
|
||||||
{"uqadd8" , 0 , 6 , 0},
|
{ "uqadd8", 0, 6, 0 },
|
||||||
{"uqadd16" , 0 , 6 , 0},
|
{ "uqadd16", 0, 6, 0 },
|
||||||
{"sxtab" , 0 , 6 , 0},
|
{ "sxtab", 0, 6, 0 },
|
||||||
{"uhsubaddx" , 0 , 6 , 0},
|
{ "uhsubaddx", 0, 6, 0 },
|
||||||
{"uhsub8" , 0 , 6 , 0},
|
{ "uhsub8", 0, 6, 0 },
|
||||||
{"uhsub16" , 0 , 6 , 0},
|
{ "uhsub16", 0, 6, 0 },
|
||||||
{"uhaddsubx" , 0 , 6 , 0},
|
{ "uhaddsubx", 0, 6, 0 },
|
||||||
{"uhadd8" , 0 , 6 , 0},
|
{ "uhadd8", 0, 6, 0 },
|
||||||
{"uhadd16" , 0 , 6 , 0},
|
{ "uhadd16", 0, 6, 0 },
|
||||||
{"uaddsubx" , 0 , 6 , 0},
|
{ "uaddsubx", 0, 6, 0 },
|
||||||
{"uadd8" , 0 , 6 , 0},
|
{ "uadd8", 0, 6, 0 },
|
||||||
{"uadd16" , 0 , 6 , 0},
|
{ "uadd16", 0, 6, 0 },
|
||||||
{"sxtah" , 0 , 6 , 0},
|
{ "sxtah", 0, 6, 0 },
|
||||||
{"sxtab16" , 0 , 6 , 0},
|
{ "sxtab16", 0, 6, 0 },
|
||||||
{"qadd8" , 0 , 6 , 0},
|
{ "qadd8", 0, 6, 0 },
|
||||||
{"bxj" , 0 , 5 , 0},
|
{ "bxj", 0, 5, 0 },
|
||||||
{"clz" , 0 , 3 , 0},
|
{ "clz", 0, 3, 0 },
|
||||||
{"uxtah" , 0 , 6 , 0},
|
{ "uxtah", 0, 6, 0 },
|
||||||
{"bx" , 0 , 2 , 0},
|
{ "bx", 0, 2, 0 },
|
||||||
{"rev" , 0 , 6 , 0},
|
{ "rev", 0, 6, 0 },
|
||||||
{"blx" , 0 , 3 , 0},
|
{ "blx", 0, 3, 0 },
|
||||||
{"revsh" , 0 , 6 , 0},
|
{ "revsh", 0, 6, 0 },
|
||||||
{"qadd" , 0 , 4 , 0},
|
{ "qadd", 0, 4, 0 },
|
||||||
{"qadd16" , 0 , 6 , 0},
|
{ "qadd16", 0, 6, 0 },
|
||||||
{"qaddsubx" , 0 , 6 , 0},
|
{ "qaddsubx", 0, 6, 0 },
|
||||||
{"ldrex" , 0 , 0 , 0},
|
{ "ldrex", 0, 0, 0 },
|
||||||
{"qdadd" , 0 , 4 , 0},
|
{ "qdadd", 0, 4, 0 },
|
||||||
{"qdsub" , 0 , 4 , 0},
|
{ "qdsub", 0, 4, 0 },
|
||||||
{"qsub" , 0 , 4 , 0},
|
{ "qsub", 0, 4, 0 },
|
||||||
{"ldrexb" , 0 , 7 , 0},
|
{ "ldrexb", 0, 7, 0 },
|
||||||
{"qsub8" , 0 , 6 , 0},
|
{ "qsub8", 0, 6, 0 },
|
||||||
{"qsub16" , 0 , 6 , 0},
|
{ "qsub16", 0, 6, 0 },
|
||||||
{"smuad" , 0 , 6 , 0},
|
{ "smuad", 0, 6, 0 },
|
||||||
{"smmul" , 0 , 6 , 0},
|
{ "smmul", 0, 6, 0 },
|
||||||
{"smusd" , 0 , 6 , 0},
|
{ "smusd", 0, 6, 0 },
|
||||||
{"smlsd" , 0 , 6 , 0},
|
{ "smlsd", 0, 6, 0 },
|
||||||
{"smlsld" , 0 , 6 , 0},
|
{ "smlsld", 0, 6, 0 },
|
||||||
{"smmla" , 0 , 6 , 0},
|
{ "smmla", 0, 6, 0 },
|
||||||
{"smmls" , 0 , 6 , 0},
|
{ "smmls", 0, 6, 0 },
|
||||||
{"smlald" , 0 , 6 , 0},
|
{ "smlald", 0, 6, 0 },
|
||||||
{"smlad" , 0 , 6 , 0},
|
{ "smlad", 0, 6, 0 },
|
||||||
{"smlaw" , 0 , 4 , 0},
|
{ "smlaw", 0, 4, 0 },
|
||||||
{"smulw" , 0 , 4 , 0},
|
{ "smulw", 0, 4, 0 },
|
||||||
{"pkhtb" , 0 , 6 , 0},
|
{ "pkhtb", 0, 6, 0 },
|
||||||
{"pkhbt" , 0 , 6 , 0},
|
{ "pkhbt", 0, 6, 0 },
|
||||||
{"smul" , 0 , 4 , 0},
|
{ "smul", 0, 4, 0 },
|
||||||
{"smlal" , 0 , 4 , 0},
|
{ "smlal", 0, 4, 0 },
|
||||||
{"smla" , 0 , 4 , 0},
|
{ "smla", 0, 4, 0 },
|
||||||
{"mcrr" , 0 , 6 , 0},
|
{ "mcrr", 0, 6, 0 },
|
||||||
{"mrrc" , 0 , 6 , 0},
|
{ "mrrc", 0, 6, 0 },
|
||||||
{"cmp" , 3 , 0 , 4, 4, 0x00000001, 7, 7, 0x00000001, 25, 25, 0x00000000},
|
{ "cmp", 3, 0, 4, 4, 0x00000001, 7, 7, 0x00000001, 25, 25, 0x00000000 },
|
||||||
{"tst" , 3 , 0 , 4, 4, 0x00000001, 7, 7, 0x00000001, 25, 25, 0x00000000},
|
{ "tst", 3, 0, 4, 4, 0x00000001, 7, 7, 0x00000001, 25, 25, 0x00000000 },
|
||||||
{"teq" , 3 , 0 , 4, 4, 0x00000001, 7, 7, 0x00000001, 25, 25, 0x00000000},
|
{ "teq", 3, 0, 4, 4, 0x00000001, 7, 7, 0x00000001, 25, 25, 0x00000000 },
|
||||||
{"cmn" , 3 , 0 , 4, 4, 0x00000001, 7, 7, 0x00000001, 25, 25, 0x00000000},
|
{ "cmn", 3, 0, 4, 4, 0x00000001, 7, 7, 0x00000001, 25, 25, 0x00000000 },
|
||||||
{"smull" , 0 , 0 , 0},
|
{ "smull", 0, 0, 0 },
|
||||||
{"umull" , 0 , 0 , 0},
|
{ "umull", 0, 0, 0 },
|
||||||
{"umlal" , 0 , 0 , 0},
|
{ "umlal", 0, 0, 0 },
|
||||||
{"smlal" , 0 , 0 , 0},
|
{ "smlal", 0, 0, 0 },
|
||||||
{"mul" , 0 , 0 , 0},
|
{ "mul", 0, 0, 0 },
|
||||||
{"mla" , 0 , 0 , 0},
|
{ "mla", 0, 0, 0 },
|
||||||
{"ssat" , 0 , 6 , 0},
|
{ "ssat", 0, 6, 0 },
|
||||||
{"usat" , 0 , 6 , 0},
|
{ "usat", 0, 6, 0 },
|
||||||
{"mrs" , 0 , 0 , 0},
|
{ "mrs", 0, 0, 0 },
|
||||||
{"msr" , 0 , 0 , 0},
|
{ "msr", 0, 0, 0 },
|
||||||
{"and" , 3 , 0 , 4, 4, 0x00000001, 7, 7, 0x00000001, 25, 25, 0x00000000},
|
{ "and", 3, 0, 4, 4, 0x00000001, 7, 7, 0x00000001, 25, 25, 0x00000000 },
|
||||||
{"bic" , 3 , 0 , 4, 4, 0x00000001, 7, 7, 0x00000001, 25, 25, 0x00000000},
|
{ "bic", 3, 0, 4, 4, 0x00000001, 7, 7, 0x00000001, 25, 25, 0x00000000 },
|
||||||
{"ldm" , 0 , 0 , 0},
|
{ "ldm", 0, 0, 0 },
|
||||||
{"eor" , 3 , 0 , 4, 4, 0x00000001, 7, 7, 0x00000001, 25, 25, 0x00000000},
|
{ "eor", 3, 0, 4, 4, 0x00000001, 7, 7, 0x00000001, 25, 25, 0x00000000 },
|
||||||
{"add" , 3 , 0 , 4, 4, 0x00000001, 7, 7, 0x00000001, 25, 25, 0x00000000},
|
{ "add", 3, 0, 4, 4, 0x00000001, 7, 7, 0x00000001, 25, 25, 0x00000000 },
|
||||||
{"rsb" , 3 , 0 , 4, 4, 0x00000001, 7, 7, 0x00000001, 25, 25, 0x00000000},
|
{ "rsb", 3, 0, 4, 4, 0x00000001, 7, 7, 0x00000001, 25, 25, 0x00000000 },
|
||||||
{"rsc" , 3 , 0 , 4, 4, 0x00000001, 7, 7, 0x00000001, 25, 25, 0x00000000},
|
{ "rsc", 3, 0, 4, 4, 0x00000001, 7, 7, 0x00000001, 25, 25, 0x00000000 },
|
||||||
{"sbc" , 3 , 0 , 4, 4, 0x00000001, 7, 7, 0x00000001, 25, 25, 0x00000000},
|
{ "sbc", 3, 0, 4, 4, 0x00000001, 7, 7, 0x00000001, 25, 25, 0x00000000 },
|
||||||
{"adc" , 3 , 0 , 4, 4, 0x00000001, 7, 7, 0x00000001, 25, 25, 0x00000000},
|
{ "adc", 3, 0, 4, 4, 0x00000001, 7, 7, 0x00000001, 25, 25, 0x00000000 },
|
||||||
{"sub" , 3 , 0 , 4, 4, 0x00000001, 7, 7, 0x00000001, 25, 25, 0x00000000},
|
{ "sub", 3, 0, 4, 4, 0x00000001, 7, 7, 0x00000001, 25, 25, 0x00000000 },
|
||||||
{"orr" , 3 , 0 , 4, 4, 0x00000001, 7, 7, 0x00000001, 25, 25, 0x00000000},
|
{ "orr", 3, 0, 4, 4, 0x00000001, 7, 7, 0x00000001, 25, 25, 0x00000000 },
|
||||||
{"mvn" , 3 , 0 , 4, 4, 0x00000001, 7, 7, 0x00000001, 25, 25, 0x00000000},
|
{ "mvn", 3, 0, 4, 4, 0x00000001, 7, 7, 0x00000001, 25, 25, 0x00000000 },
|
||||||
{"mov" , 3 , 0 , 4, 4, 0x00000001, 7, 7, 0x00000001, 25, 25, 0x00000000},
|
{ "mov", 3, 0, 4, 4, 0x00000001, 7, 7, 0x00000001, 25, 25, 0x00000000 },
|
||||||
{"stm" , 0 , 0 , 0},
|
{ "stm", 0, 0, 0 },
|
||||||
{"ldm" , 0 , 0 , 0},
|
{ "ldm", 0, 0, 0 },
|
||||||
{"ldrsh" , 0 , 2 , 0},
|
{ "ldrsh", 0, 2, 0 },
|
||||||
{"stm" , 0 , 0 , 0},
|
{ "stm", 0, 0, 0 },
|
||||||
{"ldm" , 0 , 0 , 0},
|
{ "ldm", 0, 0, 0 },
|
||||||
{"ldrsb" , 0 , 2 , 0},
|
{ "ldrsb", 0, 2, 0 },
|
||||||
{"strd" , 0 , 4 , 0},
|
{ "strd", 0, 4, 0 },
|
||||||
{"ldrh" , 0 , 0 , 0},
|
{ "ldrh", 0, 0, 0 },
|
||||||
{"strh" , 0 , 0 , 0},
|
{ "strh", 0, 0, 0 },
|
||||||
{"ldrd" , 0 , 4 , 0},
|
{ "ldrd", 0, 4, 0 },
|
||||||
{"strt" , 0 , 0 , 0},
|
{ "strt", 0, 0, 0 },
|
||||||
{"strbt" , 0 , 0 , 0},
|
{ "strbt", 0, 0, 0 },
|
||||||
{"ldrbt" , 0 , 0 , 0},
|
{ "ldrbt", 0, 0, 0 },
|
||||||
{"ldrt" , 0 , 0 , 0},
|
{ "ldrt", 0, 0, 0 },
|
||||||
{"mrc" , 0 , 6 , 0},
|
{ "mrc", 0, 6, 0 },
|
||||||
{"mcr" , 0 , 0 , 0},
|
{ "mcr", 0, 0, 0 },
|
||||||
{"msr" , 0 , 0 , 0},
|
{ "msr", 0, 0, 0 },
|
||||||
{"ldrb" , 0 , 0 , 0},
|
{ "ldrb", 0, 0, 0 },
|
||||||
{"strb" , 0 , 0 , 0},
|
{ "strb", 0, 0, 0 },
|
||||||
{"ldr" , 0 , 0 , 0},
|
{ "ldr", 0, 0, 0 },
|
||||||
{"ldrcond" , 1 , 0 , 28, 31, 0x0000000e},
|
{ "ldrcond", 1, 0, 28, 31, 0x0000000e },
|
||||||
{"str" , 0 , 0 , 0},
|
{ "str", 0, 0, 0 },
|
||||||
{"cdp" , 0 , 0 , 0},
|
{ "cdp", 0, 0, 0 },
|
||||||
{"stc" , 0 , 0 , 0},
|
{ "stc", 0, 0, 0 },
|
||||||
{"ldc" , 0 , 0 , 0},
|
{ "ldc", 0, 0, 0 },
|
||||||
{"swi" , 0 , 0 , 0},
|
{ "swi", 0, 0, 0 },
|
||||||
{"bbl" , 0 , 0 , 0},
|
{ "bbl", 0, 0, 0 },
|
||||||
{"bl_1_thumb", 0, INVALID, 0},/* should be table[-4] */
|
{ "bl_1_thumb", 0, INVALID, 0 }, // Should be table[-4]
|
||||||
{"bl_2_thumb", 0, INVALID, 0}, /* should be located at the end of the table[-3] */
|
{ "bl_2_thumb", 0, INVALID, 0 }, // Should be located at the end of the table[-3]
|
||||||
{"blx_1_thumb", 0, INVALID, 0}, /* should be located at table[-2] */
|
{ "blx_1_thumb", 0, INVALID, 0 }, // Should be located at table[-2]
|
||||||
{"invalid", 0, INVALID, 0}
|
{ "invalid", 0, INVALID, 0 }
|
||||||
};
|
};
|
||||||
|
|
||||||
int decode_arm_instr(uint32_t instr, int32_t *idx)
|
int decode_arm_instr(uint32_t instr, int32_t *idx) {
|
||||||
{
|
int n = 0;
|
||||||
int n = 0;
|
int base = 0;
|
||||||
int base = 0;
|
int ret = DECODE_FAILURE;
|
||||||
int ret = DECODE_FAILURE;
|
int i = 0;
|
||||||
int i = 0;
|
int instr_slots = sizeof(arm_instruction) / sizeof(ISEITEM);
|
||||||
int instr_slots = sizeof(arm_instruction)/sizeof(ISEITEM);
|
for (i = 0; i < instr_slots; i++) {
|
||||||
for (i = 0; i < instr_slots; i++)
|
n = arm_instruction[i].attribute_value;
|
||||||
{
|
base = 0;
|
||||||
// ret = DECODE_SUCCESS;
|
|
||||||
n = arm_instruction[i].attribute_value;
|
|
||||||
base = 0;
|
|
||||||
while (n) {
|
|
||||||
if (arm_instruction[i].content[base + 1] == 31 && arm_instruction[i].content[base] == 0) {
|
|
||||||
/* clrex */
|
|
||||||
if (instr != arm_instruction[i].content[base + 2]) {
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
} else if (BITS(arm_instruction[i].content[base], arm_instruction[i].content[base + 1]) != arm_instruction[i].content[base + 2]) {
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
base += 3;
|
|
||||||
n --;
|
|
||||||
}
|
|
||||||
//All conditions is satisfied.
|
|
||||||
if (n == 0)
|
|
||||||
ret = DECODE_SUCCESS;
|
|
||||||
|
|
||||||
if (ret == DECODE_SUCCESS) {
|
while (n) {
|
||||||
n = arm_exclusion_code[i].attribute_value;
|
if (arm_instruction[i].content[base + 1] == 31 && arm_instruction[i].content[base] == 0) {
|
||||||
if (n != 0) {
|
// clrex
|
||||||
base = 0;
|
if (instr != arm_instruction[i].content[base + 2]) {
|
||||||
while (n) {
|
break;
|
||||||
if (BITS(arm_exclusion_code[i].content[base], arm_exclusion_code[i].content[base + 1]) != arm_exclusion_code[i].content[base + 2]) {
|
}
|
||||||
break; }
|
} else if (BITS(arm_instruction[i].content[base], arm_instruction[i].content[base + 1]) != arm_instruction[i].content[base + 2]) {
|
||||||
base += 3;
|
break;
|
||||||
n --;
|
}
|
||||||
}
|
base += 3;
|
||||||
//All conditions is satisfied.
|
n--;
|
||||||
if (n == 0)
|
}
|
||||||
ret = DECODE_FAILURE;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
if (ret == DECODE_SUCCESS) {
|
// All conditions is satisfied.
|
||||||
*idx = i;
|
if (n == 0)
|
||||||
return ret;
|
ret = DECODE_SUCCESS;
|
||||||
}
|
|
||||||
}
|
if (ret == DECODE_SUCCESS) {
|
||||||
return ret;
|
n = arm_exclusion_code[i].attribute_value;
|
||||||
|
if (n != 0) {
|
||||||
|
base = 0;
|
||||||
|
while (n) {
|
||||||
|
if (BITS(arm_exclusion_code[i].content[base], arm_exclusion_code[i].content[base + 1]) != arm_exclusion_code[i].content[base + 2]) {
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
base += 3;
|
||||||
|
n--;
|
||||||
|
}
|
||||||
|
|
||||||
|
// All conditions is satisfied.
|
||||||
|
if (n == 0)
|
||||||
|
ret = DECODE_FAILURE;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
if (ret == DECODE_SUCCESS) {
|
||||||
|
*idx = i;
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
return ret;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
|
||||||
File diff suppressed because it is too large
Load diff
|
|
@ -1,41 +1,15 @@
|
||||||
/* Copyright (C)
|
// Copyright 2012 Michael Kang, 2014 Citra Emulator Project
|
||||||
* 2011 - Michael.Kang blackfin.kang@gmail.com
|
// Licensed under GPLv2 or any later version
|
||||||
* This program is free software; you can redistribute it and/or
|
// Refer to the license.txt file included.
|
||||||
* modify it under the terms of the GNU General Public License
|
|
||||||
* as published by the Free Software Foundation; either version 2
|
|
||||||
* of the License, or (at your option) any later version.
|
|
||||||
*
|
|
||||||
* This program is distributed in the hope that it will be useful,
|
|
||||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
||||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
||||||
* GNU General Public License for more details.
|
|
||||||
*
|
|
||||||
* You should have received a copy of the GNU General Public License
|
|
||||||
* along with this program; if not, write to the Free Software
|
|
||||||
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
|
|
||||||
*
|
|
||||||
*/
|
|
||||||
/**
|
|
||||||
* @file arm_dyncom_run.cpp
|
|
||||||
* @brief The dyncom run implementation for arm
|
|
||||||
* @author Michael.Kang blackfin.kang@gmail.com
|
|
||||||
* @version 78.77
|
|
||||||
* @date 2011-11-20
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include <assert.h>
|
#include <assert.h>
|
||||||
|
|
||||||
#include "core/arm/skyeye_common/armdefs.h"
|
#include "core/arm/skyeye_common/armdefs.h"
|
||||||
|
|
||||||
void switch_mode(arm_core_t *core, uint32_t mode)
|
void switch_mode(arm_core_t *core, uint32_t mode) {
|
||||||
{
|
if (core->Mode == mode)
|
||||||
if (core->Mode == mode) {
|
|
||||||
//Mode not changed.
|
|
||||||
//printf("mode not changed\n");
|
|
||||||
return;
|
return;
|
||||||
}
|
|
||||||
//printf("%d --->>> %d\n", core->Mode, mode);
|
|
||||||
//printf("In %s, Cpsr=0x%x, R15=0x%x, last_pc=0x%x, cpsr=0x%x, spsr_copy=0x%x, icounter=%lld\n", __FUNCTION__, core->Cpsr, core->Reg[15], core->last_pc, core->Cpsr, core->Spsr_copy, core->icounter);
|
|
||||||
if (mode != USERBANK) {
|
if (mode != USERBANK) {
|
||||||
switch (core->Mode) {
|
switch (core->Mode) {
|
||||||
case USER32MODE:
|
case USER32MODE:
|
||||||
|
|
@ -109,11 +83,8 @@ void switch_mode(arm_core_t *core, uint32_t mode)
|
||||||
|
|
||||||
}
|
}
|
||||||
core->Mode = mode;
|
core->Mode = mode;
|
||||||
//printf("In %si end, Cpsr=0x%x, R15=0x%x, last_pc=0x%x, cpsr=0x%x, spsr_copy=0x%x, icounter=%lld\n", __FUNCTION__, core->Cpsr, core->Reg[15], core->last_pc, core->Cpsr, core->Spsr_copy, core->icounter);
|
} else {
|
||||||
//printf("\n--------------------------------------\n");
|
LOG_CRITICAL(Core_ARM11, "user mode");
|
||||||
}
|
|
||||||
else {
|
|
||||||
printf("user mode\n");
|
|
||||||
exit(-2);
|
exit(-2);
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
|
||||||
|
|
@ -1,35 +1,13 @@
|
||||||
/* Copyright (C)
|
// Copyright 2012 Michael Kang, 2014 Citra Emulator Project
|
||||||
* 2011 - Michael.Kang blackfin.kang@gmail.com
|
// Licensed under GPLv2 or any later version
|
||||||
* This program is free software; you can redistribute it and/or
|
// Refer to the license.txt file included.
|
||||||
* modify it under the terms of the GNU General Public License
|
|
||||||
* as published by the Free Software Foundation; either version 2
|
|
||||||
* of the License, or (at your option) any later version.
|
|
||||||
*
|
|
||||||
* This program is distributed in the hope that it will be useful,
|
|
||||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
||||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
||||||
* GNU General Public License for more details.
|
|
||||||
*
|
|
||||||
* You should have received a copy of the GNU General Public License
|
|
||||||
* along with this program; if not, write to the Free Software
|
|
||||||
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
|
|
||||||
*
|
|
||||||
*/
|
|
||||||
/**
|
|
||||||
* @file arm_dyncom_thumb.c
|
|
||||||
* @brief The thumb dynamic interpreter
|
|
||||||
* @author Michael.Kang blackfin.kang@gmail.com
|
|
||||||
* @version 78.77
|
|
||||||
* @date 2011-11-07
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* We can provide simple Thumb simulation by decoding the Thumb
|
// We can provide simple Thumb simulation by decoding the Thumb instruction into its corresponding
|
||||||
instruction into its corresponding ARM instruction, and using the
|
// ARM instruction, and using the existing ARM simulator.
|
||||||
existing ARM simulator. */
|
|
||||||
|
|
||||||
#include "core/arm/skyeye_common/skyeye_defs.h"
|
#include "core/arm/skyeye_common/skyeye_defs.h"
|
||||||
|
|
||||||
#ifndef MODET /* required for the Thumb instruction support */
|
#ifndef MODET // Required for the Thumb instruction support
|
||||||
#if 1
|
#if 1
|
||||||
#error "MODET needs to be defined for the Thumb world to work"
|
#error "MODET needs to be defined for the Thumb world to work"
|
||||||
#else
|
#else
|
||||||
|
|
@ -40,482 +18,359 @@ existing ARM simulator. */
|
||||||
#include "core/arm/skyeye_common/armos.h"
|
#include "core/arm/skyeye_common/armos.h"
|
||||||
#include "core/arm/dyncom/arm_dyncom_thumb.h"
|
#include "core/arm/dyncom/arm_dyncom_thumb.h"
|
||||||
|
|
||||||
/* Decode a 16bit Thumb instruction. The instruction is in the low
|
// Decode a 16bit Thumb instruction. The instruction is in the low 16-bits of the tinstr field,
|
||||||
16-bits of the tinstr field, with the following Thumb instruction
|
// with the following Thumb instruction held in the high 16-bits. Passing in two Thumb instructions
|
||||||
held in the high 16-bits. Passing in two Thumb instructions allows
|
// allows easier simulation of the special dual BL instruction.
|
||||||
easier simulation of the special dual BL instruction. */
|
|
||||||
|
|
||||||
tdstate thumb_translate (addr_t addr, uint32_t instr, uint32_t* ainstr, uint32_t* inst_size)
|
tdstate thumb_translate (addr_t addr, uint32_t instr, uint32_t* ainstr, uint32_t* inst_size) {
|
||||||
{
|
|
||||||
tdstate valid = t_uninitialized;
|
tdstate valid = t_uninitialized;
|
||||||
ARMword next_instr;
|
ARMword tinstr;
|
||||||
ARMword tinstr;
|
tinstr = instr;
|
||||||
tinstr = instr;
|
|
||||||
/* The endian should be judge here */
|
|
||||||
#if 0
|
|
||||||
if (state->bigendSig) {
|
|
||||||
next_instr = tinstr & 0xFFFF;
|
|
||||||
tinstr >>= 16;
|
|
||||||
}
|
|
||||||
else {
|
|
||||||
next_instr = tinstr >> 16;
|
|
||||||
tinstr &= 0xFFFF;
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
if((addr & 0x3) != 0)
|
|
||||||
tinstr = instr >> 16;
|
|
||||||
else
|
|
||||||
tinstr &= 0xFFFF;
|
|
||||||
|
|
||||||
//printf("In %s, instr=0x%x, tinstr=0x%x, r15=0x%x\n", __FUNCTION__, instr, tinstr, cpu->translate_pc);
|
// The endian should be judge here
|
||||||
#if 1 /* debugging to catch non updates */
|
if((addr & 0x3) != 0)
|
||||||
*ainstr = 0xDEADC0DE;
|
tinstr = instr >> 16;
|
||||||
#endif
|
else
|
||||||
|
tinstr &= 0xFFFF;
|
||||||
|
|
||||||
switch ((tinstr & 0xF800) >> 11) {
|
*ainstr = 0xDEADC0DE; // Debugging to catch non updates
|
||||||
case 0: /* LSL */
|
|
||||||
case 1: /* LSR */
|
|
||||||
case 2: /* ASR */
|
|
||||||
/* Format 1 */
|
|
||||||
*ainstr = 0xE1B00000 /* base opcode */
|
|
||||||
| ((tinstr & 0x1800) >> (11 - 5)) /* shift type */
|
|
||||||
|((tinstr & 0x07C0) << (7 - 6)) /* imm5 */
|
|
||||||
|((tinstr & 0x0038) >> 3) /* Rs */
|
|
||||||
|((tinstr & 0x0007) << 12); /* Rd */
|
|
||||||
break;
|
|
||||||
case 3: /* ADD/SUB */
|
|
||||||
/* Format 2 */
|
|
||||||
{
|
|
||||||
ARMword subset[4] = {
|
|
||||||
0xE0900000, /* ADDS Rd,Rs,Rn */
|
|
||||||
0xE0500000, /* SUBS Rd,Rs,Rn */
|
|
||||||
0xE2900000, /* ADDS Rd,Rs,#imm3 */
|
|
||||||
0xE2500000 /* SUBS Rd,Rs,#imm3 */
|
|
||||||
};
|
|
||||||
/* It is quicker indexing into a table, than performing switch
|
|
||||||
or conditionals: */
|
|
||||||
*ainstr = subset[(tinstr & 0x0600) >> 9] /* base opcode */
|
|
||||||
|((tinstr & 0x01C0) >> 6) /* Rn or imm3 */
|
|
||||||
|((tinstr & 0x0038) << (16 - 3)) /* Rs */
|
|
||||||
|((tinstr & 0x0007) << (12 - 0)); /* Rd */
|
|
||||||
}
|
|
||||||
break;
|
|
||||||
case 4: /* MOV */
|
|
||||||
case 5: /* CMP */
|
|
||||||
case 6: /* ADD */
|
|
||||||
case 7: /* SUB */
|
|
||||||
/* Format 3 */
|
|
||||||
{
|
|
||||||
ARMword subset[4] = {
|
|
||||||
0xE3B00000, /* MOVS Rd,#imm8 */
|
|
||||||
0xE3500000, /* CMP Rd,#imm8 */
|
|
||||||
0xE2900000, /* ADDS Rd,Rd,#imm8 */
|
|
||||||
0xE2500000, /* SUBS Rd,Rd,#imm8 */
|
|
||||||
};
|
|
||||||
*ainstr = subset[(tinstr & 0x1800) >> 11] /* base opcode */
|
|
||||||
|((tinstr & 0x00FF) >> 0) /* imm8 */
|
|
||||||
|((tinstr & 0x0700) << (16 - 8)) /* Rn */
|
|
||||||
|((tinstr & 0x0700) << (12 - 8)); /* Rd */
|
|
||||||
}
|
|
||||||
break;
|
|
||||||
case 8: /* Arithmetic and high register transfers */
|
|
||||||
/* TODO: Since the subsets for both Format 4 and Format 5
|
|
||||||
instructions are made up of different ARM encodings, we could
|
|
||||||
save the following conditional, and just have one large
|
|
||||||
subset. */
|
|
||||||
if ((tinstr & (1 << 10)) == 0) {
|
|
||||||
typedef enum
|
|
||||||
{ t_norm, t_shift, t_neg, t_mul }otype_t;
|
|
||||||
|
|
||||||
/* Format 4 */
|
switch ((tinstr & 0xF800) >> 11) {
|
||||||
struct
|
case 0: // LSL
|
||||||
{
|
case 1: // LSR
|
||||||
ARMword opcode;
|
case 2: // ASR
|
||||||
otype_t otype;
|
*ainstr = 0xE1B00000 // base opcode
|
||||||
}
|
| ((tinstr & 0x1800) >> (11 - 5)) // shift type
|
||||||
subset[16] = {
|
|((tinstr & 0x07C0) << (7 - 6)) // imm5
|
||||||
{
|
|((tinstr & 0x0038) >> 3) // Rs
|
||||||
0xE0100000, t_norm}, /* ANDS Rd,Rd,Rs */
|
|((tinstr & 0x0007) << 12); // Rd
|
||||||
{
|
break;
|
||||||
0xE0300000, t_norm}, /* EORS Rd,Rd,Rs */
|
|
||||||
{
|
|
||||||
0xE1B00010, t_shift}, /* MOVS Rd,Rd,LSL Rs */
|
|
||||||
{
|
|
||||||
0xE1B00030, t_shift}, /* MOVS Rd,Rd,LSR Rs */
|
|
||||||
{
|
|
||||||
0xE1B00050, t_shift}, /* MOVS Rd,Rd,ASR Rs */
|
|
||||||
{
|
|
||||||
0xE0B00000, t_norm}, /* ADCS Rd,Rd,Rs */
|
|
||||||
{
|
|
||||||
0xE0D00000, t_norm}, /* SBCS Rd,Rd,Rs */
|
|
||||||
{
|
|
||||||
0xE1B00070, t_shift}, /* MOVS Rd,Rd,ROR Rs */
|
|
||||||
{
|
|
||||||
0xE1100000, t_norm}, /* TST Rd,Rs */
|
|
||||||
{
|
|
||||||
0xE2700000, t_neg}, /* RSBS Rd,Rs,#0 */
|
|
||||||
{
|
|
||||||
0xE1500000, t_norm}, /* CMP Rd,Rs */
|
|
||||||
{
|
|
||||||
0xE1700000, t_norm}, /* CMN Rd,Rs */
|
|
||||||
{
|
|
||||||
0xE1900000, t_norm}, /* ORRS Rd,Rd,Rs */
|
|
||||||
{
|
|
||||||
0xE0100090, t_mul}, /* MULS Rd,Rd,Rs */
|
|
||||||
{
|
|
||||||
0xE1D00000, t_norm}, /* BICS Rd,Rd,Rs */
|
|
||||||
{
|
|
||||||
0xE1F00000, t_norm} /* MVNS Rd,Rs */
|
|
||||||
};
|
|
||||||
*ainstr = subset[(tinstr & 0x03C0) >> 6].opcode; /* base */
|
|
||||||
switch (subset[(tinstr & 0x03C0) >> 6].otype) {
|
|
||||||
case t_norm:
|
|
||||||
*ainstr |= ((tinstr & 0x0007) << 16) /* Rn */
|
|
||||||
|((tinstr & 0x0007) << 12) /* Rd */
|
|
||||||
|((tinstr & 0x0038) >> 3); /* Rs */
|
|
||||||
break;
|
|
||||||
case t_shift:
|
|
||||||
*ainstr |= ((tinstr & 0x0007) << 12) /* Rd */
|
|
||||||
|((tinstr & 0x0007) >> 0) /* Rm */
|
|
||||||
|((tinstr & 0x0038) << (8 - 3)); /* Rs */
|
|
||||||
break;
|
|
||||||
case t_neg:
|
|
||||||
*ainstr |= ((tinstr & 0x0007) << 12) /* Rd */
|
|
||||||
|((tinstr & 0x0038) << (16 - 3)); /* Rn */
|
|
||||||
break;
|
|
||||||
case t_mul:
|
|
||||||
*ainstr |= ((tinstr & 0x0007) << 16) /* Rd */
|
|
||||||
|((tinstr & 0x0007) << 8) /* Rs */
|
|
||||||
|((tinstr & 0x0038) >> 3); /* Rm */
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
else {
|
|
||||||
/* Format 5 */
|
|
||||||
ARMword Rd = ((tinstr & 0x0007) >> 0);
|
|
||||||
ARMword Rs = ((tinstr & 0x0038) >> 3);
|
|
||||||
if (tinstr & (1 << 7))
|
|
||||||
Rd += 8;
|
|
||||||
if (tinstr & (1 << 6))
|
|
||||||
Rs += 8;
|
|
||||||
switch ((tinstr & 0x03C0) >> 6) {
|
|
||||||
case 0x1: /* ADD Rd,Rd,Hs */
|
|
||||||
case 0x2: /* ADD Hd,Hd,Rs */
|
|
||||||
case 0x3: /* ADD Hd,Hd,Hs */
|
|
||||||
*ainstr = 0xE0800000 /* base */
|
|
||||||
| (Rd << 16) /* Rn */
|
|
||||||
|(Rd << 12) /* Rd */
|
|
||||||
|(Rs << 0); /* Rm */
|
|
||||||
break;
|
|
||||||
case 0x5: /* CMP Rd,Hs */
|
|
||||||
case 0x6: /* CMP Hd,Rs */
|
|
||||||
case 0x7: /* CMP Hd,Hs */
|
|
||||||
*ainstr = 0xE1500000 /* base */
|
|
||||||
| (Rd << 16) /* Rn */
|
|
||||||
|(Rd << 12) /* Rd */
|
|
||||||
|(Rs << 0); /* Rm */
|
|
||||||
break;
|
|
||||||
case 0x9: /* MOV Rd,Hs */
|
|
||||||
case 0xA: /* MOV Hd,Rs */
|
|
||||||
case 0xB: /* MOV Hd,Hs */
|
|
||||||
*ainstr = 0xE1A00000 /* base */
|
|
||||||
| (Rd << 16) /* Rn */
|
|
||||||
|(Rd << 12) /* Rd */
|
|
||||||
|(Rs << 0); /* Rm */
|
|
||||||
break;
|
|
||||||
case 0xC: /* BX Rs */
|
|
||||||
case 0xD: /* BX Hs */
|
|
||||||
*ainstr = 0xE12FFF10 /* base */
|
|
||||||
| ((tinstr & 0x0078) >> 3); /* Rd */
|
|
||||||
break;
|
|
||||||
case 0x0: /* UNDEFINED */
|
|
||||||
case 0x4: /* UNDEFINED */
|
|
||||||
case 0x8: /* UNDEFINED */
|
|
||||||
valid = t_undefined;
|
|
||||||
break;
|
|
||||||
case 0xE: /* BLX */
|
|
||||||
case 0xF: /* BLX */
|
|
||||||
|
|
||||||
//if (state->is_v5) {
|
case 3: // ADD/SUB
|
||||||
if(1){
|
{
|
||||||
//valid = t_branch;
|
ARMword subset[4] = {
|
||||||
#if 1
|
0xE0900000, // ADDS Rd,Rs,Rn
|
||||||
*ainstr = 0xE1200030 /* base */
|
0xE0500000, // SUBS Rd,Rs,Rn
|
||||||
|(Rs << 0); /* Rm */
|
0xE2900000, // ADDS Rd,Rs,#imm3
|
||||||
#endif
|
0xE2500000 // SUBS Rd,Rs,#imm3
|
||||||
} else {
|
};
|
||||||
valid = t_undefined;
|
// It is quicker indexing into a table, than performing switch or conditionals:
|
||||||
}
|
*ainstr = subset[(tinstr & 0x0600) >> 9] // base opcode
|
||||||
break;
|
|((tinstr & 0x01C0) >> 6) // Rn or imm3
|
||||||
}
|
|((tinstr & 0x0038) << (16 - 3)) // Rs
|
||||||
}
|
|((tinstr & 0x0007) << (12 - 0)); // Rd
|
||||||
break;
|
}
|
||||||
case 9: /* LDR Rd,[PC,#imm8] */
|
break;
|
||||||
/* Format 6 */
|
|
||||||
*ainstr = 0xE59F0000 /* base */
|
case 4: // MOV
|
||||||
| ((tinstr & 0x0700) << (12 - 8)) /* Rd */
|
case 5: // CMP
|
||||||
|((tinstr & 0x00FF) << (2 - 0)); /* off8 */
|
case 6: // ADD
|
||||||
break;
|
case 7: // SUB
|
||||||
case 10:
|
{
|
||||||
case 11:
|
ARMword subset[4] = {
|
||||||
/* TODO: Format 7 and Format 8 perform the same ARM encoding, so
|
0xE3B00000, // MOVS Rd,#imm8
|
||||||
the following could be merged into a single subset, saving on
|
0xE3500000, // CMP Rd,#imm8
|
||||||
the following boolean: */
|
0xE2900000, // ADDS Rd,Rd,#imm8
|
||||||
if ((tinstr & (1 << 9)) == 0) {
|
0xE2500000, // SUBS Rd,Rd,#imm8
|
||||||
/* Format 7 */
|
};
|
||||||
ARMword subset[4] = {
|
|
||||||
0xE7800000, /* STR Rd,[Rb,Ro] */
|
*ainstr = subset[(tinstr & 0x1800) >> 11] // base opcode
|
||||||
0xE7C00000, /* STRB Rd,[Rb,Ro] */
|
|((tinstr & 0x00FF) >> 0) // imm8
|
||||||
0xE7900000, /* LDR Rd,[Rb,Ro] */
|
|((tinstr & 0x0700) << (16 - 8)) // Rn
|
||||||
0xE7D00000 /* LDRB Rd,[Rb,Ro] */
|
|((tinstr & 0x0700) << (12 - 8)); // Rd
|
||||||
};
|
}
|
||||||
*ainstr = subset[(tinstr & 0x0C00) >> 10] /* base */
|
break;
|
||||||
|((tinstr & 0x0007) << (12 - 0)) /* Rd */
|
|
||||||
|((tinstr & 0x0038) << (16 - 3)) /* Rb */
|
case 8: // Arithmetic and high register transfers
|
||||||
|((tinstr & 0x01C0) >> 6); /* Ro */
|
|
||||||
}
|
// TODO: Since the subsets for both Format 4 and Format 5 instructions are made up of
|
||||||
else {
|
// different ARM encodings, we could save the following conditional, and just have one
|
||||||
/* Format 8 */
|
// large subset
|
||||||
ARMword subset[4] = {
|
|
||||||
0xE18000B0, /* STRH Rd,[Rb,Ro] */
|
if ((tinstr & (1 << 10)) == 0) {
|
||||||
0xE19000D0, /* LDRSB Rd,[Rb,Ro] */
|
enum otype {
|
||||||
0xE19000B0, /* LDRH Rd,[Rb,Ro] */
|
t_norm,
|
||||||
0xE19000F0 /* LDRSH Rd,[Rb,Ro] */
|
t_shift,
|
||||||
};
|
t_neg,
|
||||||
*ainstr = subset[(tinstr & 0x0C00) >> 10] /* base */
|
t_mul
|
||||||
|((tinstr & 0x0007) << (12 - 0)) /* Rd */
|
};
|
||||||
|((tinstr & 0x0038) << (16 - 3)) /* Rb */
|
|
||||||
|((tinstr & 0x01C0) >> 6); /* Ro */
|
struct {
|
||||||
}
|
ARMword opcode;
|
||||||
break;
|
otype type;
|
||||||
case 12: /* STR Rd,[Rb,#imm5] */
|
} subset[16] = {
|
||||||
case 13: /* LDR Rd,[Rb,#imm5] */
|
{ 0xE0100000, t_norm }, // ANDS Rd,Rd,Rs
|
||||||
case 14: /* STRB Rd,[Rb,#imm5] */
|
{ 0xE0300000, t_norm }, // EORS Rd,Rd,Rs
|
||||||
case 15: /* LDRB Rd,[Rb,#imm5] */
|
{ 0xE1B00010, t_shift }, // MOVS Rd,Rd,LSL Rs
|
||||||
/* Format 9 */
|
{ 0xE1B00030, t_shift }, // MOVS Rd,Rd,LSR Rs
|
||||||
{
|
{ 0xE1B00050, t_shift }, // MOVS Rd,Rd,ASR Rs
|
||||||
ARMword subset[4] = {
|
{ 0xE0B00000, t_norm }, // ADCS Rd,Rd,Rs
|
||||||
0xE5800000, /* STR Rd,[Rb,#imm5] */
|
{ 0xE0D00000, t_norm }, // SBCS Rd,Rd,Rs
|
||||||
0xE5900000, /* LDR Rd,[Rb,#imm5] */
|
{ 0xE1B00070, t_shift }, // MOVS Rd,Rd,ROR Rs
|
||||||
0xE5C00000, /* STRB Rd,[Rb,#imm5] */
|
{ 0xE1100000, t_norm }, // TST Rd,Rs
|
||||||
0xE5D00000 /* LDRB Rd,[Rb,#imm5] */
|
{ 0xE2700000, t_neg }, // RSBS Rd,Rs,#0
|
||||||
};
|
{ 0xE1500000, t_norm }, // CMP Rd,Rs
|
||||||
/* The offset range defends on whether we are transferring a
|
{ 0xE1700000, t_norm }, // CMN Rd,Rs
|
||||||
byte or word value: */
|
{ 0xE1900000, t_norm }, // ORRS Rd,Rd,Rs
|
||||||
*ainstr = subset[(tinstr & 0x1800) >> 11] /* base */
|
{ 0xE0100090, t_mul }, // MULS Rd,Rd,Rs
|
||||||
|((tinstr & 0x0007) << (12 - 0)) /* Rd */
|
{ 0xE1D00000, t_norm }, // BICS Rd,Rd,Rs
|
||||||
|((tinstr & 0x0038) << (16 - 3)) /* Rb */
|
{ 0xE1F00000, t_norm } // MVNS Rd,Rs
|
||||||
|((tinstr & 0x07C0) >> (6 - ((tinstr & (1 << 12)) ? 0 : 2))); /* off5 */
|
};
|
||||||
}
|
|
||||||
break;
|
*ainstr = subset[(tinstr & 0x03C0) >> 6].opcode; // base
|
||||||
case 16: /* STRH Rd,[Rb,#imm5] */
|
|
||||||
case 17: /* LDRH Rd,[Rb,#imm5] */
|
switch (subset[(tinstr & 0x03C0) >> 6].type) {
|
||||||
/* Format 10 */
|
case t_norm:
|
||||||
*ainstr = ((tinstr & (1 << 11)) /* base */
|
*ainstr |= ((tinstr & 0x0007) << 16) // Rn
|
||||||
? 0xE1D000B0 /* LDRH */
|
|((tinstr & 0x0007) << 12) // Rd
|
||||||
: 0xE1C000B0) /* STRH */
|
|((tinstr & 0x0038) >> 3); // Rs
|
||||||
|((tinstr & 0x0007) << (12 - 0)) /* Rd */
|
break;
|
||||||
|((tinstr & 0x0038) << (16 - 3)) /* Rb */
|
case t_shift:
|
||||||
|((tinstr & 0x01C0) >> (6 - 1)) /* off5, low nibble */
|
*ainstr |= ((tinstr & 0x0007) << 12) // Rd
|
||||||
|((tinstr & 0x0600) >> (9 - 8)); /* off5, high nibble */
|
|((tinstr & 0x0007) >> 0) // Rm
|
||||||
break;
|
|((tinstr & 0x0038) << (8 - 3)); // Rs
|
||||||
case 18: /* STR Rd,[SP,#imm8] */
|
break;
|
||||||
case 19: /* LDR Rd,[SP,#imm8] */
|
case t_neg:
|
||||||
/* Format 11 */
|
*ainstr |= ((tinstr & 0x0007) << 12) // Rd
|
||||||
*ainstr = ((tinstr & (1 << 11)) /* base */
|
|((tinstr & 0x0038) << (16 - 3)); // Rn
|
||||||
? 0xE59D0000 /* LDR */
|
break;
|
||||||
: 0xE58D0000) /* STR */
|
case t_mul:
|
||||||
|((tinstr & 0x0700) << (12 - 8)) /* Rd */
|
*ainstr |= ((tinstr & 0x0007) << 16) // Rd
|
||||||
|((tinstr & 0x00FF) << 2); /* off8 */
|
|((tinstr & 0x0007) << 8) // Rs
|
||||||
break;
|
|((tinstr & 0x0038) >> 3); // Rm
|
||||||
case 20: /* ADD Rd,PC,#imm8 */
|
break;
|
||||||
case 21: /* ADD Rd,SP,#imm8 */
|
}
|
||||||
/* Format 12 */
|
} else {
|
||||||
if ((tinstr & (1 << 11)) == 0) {
|
ARMword Rd = ((tinstr & 0x0007) >> 0);
|
||||||
/* NOTE: The PC value used here should by word aligned */
|
ARMword Rs = ((tinstr & 0x0038) >> 3);
|
||||||
/* We encode shift-left-by-2 in the rotate immediate field,
|
|
||||||
so no shift of off8 is needed. */
|
if (tinstr & (1 << 7))
|
||||||
*ainstr = 0xE28F0F00 /* base */
|
Rd += 8;
|
||||||
| ((tinstr & 0x0700) << (12 - 8)) /* Rd */
|
if (tinstr & (1 << 6))
|
||||||
|(tinstr & 0x00FF); /* off8 */
|
Rs += 8;
|
||||||
}
|
|
||||||
else {
|
switch ((tinstr & 0x03C0) >> 6) {
|
||||||
/* We encode shift-left-by-2 in the rotate immediate field,
|
case 0x1: // ADD Rd,Rd,Hs
|
||||||
so no shift of off8 is needed. */
|
case 0x2: // ADD Hd,Hd,Rs
|
||||||
*ainstr = 0xE28D0F00 /* base */
|
case 0x3: // ADD Hd,Hd,Hs
|
||||||
| ((tinstr & 0x0700) << (12 - 8)) /* Rd */
|
*ainstr = 0xE0800000 // base
|
||||||
|(tinstr & 0x00FF); /* off8 */
|
| (Rd << 16) // Rn
|
||||||
}
|
|(Rd << 12) // Rd
|
||||||
break;
|
|(Rs << 0); // Rm
|
||||||
case 22:
|
break;
|
||||||
case 23:
|
case 0x5: // CMP Rd,Hs
|
||||||
if ((tinstr & 0x0F00) == 0x0000) {
|
case 0x6: // CMP Hd,Rs
|
||||||
/* Format 13 */
|
case 0x7: // CMP Hd,Hs
|
||||||
/* NOTE: The instruction contains a shift left of 2
|
*ainstr = 0xE1500000 // base
|
||||||
equivalent (implemented as ROR #30): */
|
| (Rd << 16) // Rn
|
||||||
*ainstr = ((tinstr & (1 << 7)) /* base */
|
|(Rd << 12) // Rd
|
||||||
? 0xE24DDF00 /* SUB */
|
|(Rs << 0); // Rm
|
||||||
: 0xE28DDF00) /* ADD */
|
break;
|
||||||
|(tinstr & 0x007F); /* off7 */
|
case 0x9: // MOV Rd,Hs
|
||||||
}
|
case 0xA: // MOV Hd,Rs
|
||||||
else if ((tinstr & 0x0F00) == 0x0e00)
|
case 0xB: // MOV Hd,Hs
|
||||||
*ainstr = 0xEF000000 | SWI_Breakpoint;
|
*ainstr = 0xE1A00000 // base
|
||||||
else {
|
| (Rd << 16) // Rn
|
||||||
/* Format 14 */
|
|(Rd << 12) // Rd
|
||||||
ARMword subset[4] = {
|
|(Rs << 0); // Rm
|
||||||
0xE92D0000, /* STMDB sp!,{rlist} */
|
break;
|
||||||
0xE92D4000, /* STMDB sp!,{rlist,lr} */
|
case 0xC: // BX Rs
|
||||||
0xE8BD0000, /* LDMIA sp!,{rlist} */
|
case 0xD: // BX Hs
|
||||||
0xE8BD8000 /* LDMIA sp!,{rlist,pc} */
|
*ainstr = 0xE12FFF10 // base
|
||||||
};
|
| ((tinstr & 0x0078) >> 3); // Rd
|
||||||
*ainstr = subset[((tinstr & (1 << 11)) >> 10) | ((tinstr & (1 << 8)) >> 8)] /* base */
|
break;
|
||||||
|(tinstr & 0x00FF); /* mask8 */
|
case 0x0: // UNDEFINED
|
||||||
}
|
case 0x4: // UNDEFINED
|
||||||
break;
|
case 0x8: // UNDEFINED
|
||||||
case 24: /* STMIA */
|
valid = t_undefined;
|
||||||
case 25: /* LDMIA */
|
break;
|
||||||
/* Format 15 */
|
case 0xE: // BLX
|
||||||
*ainstr = ((tinstr & (1 << 11)) /* base */
|
case 0xF: // BLX
|
||||||
? 0xE8B00000 /* LDMIA */
|
*ainstr = 0xE1200030 // base
|
||||||
: 0xE8A00000) /* STMIA */
|
| (Rs << 0); // Rm
|
||||||
|((tinstr & 0x0700) << (16 - 8)) /* Rb */
|
break;
|
||||||
|(tinstr & 0x00FF); /* mask8 */
|
}
|
||||||
break;
|
}
|
||||||
case 26: /* Bcc */
|
break;
|
||||||
case 27: /* Bcc/SWI */
|
|
||||||
if ((tinstr & 0x0F00) == 0x0F00) {
|
case 9: // LDR Rd,[PC,#imm8]
|
||||||
#if 0
|
*ainstr = 0xE59F0000 // base
|
||||||
if (tinstr == (ARMul_ABORTWORD & 0xffff) &&
|
| ((tinstr & 0x0700) << (12 - 8)) // Rd
|
||||||
state->AbortAddr == pc) {
|
|((tinstr & 0x00FF) << (2 - 0)); // off8
|
||||||
*ainstr = ARMul_ABORTWORD;
|
break;
|
||||||
break;
|
|
||||||
}
|
case 10:
|
||||||
#endif
|
case 11:
|
||||||
/* Format 17 : SWI */
|
// TODO: Format 7 and Format 8 perform the same ARM encoding, so the following could be
|
||||||
*ainstr = 0xEF000000;
|
// merged into a single subset, saving on the following boolean:
|
||||||
/* Breakpoint must be handled specially. */
|
|
||||||
if ((tinstr & 0x00FF) == 0x18)
|
if ((tinstr & (1 << 9)) == 0) {
|
||||||
*ainstr |= ((tinstr & 0x00FF) << 16);
|
ARMword subset[4] = {
|
||||||
/* New breakpoint value. See gdb/arm-tdep.c */
|
0xE7800000, // STR Rd,[Rb,Ro]
|
||||||
else if ((tinstr & 0x00FF) == 0xFE)
|
0xE7C00000, // STRB Rd,[Rb,Ro]
|
||||||
*ainstr |= SWI_Breakpoint;
|
0xE7900000, // LDR Rd,[Rb,Ro]
|
||||||
else
|
0xE7D00000 // LDRB Rd,[Rb,Ro]
|
||||||
*ainstr |= (tinstr & 0x00FF);
|
};
|
||||||
}
|
|
||||||
else if ((tinstr & 0x0F00) != 0x0E00) {
|
*ainstr = subset[(tinstr & 0x0C00) >> 10] // base
|
||||||
/* Format 16 */
|
|((tinstr & 0x0007) << (12 - 0)) // Rd
|
||||||
#if 0
|
|((tinstr & 0x0038) << (16 - 3)) // Rb
|
||||||
int doit = FALSE;
|
|((tinstr & 0x01C0) >> 6); // Ro
|
||||||
/* TODO: Since we are doing a switch here, we could just add
|
|
||||||
the SWI and undefined instruction checks into this
|
} else {
|
||||||
switch to same on a couple of conditionals: */
|
ARMword subset[4] = {
|
||||||
switch ((tinstr & 0x0F00) >> 8) {
|
0xE18000B0, // STRH Rd,[Rb,Ro]
|
||||||
case EQ:
|
0xE19000D0, // LDRSB Rd,[Rb,Ro]
|
||||||
doit = ZFLAG;
|
0xE19000B0, // LDRH Rd,[Rb,Ro]
|
||||||
break;
|
0xE19000F0 // LDRSH Rd,[Rb,Ro]
|
||||||
case NE:
|
};
|
||||||
doit = !ZFLAG;
|
*ainstr = subset[(tinstr & 0x0C00) >> 10] // base
|
||||||
break;
|
|((tinstr & 0x0007) << (12 - 0)) // Rd
|
||||||
case VS:
|
|((tinstr & 0x0038) << (16 - 3)) // Rb
|
||||||
doit = VFLAG;
|
|((tinstr & 0x01C0) >> 6); // Ro
|
||||||
break;
|
}
|
||||||
case VC:
|
break;
|
||||||
doit = !VFLAG;
|
|
||||||
break;
|
case 12: // STR Rd,[Rb,#imm5]
|
||||||
case MI:
|
case 13: // LDR Rd,[Rb,#imm5]
|
||||||
doit = NFLAG;
|
case 14: // STRB Rd,[Rb,#imm5]
|
||||||
break;
|
case 15: // LDRB Rd,[Rb,#imm5]
|
||||||
case PL:
|
{
|
||||||
doit = !NFLAG;
|
ARMword subset[4] = {
|
||||||
break;
|
0xE5800000, // STR Rd,[Rb,#imm5]
|
||||||
case CS:
|
0xE5900000, // LDR Rd,[Rb,#imm5]
|
||||||
doit = CFLAG;
|
0xE5C00000, // STRB Rd,[Rb,#imm5]
|
||||||
break;
|
0xE5D00000 // LDRB Rd,[Rb,#imm5]
|
||||||
case CC:
|
};
|
||||||
doit = !CFLAG;
|
// The offset range defends on whether we are transferring a byte or word value:
|
||||||
break;
|
*ainstr = subset[(tinstr & 0x1800) >> 11] // base
|
||||||
case HI:
|
|((tinstr & 0x0007) << (12 - 0)) // Rd
|
||||||
doit = (CFLAG && !ZFLAG);
|
|((tinstr & 0x0038) << (16 - 3)) // Rb
|
||||||
break;
|
|((tinstr & 0x07C0) >> (6 - ((tinstr & (1 << 12)) ? 0 : 2))); // off5
|
||||||
case LS:
|
}
|
||||||
doit = (!CFLAG || ZFLAG);
|
break;
|
||||||
break;
|
|
||||||
case GE:
|
case 16: // STRH Rd,[Rb,#imm5]
|
||||||
doit = ((!NFLAG && !VFLAG)
|
case 17: // LDRH Rd,[Rb,#imm5]
|
||||||
|| (NFLAG && VFLAG));
|
*ainstr = ((tinstr & (1 << 11)) // base
|
||||||
break;
|
? 0xE1D000B0 // LDRH
|
||||||
case LT:
|
: 0xE1C000B0) // STRH
|
||||||
doit = ((NFLAG && !VFLAG)
|
|((tinstr & 0x0007) << (12 - 0)) // Rd
|
||||||
|| (!NFLAG && VFLAG));
|
|((tinstr & 0x0038) << (16 - 3)) // Rb
|
||||||
break;
|
|((tinstr & 0x01C0) >> (6 - 1)) // off5, low nibble
|
||||||
case GT:
|
|((tinstr & 0x0600) >> (9 - 8)); // off5, high nibble
|
||||||
doit = ((!NFLAG && !VFLAG && !ZFLAG)
|
break;
|
||||||
|| (NFLAG && VFLAG && !ZFLAG));
|
|
||||||
break;
|
case 18: // STR Rd,[SP,#imm8]
|
||||||
case LE:
|
case 19: // LDR Rd,[SP,#imm8]
|
||||||
doit = ((NFLAG && !VFLAG)
|
*ainstr = ((tinstr & (1 << 11)) // base
|
||||||
|| (!NFLAG && VFLAG)) || ZFLAG;
|
? 0xE59D0000 // LDR
|
||||||
break;
|
: 0xE58D0000) // STR
|
||||||
}
|
|((tinstr & 0x0700) << (12 - 8)) // Rd
|
||||||
if (doit) {
|
|((tinstr & 0x00FF) << 2); // off8
|
||||||
state->Reg[15] = (pc + 4
|
break;
|
||||||
+ (((tinstr & 0x7F) << 1)
|
|
||||||
| ((tinstr & (1 << 7)) ?
|
case 20: // ADD Rd,PC,#imm8
|
||||||
0xFFFFFF00 : 0)));
|
case 21: // ADD Rd,SP,#imm8
|
||||||
FLUSHPIPE;
|
|
||||||
}
|
if ((tinstr & (1 << 11)) == 0) {
|
||||||
#endif
|
|
||||||
valid = t_branch;
|
// NOTE: The PC value used here should by word aligned. We encode shift-left-by-2 in the
|
||||||
}
|
// rotate immediate field, so no shift of off8 is needed.
|
||||||
else /* UNDEFINED : cc=1110(AL) uses different format */
|
|
||||||
valid = t_undefined;
|
*ainstr = 0xE28F0F00 // base
|
||||||
break;
|
| ((tinstr & 0x0700) << (12 - 8)) // Rd
|
||||||
case 28: /* B */
|
|(tinstr & 0x00FF); // off8
|
||||||
/* Format 18 */
|
} else {
|
||||||
#if 0
|
// We encode shift-left-by-2 in the rotate immediate field, so no shift of off8 is needed.
|
||||||
state->Reg[15] = (pc + 4 + (((tinstr & 0x3FF) << 1)
|
*ainstr = 0xE28D0F00 // base
|
||||||
| ((tinstr & (1 << 10)) ?
|
| ((tinstr & 0x0700) << (12 - 8)) // Rd
|
||||||
0xFFFFF800 : 0)));
|
|(tinstr & 0x00FF); // off8
|
||||||
#endif
|
}
|
||||||
//FLUSHPIPE;
|
break;
|
||||||
valid = t_branch;
|
|
||||||
break;
|
case 22:
|
||||||
case 29:
|
case 23:
|
||||||
if(tinstr & 0x1)
|
if ((tinstr & 0x0F00) == 0x0000) {
|
||||||
valid = t_undefined;
|
// NOTE: The instruction contains a shift left of 2 equivalent (implemented as ROR #30):
|
||||||
else{
|
*ainstr = ((tinstr & (1 << 7)) // base
|
||||||
/* BLX 1 for armv5t and above */
|
? 0xE24DDF00 // SUB
|
||||||
//printf("In %s, After BLX(1),LR=0x%x,PC=0x%x, offset=0x%x\n", __FUNCTION__, state->Reg[14], state->Reg[15], (tinstr &0x7FF) << 1);
|
: 0xE28DDF00) // ADD
|
||||||
valid = t_branch;
|
|(tinstr & 0x007F); // off7
|
||||||
}
|
} else if ((tinstr & 0x0F00) == 0x0e00)
|
||||||
break;
|
*ainstr = 0xEF000000 | SWI_Breakpoint;
|
||||||
case 30: /* BL instruction 1 */
|
else {
|
||||||
/* Format 19 */
|
ARMword subset[4] = {
|
||||||
/* There is no single ARM instruction equivalent for this Thumb
|
0xE92D0000, // STMDB sp!,{rlist}
|
||||||
instruction. To keep the simulation simple (from the user
|
0xE92D4000, // STMDB sp!,{rlist,lr}
|
||||||
perspective) we check if the following instruction is the
|
0xE8BD0000, // LDMIA sp!,{rlist}
|
||||||
second half of this BL, and if it is we simulate it
|
0xE8BD8000 // LDMIA sp!,{rlist,pc}
|
||||||
immediately. */
|
};
|
||||||
valid = t_branch;
|
*ainstr = subset[((tinstr & (1 << 11)) >> 10) | ((tinstr & (1 << 8)) >> 8)] // base
|
||||||
break;
|
|(tinstr & 0x00FF); // mask8
|
||||||
case 31: /* BL instruction 2 */
|
}
|
||||||
/* Format 19 */
|
break;
|
||||||
/* There is no single ARM instruction equivalent for this
|
|
||||||
instruction. Also, it should only ever be matched with the
|
case 24: // STMIA
|
||||||
fmt19 "BL instruction 1" instruction. However, we do allow
|
case 25: // LDMIA
|
||||||
the simulation of it on its own, with undefined results if
|
*ainstr = ((tinstr & (1 << 11)) // base
|
||||||
r14 is not suitably initialised. */
|
? 0xE8B00000 // LDMIA
|
||||||
{
|
: 0xE8A00000) // STMIA
|
||||||
#if 0
|
|((tinstr & 0x0700) << (16 - 8)) // Rb
|
||||||
ARMword tmp = (pc + 2);
|
|(tinstr & 0x00FF); // mask8
|
||||||
state->Reg[15] =
|
break;
|
||||||
(state->Reg[14] + ((tinstr & 0x07FF) << 1));
|
|
||||||
state->Reg[14] = (tmp | 1);
|
case 26: // Bcc
|
||||||
#endif
|
case 27: // Bcc/SWI
|
||||||
valid = t_branch;
|
if ((tinstr & 0x0F00) == 0x0F00) {
|
||||||
}
|
// Format 17 : SWI
|
||||||
break;
|
*ainstr = 0xEF000000;
|
||||||
}
|
// Breakpoint must be handled specially.
|
||||||
*inst_size = 2;
|
if ((tinstr & 0x00FF) == 0x18)
|
||||||
return valid;
|
*ainstr |= ((tinstr & 0x00FF) << 16);
|
||||||
|
// New breakpoint value. See gdb/arm-tdep.c
|
||||||
|
else if ((tinstr & 0x00FF) == 0xFE)
|
||||||
|
*ainstr |= SWI_Breakpoint;
|
||||||
|
else
|
||||||
|
*ainstr |= (tinstr & 0x00FF);
|
||||||
|
} else if ((tinstr & 0x0F00) != 0x0E00)
|
||||||
|
valid = t_branch;
|
||||||
|
else // UNDEFINED : cc=1110(AL) uses different format
|
||||||
|
valid = t_undefined;
|
||||||
|
|
||||||
|
break;
|
||||||
|
|
||||||
|
case 28: // B
|
||||||
|
valid = t_branch;
|
||||||
|
break;
|
||||||
|
|
||||||
|
case 29:
|
||||||
|
if(tinstr & 0x1)
|
||||||
|
valid = t_undefined;
|
||||||
|
else
|
||||||
|
valid = t_branch;
|
||||||
|
break;
|
||||||
|
|
||||||
|
case 30: // BL instruction 1
|
||||||
|
|
||||||
|
// There is no single ARM instruction equivalent for this Thumb instruction. To keep the
|
||||||
|
// simulation simple (from the user perspective) we check if the following instruction is
|
||||||
|
// the second half of this BL, and if it is we simulate it immediately
|
||||||
|
|
||||||
|
valid = t_branch;
|
||||||
|
break;
|
||||||
|
|
||||||
|
case 31: // BL instruction 2
|
||||||
|
|
||||||
|
// There is no single ARM instruction equivalent for this instruction. Also, it should only
|
||||||
|
// ever be matched with the fmt19 "BL instruction 1" instruction. However, we do allow the
|
||||||
|
// simulation of it on its own, with undefined results if r14 is not suitably initialised.
|
||||||
|
|
||||||
|
valid = t_branch;
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
*inst_size = 2;
|
||||||
|
|
||||||
|
return valid;
|
||||||
}
|
}
|
||||||
|
|
|
||||||
|
|
@ -56,7 +56,6 @@ ARM_INST_PTR INTERPRETER_TRANSLATE(vmla)(unsigned int inst, int index)
|
||||||
#ifdef VFP_INTERPRETER_IMPL
|
#ifdef VFP_INTERPRETER_IMPL
|
||||||
VMLA_INST:
|
VMLA_INST:
|
||||||
{
|
{
|
||||||
INC_ICOUNTER;
|
|
||||||
if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
|
if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
|
||||||
CHECK_VFP_ENABLED;
|
CHECK_VFP_ENABLED;
|
||||||
|
|
||||||
|
|
@ -180,7 +179,6 @@ ARM_INST_PTR INTERPRETER_TRANSLATE(vmls)(unsigned int inst, int index)
|
||||||
#ifdef VFP_INTERPRETER_IMPL
|
#ifdef VFP_INTERPRETER_IMPL
|
||||||
VMLS_INST:
|
VMLS_INST:
|
||||||
{
|
{
|
||||||
INC_ICOUNTER;
|
|
||||||
if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
|
if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
|
||||||
CHECK_VFP_ENABLED;
|
CHECK_VFP_ENABLED;
|
||||||
|
|
||||||
|
|
@ -304,7 +302,6 @@ ARM_INST_PTR INTERPRETER_TRANSLATE(vnmla)(unsigned int inst, int index)
|
||||||
#ifdef VFP_INTERPRETER_IMPL
|
#ifdef VFP_INTERPRETER_IMPL
|
||||||
VNMLA_INST:
|
VNMLA_INST:
|
||||||
{
|
{
|
||||||
INC_ICOUNTER;
|
|
||||||
if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
|
if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
|
||||||
CHECK_VFP_ENABLED;
|
CHECK_VFP_ENABLED;
|
||||||
|
|
||||||
|
|
@ -430,7 +427,6 @@ ARM_INST_PTR INTERPRETER_TRANSLATE(vnmls)(unsigned int inst, int index)
|
||||||
#ifdef VFP_INTERPRETER_IMPL
|
#ifdef VFP_INTERPRETER_IMPL
|
||||||
VNMLS_INST:
|
VNMLS_INST:
|
||||||
{
|
{
|
||||||
INC_ICOUNTER;
|
|
||||||
if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
|
if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
|
||||||
CHECK_VFP_ENABLED;
|
CHECK_VFP_ENABLED;
|
||||||
|
|
||||||
|
|
@ -554,7 +550,6 @@ ARM_INST_PTR INTERPRETER_TRANSLATE(vnmul)(unsigned int inst, int index)
|
||||||
#ifdef VFP_INTERPRETER_IMPL
|
#ifdef VFP_INTERPRETER_IMPL
|
||||||
VNMUL_INST:
|
VNMUL_INST:
|
||||||
{
|
{
|
||||||
INC_ICOUNTER;
|
|
||||||
if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
|
if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
|
||||||
CHECK_VFP_ENABLED;
|
CHECK_VFP_ENABLED;
|
||||||
|
|
||||||
|
|
@ -669,7 +664,6 @@ ARM_INST_PTR INTERPRETER_TRANSLATE(vmul)(unsigned int inst, int index)
|
||||||
#ifdef VFP_INTERPRETER_IMPL
|
#ifdef VFP_INTERPRETER_IMPL
|
||||||
VMUL_INST:
|
VMUL_INST:
|
||||||
{
|
{
|
||||||
INC_ICOUNTER;
|
|
||||||
if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
|
if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
|
||||||
CHECK_VFP_ENABLED;
|
CHECK_VFP_ENABLED;
|
||||||
|
|
||||||
|
|
@ -797,7 +791,6 @@ ARM_INST_PTR INTERPRETER_TRANSLATE(vadd)(unsigned int inst, int index)
|
||||||
#ifdef VFP_INTERPRETER_IMPL
|
#ifdef VFP_INTERPRETER_IMPL
|
||||||
VADD_INST:
|
VADD_INST:
|
||||||
{
|
{
|
||||||
INC_ICOUNTER;
|
|
||||||
if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
|
if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
|
||||||
CHECK_VFP_ENABLED;
|
CHECK_VFP_ENABLED;
|
||||||
|
|
||||||
|
|
@ -919,7 +912,6 @@ ARM_INST_PTR INTERPRETER_TRANSLATE(vsub)(unsigned int inst, int index)
|
||||||
#ifdef VFP_INTERPRETER_IMPL
|
#ifdef VFP_INTERPRETER_IMPL
|
||||||
VSUB_INST:
|
VSUB_INST:
|
||||||
{
|
{
|
||||||
INC_ICOUNTER;
|
|
||||||
if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
|
if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
|
||||||
CHECK_VFP_ENABLED;
|
CHECK_VFP_ENABLED;
|
||||||
|
|
||||||
|
|
@ -1039,7 +1031,6 @@ ARM_INST_PTR INTERPRETER_TRANSLATE(vdiv)(unsigned int inst, int index)
|
||||||
#ifdef VFP_INTERPRETER_IMPL
|
#ifdef VFP_INTERPRETER_IMPL
|
||||||
VDIV_INST:
|
VDIV_INST:
|
||||||
{
|
{
|
||||||
INC_ICOUNTER;
|
|
||||||
if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
|
if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
|
||||||
CHECK_VFP_ENABLED;
|
CHECK_VFP_ENABLED;
|
||||||
|
|
||||||
|
|
@ -1167,7 +1158,6 @@ ARM_INST_PTR INTERPRETER_TRANSLATE(vmovi)(unsigned int inst, int index)
|
||||||
#ifdef VFP_INTERPRETER_IMPL
|
#ifdef VFP_INTERPRETER_IMPL
|
||||||
VMOVI_INST:
|
VMOVI_INST:
|
||||||
{
|
{
|
||||||
INC_ICOUNTER;
|
|
||||||
if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
|
if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
|
||||||
CHECK_VFP_ENABLED;
|
CHECK_VFP_ENABLED;
|
||||||
|
|
||||||
|
|
@ -1256,7 +1246,6 @@ ARM_INST_PTR INTERPRETER_TRANSLATE(vmovr)(unsigned int inst, int index)
|
||||||
#ifdef VFP_INTERPRETER_IMPL
|
#ifdef VFP_INTERPRETER_IMPL
|
||||||
VMOVR_INST:
|
VMOVR_INST:
|
||||||
{
|
{
|
||||||
INC_ICOUNTER;
|
|
||||||
if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
|
if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
|
||||||
CHECK_VFP_ENABLED;
|
CHECK_VFP_ENABLED;
|
||||||
|
|
||||||
|
|
@ -1338,7 +1327,6 @@ ARM_INST_PTR INTERPRETER_TRANSLATE(vabs)(unsigned int inst, int index)
|
||||||
#ifdef VFP_INTERPRETER_IMPL
|
#ifdef VFP_INTERPRETER_IMPL
|
||||||
VABS_INST:
|
VABS_INST:
|
||||||
{
|
{
|
||||||
INC_ICOUNTER;
|
|
||||||
if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
|
if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
|
||||||
CHECK_VFP_ENABLED;
|
CHECK_VFP_ENABLED;
|
||||||
|
|
||||||
|
|
@ -1447,7 +1435,6 @@ ARM_INST_PTR INTERPRETER_TRANSLATE(vneg)(unsigned int inst, int index)
|
||||||
#ifdef VFP_INTERPRETER_IMPL
|
#ifdef VFP_INTERPRETER_IMPL
|
||||||
VNEG_INST:
|
VNEG_INST:
|
||||||
{
|
{
|
||||||
INC_ICOUNTER;
|
|
||||||
if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
|
if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
|
||||||
CHECK_VFP_ENABLED;
|
CHECK_VFP_ENABLED;
|
||||||
|
|
||||||
|
|
@ -1555,7 +1542,6 @@ ARM_INST_PTR INTERPRETER_TRANSLATE(vsqrt)(unsigned int inst, int index)
|
||||||
#ifdef VFP_INTERPRETER_IMPL
|
#ifdef VFP_INTERPRETER_IMPL
|
||||||
VSQRT_INST:
|
VSQRT_INST:
|
||||||
{
|
{
|
||||||
INC_ICOUNTER;
|
|
||||||
if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
|
if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
|
||||||
CHECK_VFP_ENABLED;
|
CHECK_VFP_ENABLED;
|
||||||
|
|
||||||
|
|
@ -1651,7 +1637,6 @@ ARM_INST_PTR INTERPRETER_TRANSLATE(vcmp)(unsigned int inst, int index)
|
||||||
#ifdef VFP_INTERPRETER_IMPL
|
#ifdef VFP_INTERPRETER_IMPL
|
||||||
VCMP_INST:
|
VCMP_INST:
|
||||||
{
|
{
|
||||||
INC_ICOUNTER;
|
|
||||||
if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
|
if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
|
||||||
CHECK_VFP_ENABLED;
|
CHECK_VFP_ENABLED;
|
||||||
|
|
||||||
|
|
@ -1774,7 +1759,6 @@ ARM_INST_PTR INTERPRETER_TRANSLATE(vcmp2)(unsigned int inst, int index)
|
||||||
#ifdef VFP_INTERPRETER_IMPL
|
#ifdef VFP_INTERPRETER_IMPL
|
||||||
VCMP2_INST:
|
VCMP2_INST:
|
||||||
{
|
{
|
||||||
INC_ICOUNTER;
|
|
||||||
if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
|
if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
|
||||||
CHECK_VFP_ENABLED;
|
CHECK_VFP_ENABLED;
|
||||||
|
|
||||||
|
|
@ -1897,7 +1881,6 @@ ARM_INST_PTR INTERPRETER_TRANSLATE(vcvtbds)(unsigned int inst, int index)
|
||||||
#ifdef VFP_INTERPRETER_IMPL
|
#ifdef VFP_INTERPRETER_IMPL
|
||||||
VCVTBDS_INST:
|
VCVTBDS_INST:
|
||||||
{
|
{
|
||||||
INC_ICOUNTER;
|
|
||||||
if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
|
if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
|
||||||
CHECK_VFP_ENABLED;
|
CHECK_VFP_ENABLED;
|
||||||
|
|
||||||
|
|
@ -1994,7 +1977,6 @@ ARM_INST_PTR INTERPRETER_TRANSLATE(vcvtbff)(unsigned int inst, int index)
|
||||||
#ifdef VFP_INTERPRETER_IMPL
|
#ifdef VFP_INTERPRETER_IMPL
|
||||||
VCVTBFF_INST:
|
VCVTBFF_INST:
|
||||||
{
|
{
|
||||||
INC_ICOUNTER;
|
|
||||||
if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
|
if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
|
||||||
CHECK_VFP_ENABLED;
|
CHECK_VFP_ENABLED;
|
||||||
|
|
||||||
|
|
@ -2070,7 +2052,6 @@ ARM_INST_PTR INTERPRETER_TRANSLATE(vcvtbfi)(unsigned int inst, int index)
|
||||||
#ifdef VFP_INTERPRETER_IMPL
|
#ifdef VFP_INTERPRETER_IMPL
|
||||||
VCVTBFI_INST:
|
VCVTBFI_INST:
|
||||||
{
|
{
|
||||||
INC_ICOUNTER;
|
|
||||||
if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
|
if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
|
||||||
CHECK_VFP_ENABLED;
|
CHECK_VFP_ENABLED;
|
||||||
|
|
||||||
|
|
@ -2243,7 +2224,6 @@ ARM_INST_PTR INTERPRETER_TRANSLATE(vmovbrs)(unsigned int inst, int index)
|
||||||
#ifdef VFP_INTERPRETER_IMPL
|
#ifdef VFP_INTERPRETER_IMPL
|
||||||
VMOVBRS_INST:
|
VMOVBRS_INST:
|
||||||
{
|
{
|
||||||
INC_ICOUNTER;
|
|
||||||
if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
|
if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
|
||||||
CHECK_VFP_ENABLED;
|
CHECK_VFP_ENABLED;
|
||||||
|
|
||||||
|
|
@ -2323,7 +2303,6 @@ ARM_INST_PTR INTERPRETER_TRANSLATE(vmsr)(unsigned int inst, int index)
|
||||||
#ifdef VFP_INTERPRETER_IMPL
|
#ifdef VFP_INTERPRETER_IMPL
|
||||||
VMSR_INST:
|
VMSR_INST:
|
||||||
{
|
{
|
||||||
INC_ICOUNTER;
|
|
||||||
if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
|
if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
|
||||||
/* FIXME: special case for access to FPSID and FPEXC, VFP must be disabled ,
|
/* FIXME: special case for access to FPSID and FPEXC, VFP must be disabled ,
|
||||||
and in privilegied mode */
|
and in privilegied mode */
|
||||||
|
|
@ -2426,7 +2405,6 @@ ARM_INST_PTR INTERPRETER_TRANSLATE(vmovbrc)(unsigned int inst, int index)
|
||||||
#ifdef VFP_INTERPRETER_IMPL
|
#ifdef VFP_INTERPRETER_IMPL
|
||||||
VMOVBRC_INST:
|
VMOVBRC_INST:
|
||||||
{
|
{
|
||||||
INC_ICOUNTER;
|
|
||||||
if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
|
if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
|
||||||
CHECK_VFP_ENABLED;
|
CHECK_VFP_ENABLED;
|
||||||
|
|
||||||
|
|
@ -2493,7 +2471,6 @@ ARM_INST_PTR INTERPRETER_TRANSLATE(vmrs)(unsigned int inst, int index)
|
||||||
#ifdef VFP_INTERPRETER_IMPL
|
#ifdef VFP_INTERPRETER_IMPL
|
||||||
VMRS_INST:
|
VMRS_INST:
|
||||||
{
|
{
|
||||||
INC_ICOUNTER;
|
|
||||||
if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
|
if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
|
||||||
/* FIXME: special case for access to FPSID and FPEXC, VFP must be disabled,
|
/* FIXME: special case for access to FPSID and FPEXC, VFP must be disabled,
|
||||||
and in privilegied mode */
|
and in privilegied mode */
|
||||||
|
|
@ -2657,7 +2634,6 @@ ARM_INST_PTR INTERPRETER_TRANSLATE(vmovbcr)(unsigned int inst, int index)
|
||||||
#ifdef VFP_INTERPRETER_IMPL
|
#ifdef VFP_INTERPRETER_IMPL
|
||||||
VMOVBCR_INST:
|
VMOVBCR_INST:
|
||||||
{
|
{
|
||||||
INC_ICOUNTER;
|
|
||||||
if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
|
if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
|
||||||
CHECK_VFP_ENABLED;
|
CHECK_VFP_ENABLED;
|
||||||
|
|
||||||
|
|
@ -2733,7 +2709,6 @@ ARM_INST_PTR INTERPRETER_TRANSLATE(vmovbrrss)(unsigned int inst, int index)
|
||||||
#ifdef VFP_INTERPRETER_IMPL
|
#ifdef VFP_INTERPRETER_IMPL
|
||||||
VMOVBRRSS_INST:
|
VMOVBRRSS_INST:
|
||||||
{
|
{
|
||||||
INC_ICOUNTER;
|
|
||||||
if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
|
if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
|
||||||
CHECK_VFP_ENABLED;
|
CHECK_VFP_ENABLED;
|
||||||
|
|
||||||
|
|
@ -2803,7 +2778,6 @@ ARM_INST_PTR INTERPRETER_TRANSLATE(vmovbrrd)(unsigned int inst, int index)
|
||||||
#ifdef VFP_INTERPRETER_IMPL
|
#ifdef VFP_INTERPRETER_IMPL
|
||||||
VMOVBRRD_INST:
|
VMOVBRRD_INST:
|
||||||
{
|
{
|
||||||
INC_ICOUNTER;
|
|
||||||
if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
|
if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
|
||||||
CHECK_VFP_ENABLED;
|
CHECK_VFP_ENABLED;
|
||||||
|
|
||||||
|
|
@ -2895,7 +2869,6 @@ ARM_INST_PTR INTERPRETER_TRANSLATE(vstr)(unsigned int inst, int index)
|
||||||
#ifdef VFP_INTERPRETER_IMPL
|
#ifdef VFP_INTERPRETER_IMPL
|
||||||
VSTR_INST:
|
VSTR_INST:
|
||||||
{
|
{
|
||||||
INC_ICOUNTER;
|
|
||||||
if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
|
if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
|
||||||
CHECK_VFP_ENABLED;
|
CHECK_VFP_ENABLED;
|
||||||
|
|
||||||
|
|
@ -3037,7 +3010,6 @@ ARM_INST_PTR INTERPRETER_TRANSLATE(vpush)(unsigned int inst, int index)
|
||||||
#ifdef VFP_INTERPRETER_IMPL
|
#ifdef VFP_INTERPRETER_IMPL
|
||||||
VPUSH_INST:
|
VPUSH_INST:
|
||||||
{
|
{
|
||||||
INC_ICOUNTER;
|
|
||||||
if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
|
if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
|
||||||
CHECK_VFP_ENABLED;
|
CHECK_VFP_ENABLED;
|
||||||
|
|
||||||
|
|
@ -3204,7 +3176,6 @@ ARM_INST_PTR INTERPRETER_TRANSLATE(vstm)(unsigned int inst, int index)
|
||||||
#ifdef VFP_INTERPRETER_IMPL
|
#ifdef VFP_INTERPRETER_IMPL
|
||||||
VSTM_INST: /* encoding 1 */
|
VSTM_INST: /* encoding 1 */
|
||||||
{
|
{
|
||||||
INC_ICOUNTER;
|
|
||||||
if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
|
if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
|
||||||
CHECK_VFP_ENABLED;
|
CHECK_VFP_ENABLED;
|
||||||
|
|
||||||
|
|
@ -3392,7 +3363,6 @@ ARM_INST_PTR INTERPRETER_TRANSLATE(vpop)(unsigned int inst, int index)
|
||||||
#ifdef VFP_INTERPRETER_IMPL
|
#ifdef VFP_INTERPRETER_IMPL
|
||||||
VPOP_INST:
|
VPOP_INST:
|
||||||
{
|
{
|
||||||
INC_ICOUNTER;
|
|
||||||
if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
|
if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
|
||||||
CHECK_VFP_ENABLED;
|
CHECK_VFP_ENABLED;
|
||||||
|
|
||||||
|
|
@ -3573,7 +3543,6 @@ ARM_INST_PTR INTERPRETER_TRANSLATE(vldr)(unsigned int inst, int index)
|
||||||
#ifdef VFP_INTERPRETER_IMPL
|
#ifdef VFP_INTERPRETER_IMPL
|
||||||
VLDR_INST:
|
VLDR_INST:
|
||||||
{
|
{
|
||||||
INC_ICOUNTER;
|
|
||||||
if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
|
if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
|
||||||
CHECK_VFP_ENABLED;
|
CHECK_VFP_ENABLED;
|
||||||
|
|
||||||
|
|
@ -3737,7 +3706,6 @@ ARM_INST_PTR INTERPRETER_TRANSLATE(vldm)(unsigned int inst, int index)
|
||||||
#ifdef VFP_INTERPRETER_IMPL
|
#ifdef VFP_INTERPRETER_IMPL
|
||||||
VLDM_INST:
|
VLDM_INST:
|
||||||
{
|
{
|
||||||
INC_ICOUNTER;
|
|
||||||
if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
|
if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
|
||||||
CHECK_VFP_ENABLED;
|
CHECK_VFP_ENABLED;
|
||||||
|
|
||||||
|
|
|
||||||
Loading…
Reference in a new issue