shader_ir: Implement BRX & BRA.CC
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c218ae4b02
commit
8a6fc529a9
6 changed files with 76 additions and 4 deletions
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@ -1367,6 +1367,20 @@ union Instruction {
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}
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} bra;
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union {
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BitField<20, 24, u64> target;
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BitField<5, 1, u64> constant_buffer;
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s32 GetBranchExtend() const {
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// Sign extend the branch target offset
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u32 mask = 1U << (24 - 1);
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u32 value = static_cast<u32>(target);
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// The branch offset is relative to the next instruction and is stored in bytes, so
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// divide it by the size of an instruction and add 1 to it.
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return static_cast<s32>((value ^ mask) - mask) / sizeof(Instruction) + 1;
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}
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} brx;
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union {
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BitField<39, 1, u64> emit; // EmitVertex
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BitField<40, 1, u64> cut; // EndPrimitive
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@ -1464,6 +1478,7 @@ public:
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BFE_IMM,
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BFI_IMM_R,
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BRA,
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BRX,
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PBK,
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LD_A,
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LD_L,
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@ -1738,6 +1753,7 @@ private:
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INST("111000101001----", Id::SSY, Type::Flow, "SSY"),
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INST("111000101010----", Id::PBK, Type::Flow, "PBK"),
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INST("111000100100----", Id::BRA, Type::Flow, "BRA"),
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INST("111000100101----", Id::BRX, Type::Flow, "BRX"),
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INST("1111000011111---", Id::SYNC, Type::Flow, "SYNC"),
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INST("111000110100---", Id::BRK, Type::Flow, "BRK"),
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INST("111000110000----", Id::EXIT, Type::Flow, "EXIT"),
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@ -1555,6 +1555,14 @@ private:
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return {};
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}
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std::string BranchIndirect(Operation operation) {
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const std::string op_a = VisitOperand(operation, 0, Type::Uint);
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code.AddLine("jmp_to = {};", op_a);
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code.AddLine("break;");
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return {};
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}
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std::string PushFlowStack(Operation operation) {
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const auto stack = std::get<MetaStackClass>(operation.GetMeta());
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const auto target = std::get_if<ImmediateNode>(&*operation[0]);
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@ -1789,6 +1797,7 @@ private:
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&GLSLDecompiler::ImageStore,
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&GLSLDecompiler::Branch,
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&GLSLDecompiler::BranchIndirect,
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&GLSLDecompiler::PushFlowStack,
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&GLSLDecompiler::PopFlowStack,
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&GLSLDecompiler::Exit,
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@ -949,6 +949,14 @@ private:
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return {};
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}
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Id BranchIndirect(Operation operation) {
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const Id op_a = VisitOperand<Type::Uint>(operation, 0);
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Emit(OpStore(jmp_to, op_a));
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BranchingOp([&]() { Emit(OpBranch(continue_label)); });
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return {};
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}
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Id PushFlowStack(Operation operation) {
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const auto target = std::get_if<ImmediateNode>(&*operation[0]);
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ASSERT(target);
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@ -1334,6 +1342,7 @@ private:
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&SPIRVDecompiler::ImageStore,
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&SPIRVDecompiler::Branch,
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&SPIRVDecompiler::BranchIndirect,
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&SPIRVDecompiler::PushFlowStack,
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&SPIRVDecompiler::PopFlowStack,
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&SPIRVDecompiler::Exit,
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@ -284,6 +284,9 @@ ParseResult ParseCode(CFGRebuildState& state, u32 address, ParseInfo& parse_info
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state.pbk_labels.emplace(offset, target);
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break;
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}
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case OpCode::Id::BRX: {
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return ParseResult::AbnormalFlow;
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}
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default:
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break;
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}
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@ -91,11 +91,45 @@ u32 ShaderIR::DecodeOther(NodeBlock& bb, u32 pc) {
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break;
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}
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case OpCode::Id::BRA: {
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UNIMPLEMENTED_IF_MSG(instr.bra.constant_buffer != 0,
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"BRA with constant buffers are not implemented");
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Node branch;
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if (instr.bra.constant_buffer == 0) {
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const u32 target = pc + instr.bra.GetBranchTarget();
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branch = Operation(OperationCode::Branch, Immediate(target));
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} else {
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const u32 target = pc + 1;
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const Node op_a = GetConstBuffer(instr.cbuf36.index, instr.cbuf36.GetOffset());
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const Node convert = SignedOperation(OperationCode::IArithmeticShiftRight,
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true, PRECISE, op_a, Immediate(3));
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const Node operand = Operation(OperationCode::IAdd, PRECISE, convert, Immediate(target));
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branch = Operation(OperationCode::BranchIndirect, convert);
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}
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const u32 target = pc + instr.bra.GetBranchTarget();
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const Node branch = Operation(OperationCode::Branch, Immediate(target));
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const Tegra::Shader::ConditionCode cc = instr.flow_condition_code;
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if (cc != Tegra::Shader::ConditionCode::T) {
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bb.push_back(Conditional(GetConditionCode(cc), {branch}));
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} else {
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bb.push_back(branch);
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}
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break;
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}
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case OpCode::Id::BRX: {
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Node operand;
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if (instr.brx.constant_buffer != 0) {
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const s32 target = pc + 1;
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const Node index = GetRegister(instr.gpr8);
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const Node op_a =
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GetConstBufferIndirect(instr.cbuf36.index, instr.cbuf36.GetOffset() + 0, index);
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const Node convert = SignedOperation(OperationCode::IArithmeticShiftRight,
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true, PRECISE, op_a, Immediate(3));
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operand = Operation(OperationCode::IAdd, PRECISE, convert, Immediate(target));
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} else {
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const s32 target = pc + instr.brx.GetBranchExtend();
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const Node op_a = GetRegister(instr.gpr8);
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const Node convert = SignedOperation(OperationCode::IArithmeticShiftRight,
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true, PRECISE, op_a, Immediate(3));
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operand = Operation(OperationCode::IAdd, PRECISE, convert, Immediate(target));
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}
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const Node branch = Operation(OperationCode::BranchIndirect, operand);
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const Tegra::Shader::ConditionCode cc = instr.flow_condition_code;
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if (cc != Tegra::Shader::ConditionCode::T) {
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@ -149,6 +149,7 @@ enum class OperationCode {
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ImageStore, /// (MetaImage, float[N] coords) -> void
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Branch, /// (uint branch_target) -> void
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BranchIndirect,/// (uint branch_target) -> void
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PushFlowStack, /// (uint branch_target) -> void
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PopFlowStack, /// () -> void
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Exit, /// () -> void
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