fixed_pipeline_state: Pack rasterizer state
Reduce FixedPipelineState's size to 600 bytes.
This commit is contained in:
ReinUsesLisp
parent
7790144a55
commit
548dd27f45
4 changed files with 157 additions and 165 deletions
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@ -2,6 +2,7 @@
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#include <cstring>
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#include <tuple>
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#include <boost/functional/hash.hpp>
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@ -12,6 +13,31 @@
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namespace Vulkan {
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namespace {
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constexpr std::size_t POINT = 0;
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constexpr std::size_t LINE = 1;
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constexpr std::size_t POLYGON = 2;
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constexpr std::array POLYGON_OFFSET_ENABLE_LUT = {
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POINT, // Points
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LINE, // Lines
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LINE, // LineLoop
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LINE, // LineStrip
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POLYGON, // Triangles
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POLYGON, // TriangleStrip
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POLYGON, // TriangleFan
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POLYGON, // Quads
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POLYGON, // QuadStrip
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POLYGON, // Polygon
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LINE, // LinesAdjacency
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LINE, // LineStripAdjacency
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POLYGON, // TrianglesAdjacency
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POLYGON, // TriangleStripAdjacency
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POLYGON, // Patches
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};
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} // Anonymous namespace
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void FixedPipelineState::DepthStencil::Fill(const Maxwell& regs) noexcept {
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raw = 0;
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front.action_stencil_fail.Assign(PackStencilOp(regs.stencil_front_op_fail));
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@ -36,14 +62,41 @@ void FixedPipelineState::DepthStencil::Fill(const Maxwell& regs) noexcept {
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depth_test_func.Assign(PackComparisonOp(regs.depth_test_func));
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}
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namespace {
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void FixedPipelineState::Rasterizer::Fill(const Maxwell& regs) noexcept {
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const auto& clip = regs.view_volume_clip_control;
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const std::array enabled_lut = {regs.polygon_offset_point_enable,
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regs.polygon_offset_line_enable,
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regs.polygon_offset_fill_enable};
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const u32 topology_index = static_cast<u32>(regs.draw.topology.Value());
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constexpr FixedPipelineState::InputAssembly GetInputAssemblyState(const Maxwell& regs) {
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return FixedPipelineState::InputAssembly(
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regs.draw.topology, regs.primitive_restart.enabled,
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regs.draw.topology == Maxwell::PrimitiveTopology::Points ? regs.point_size : 0.0f);
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u32 packed_front_face = PackFrontFace(regs.front_face);
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if (regs.screen_y_control.triangle_rast_flip != 0 &&
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regs.viewport_transform[0].scale_y > 0.0f) {
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// Flip front face
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packed_front_face = 1 - packed_front_face;
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}
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raw = 0;
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topology.Assign(topology_index);
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primitive_restart_enable.Assign(regs.primitive_restart.enabled != 0 ? 1 : 0);
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cull_enable.Assign(regs.cull_test_enabled != 0 ? 1 : 0);
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depth_bias_enable.Assign(enabled_lut[POLYGON_OFFSET_ENABLE_LUT[topology_index]] != 0 ? 1 : 0);
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depth_clamp_enable.Assign(clip.depth_clamp_near == 1 || clip.depth_clamp_far == 1 ? 1 : 0);
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ndc_minus_one_to_one.Assign(regs.depth_mode == Maxwell::DepthMode::MinusOneToOne ? 1 : 0);
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cull_face.Assign(PackCullFace(regs.cull_face));
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front_face.Assign(packed_front_face);
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polygon_mode.Assign(PackPolygonMode(regs.polygon_mode_front));
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patch_control_points_minus_one.Assign(regs.patch_vertices - 1);
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tessellation_primitive.Assign(static_cast<u32>(regs.tess_mode.prim.Value()));
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tessellation_spacing.Assign(static_cast<u32>(regs.tess_mode.spacing.Value()));
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tessellation_clockwise.Assign(regs.tess_mode.cw.Value());
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logic_op_enable.Assign(regs.logic_op.enable != 0 ? 1 : 0);
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logic_op.Assign(PackLogicOp(regs.logic_op.operation));
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std::memcpy(&point_size, ®s.point_size, sizeof(point_size)); // TODO: C++20 std::bit_cast
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}
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namespace {
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constexpr FixedPipelineState::BlendingAttachment GetBlendingAttachmentState(
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const Maxwell& regs, std::size_t render_target) {
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const auto& mask = regs.color_mask[regs.color_mask_common ? 0 : render_target];
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@ -86,56 +139,6 @@ constexpr FixedPipelineState::ColorBlending GetColorBlendingState(const Maxwell&
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GetBlendingAttachmentState(regs, 6), GetBlendingAttachmentState(regs, 7)});
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}
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constexpr FixedPipelineState::Tessellation GetTessellationState(const Maxwell& regs) {
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return FixedPipelineState::Tessellation(regs.patch_vertices, regs.tess_mode.prim,
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regs.tess_mode.spacing, regs.tess_mode.cw != 0);
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}
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constexpr std::size_t Point = 0;
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constexpr std::size_t Line = 1;
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constexpr std::size_t Polygon = 2;
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constexpr std::array PolygonOffsetEnableLUT = {
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Point, // Points
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Line, // Lines
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Line, // LineLoop
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Line, // LineStrip
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Polygon, // Triangles
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Polygon, // TriangleStrip
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Polygon, // TriangleFan
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Polygon, // Quads
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Polygon, // QuadStrip
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Polygon, // Polygon
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Line, // LinesAdjacency
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Line, // LineStripAdjacency
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Polygon, // TrianglesAdjacency
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Polygon, // TriangleStripAdjacency
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Polygon, // Patches
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};
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constexpr FixedPipelineState::Rasterizer GetRasterizerState(const Maxwell& regs) {
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const std::array enabled_lut = {regs.polygon_offset_point_enable,
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regs.polygon_offset_line_enable,
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regs.polygon_offset_fill_enable};
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const auto topology = static_cast<std::size_t>(regs.draw.topology.Value());
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const bool depth_bias_enabled = enabled_lut[PolygonOffsetEnableLUT[topology]];
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const auto& clip = regs.view_volume_clip_control;
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const bool depth_clamp_enabled = clip.depth_clamp_near == 1 || clip.depth_clamp_far == 1;
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Maxwell::FrontFace front_face = regs.front_face;
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if (regs.screen_y_control.triangle_rast_flip != 0 &&
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regs.viewport_transform[0].scale_y > 0.0f) {
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if (front_face == Maxwell::FrontFace::CounterClockWise)
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front_face = Maxwell::FrontFace::ClockWise;
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else if (front_face == Maxwell::FrontFace::ClockWise)
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front_face = Maxwell::FrontFace::CounterClockWise;
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}
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const bool gl_ndc = regs.depth_mode == Maxwell::DepthMode::MinusOneToOne;
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return FixedPipelineState::Rasterizer(regs.cull_test_enabled, depth_bias_enabled,
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depth_clamp_enabled, gl_ndc, regs.cull_face, front_face);
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}
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} // Anonymous namespace
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std::size_t FixedPipelineState::BlendingAttachment::Hash() const noexcept {
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@ -168,43 +171,14 @@ bool FixedPipelineState::VertexInput::operator==(const VertexInput& rhs) const n
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return std::memcmp(this, &rhs, sizeof *this) == 0;
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}
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std::size_t FixedPipelineState::InputAssembly::Hash() const noexcept {
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std::size_t point_size_int = 0;
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std::memcpy(&point_size_int, &point_size, sizeof(point_size));
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return (static_cast<std::size_t>(topology) << 24) ^ (point_size_int << 32) ^
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static_cast<std::size_t>(primitive_restart_enable);
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}
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bool FixedPipelineState::InputAssembly::operator==(const InputAssembly& rhs) const noexcept {
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return std::tie(topology, primitive_restart_enable, point_size) ==
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std::tie(rhs.topology, rhs.primitive_restart_enable, rhs.point_size);
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}
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std::size_t FixedPipelineState::Tessellation::Hash() const noexcept {
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return static_cast<std::size_t>(patch_control_points) ^
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(static_cast<std::size_t>(primitive) << 6) ^ (static_cast<std::size_t>(spacing) << 8) ^
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(static_cast<std::size_t>(clockwise) << 10);
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}
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bool FixedPipelineState::Tessellation::operator==(const Tessellation& rhs) const noexcept {
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return std::tie(patch_control_points, primitive, spacing, clockwise) ==
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std::tie(rhs.patch_control_points, rhs.primitive, rhs.spacing, rhs.clockwise);
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}
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std::size_t FixedPipelineState::Rasterizer::Hash() const noexcept {
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return static_cast<std::size_t>(cull_enable) ^
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(static_cast<std::size_t>(depth_bias_enable) << 1) ^
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(static_cast<std::size_t>(depth_clamp_enable) << 2) ^
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(static_cast<std::size_t>(ndc_minus_one_to_one) << 3) ^
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(static_cast<std::size_t>(cull_face) << 24) ^
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(static_cast<std::size_t>(front_face) << 48);
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u64 hash = static_cast<u64>(raw) << 32;
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std::memcpy(&hash, &point_size, sizeof(u32));
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return static_cast<std::size_t>(hash);
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}
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bool FixedPipelineState::Rasterizer::operator==(const Rasterizer& rhs) const noexcept {
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return std::tie(cull_enable, depth_bias_enable, depth_clamp_enable, ndc_minus_one_to_one,
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cull_face, front_face) ==
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std::tie(rhs.cull_enable, rhs.depth_bias_enable, rhs.depth_clamp_enable,
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rhs.ndc_minus_one_to_one, rhs.cull_face, rhs.front_face);
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return raw == rhs.raw && point_size == rhs.point_size;
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}
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std::size_t FixedPipelineState::DepthStencil::Hash() const noexcept {
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@ -231,8 +205,6 @@ bool FixedPipelineState::ColorBlending::operator==(const ColorBlending& rhs) con
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std::size_t FixedPipelineState::Hash() const noexcept {
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std::size_t hash = 0;
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boost::hash_combine(hash, vertex_input.Hash());
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boost::hash_combine(hash, input_assembly.Hash());
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boost::hash_combine(hash, tessellation.Hash());
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boost::hash_combine(hash, rasterizer.Hash());
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boost::hash_combine(hash, depth_stencil.Hash());
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boost::hash_combine(hash, color_blending.Hash());
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@ -240,17 +212,13 @@ std::size_t FixedPipelineState::Hash() const noexcept {
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}
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bool FixedPipelineState::operator==(const FixedPipelineState& rhs) const noexcept {
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return std::tie(vertex_input, input_assembly, tessellation, rasterizer, depth_stencil,
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color_blending) == std::tie(rhs.vertex_input, rhs.input_assembly,
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rhs.tessellation, rhs.rasterizer, rhs.depth_stencil,
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rhs.color_blending);
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return std::tie(vertex_input, rasterizer, depth_stencil, color_blending) ==
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std::tie(rhs.vertex_input, rhs.rasterizer, rhs.depth_stencil, rhs.color_blending);
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}
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FixedPipelineState GetFixedPipelineState(const Maxwell& regs) {
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FixedPipelineState fixed_state;
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fixed_state.input_assembly = GetInputAssemblyState(regs);
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fixed_state.tessellation = GetTessellationState(regs);
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fixed_state.rasterizer = GetRasterizerState(regs);
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fixed_state.rasterizer.Fill(regs);
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fixed_state.depth_stencil.Fill(regs);
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fixed_state.color_blending = GetColorBlendingState(regs);
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return fixed_state;
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@ -307,4 +275,41 @@ Maxwell::StencilOp FixedPipelineState::UnpackStencilOp(u32 packed) noexcept {
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return LUT[packed];
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}
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u32 FixedPipelineState::PackCullFace(Maxwell::CullFace cull) noexcept {
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// FrontAndBack is 0x408, by substracting 0x406 in it we get 2.
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// Individual cull faces are in 0x404 and 0x405, substracting 0x404 we get 0 and 1.
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const u32 value = static_cast<u32>(cull);
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return value - (value == 0x408 ? 0x406 : 0x404);
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}
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Maxwell::CullFace FixedPipelineState::UnpackCullFace(u32 packed) noexcept {
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static constexpr std::array LUT = {Maxwell::CullFace::Front, Maxwell::CullFace::Back,
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Maxwell::CullFace::FrontAndBack};
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return LUT[packed];
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}
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u32 FixedPipelineState::PackFrontFace(Maxwell::FrontFace face) noexcept {
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return static_cast<u32>(face) - 0x900;
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}
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Maxwell::FrontFace FixedPipelineState::UnpackFrontFace(u32 packed) noexcept {
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return static_cast<Maxwell::FrontFace>(packed + 0x900);
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}
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u32 FixedPipelineState::PackPolygonMode(Maxwell::PolygonMode mode) noexcept {
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return static_cast<u32>(mode) - 0x1B00;
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}
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Maxwell::PolygonMode FixedPipelineState::UnpackPolygonMode(u32 packed) noexcept {
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return static_cast<Maxwell::PolygonMode>(packed + 0x1B00);
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}
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u32 FixedPipelineState::PackLogicOp(Maxwell::LogicOperation op) noexcept {
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return static_cast<u32>(op) - 0x1500;
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}
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Maxwell::LogicOperation FixedPipelineState::UnpackLogicOp(u32 packed) noexcept {
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return static_cast<Maxwell::LogicOperation>(packed + 0x1500);
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}
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} // namespace Vulkan
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@ -30,6 +30,18 @@ struct FixedPipelineState {
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static u32 PackStencilOp(Maxwell::StencilOp op) noexcept;
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static Maxwell::StencilOp UnpackStencilOp(u32 packed) noexcept;
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static u32 PackCullFace(Maxwell::CullFace cull) noexcept;
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static Maxwell::CullFace UnpackCullFace(u32 packed) noexcept;
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static u32 PackFrontFace(Maxwell::FrontFace face) noexcept;
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static Maxwell::FrontFace UnpackFrontFace(u32 packed) noexcept;
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static u32 PackPolygonMode(Maxwell::PolygonMode mode) noexcept;
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static Maxwell::PolygonMode UnpackPolygonMode(u32 packed) noexcept;
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static u32 PackLogicOp(Maxwell::LogicOperation op) noexcept;
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static Maxwell::LogicOperation UnpackLogicOp(u32 packed) noexcept;
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struct BlendingAttachment {
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constexpr BlendingAttachment(bool enable, Maxwell::Blend::Equation rgb_equation,
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Maxwell::Blend::Factor src_rgb_func,
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@ -119,62 +131,30 @@ struct FixedPipelineState {
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};
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static_assert(IsHashable<VertexInput>);
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struct InputAssembly {
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constexpr InputAssembly(Maxwell::PrimitiveTopology topology, bool primitive_restart_enable,
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float point_size)
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: topology{topology}, primitive_restart_enable{primitive_restart_enable},
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point_size{point_size} {}
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InputAssembly() = default;
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Maxwell::PrimitiveTopology topology;
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bool primitive_restart_enable;
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float point_size;
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std::size_t Hash() const noexcept;
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bool operator==(const InputAssembly& rhs) const noexcept;
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bool operator!=(const InputAssembly& rhs) const noexcept {
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return !operator==(rhs);
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}
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};
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struct Tessellation {
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constexpr Tessellation(u32 patch_control_points, Maxwell::TessellationPrimitive primitive,
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Maxwell::TessellationSpacing spacing, bool clockwise)
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: patch_control_points{patch_control_points}, primitive{primitive}, spacing{spacing},
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clockwise{clockwise} {}
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Tessellation() = default;
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u32 patch_control_points;
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Maxwell::TessellationPrimitive primitive;
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Maxwell::TessellationSpacing spacing;
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bool clockwise;
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std::size_t Hash() const noexcept;
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bool operator==(const Tessellation& rhs) const noexcept;
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bool operator!=(const Tessellation& rhs) const noexcept {
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return !operator==(rhs);
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}
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};
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struct Rasterizer {
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constexpr Rasterizer(bool cull_enable, bool depth_bias_enable, bool depth_clamp_enable,
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bool ndc_minus_one_to_one, Maxwell::CullFace cull_face,
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Maxwell::FrontFace front_face)
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: cull_enable{cull_enable}, depth_bias_enable{depth_bias_enable},
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depth_clamp_enable{depth_clamp_enable}, ndc_minus_one_to_one{ndc_minus_one_to_one},
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cull_face{cull_face}, front_face{front_face} {}
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Rasterizer() = default;
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union {
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u32 raw;
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BitField<0, 4, u32> topology;
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BitField<4, 1, u32> primitive_restart_enable;
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BitField<5, 1, u32> cull_enable;
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BitField<6, 1, u32> depth_bias_enable;
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BitField<7, 1, u32> depth_clamp_enable;
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BitField<8, 1, u32> ndc_minus_one_to_one;
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BitField<9, 2, u32> cull_face;
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BitField<11, 1, u32> front_face;
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BitField<12, 2, u32> polygon_mode;
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BitField<14, 5, u32> patch_control_points_minus_one;
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BitField<19, 2, u32> tessellation_primitive;
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BitField<21, 2, u32> tessellation_spacing;
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BitField<23, 1, u32> tessellation_clockwise;
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BitField<24, 1, u32> logic_op_enable;
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BitField<25, 4, u32> logic_op;
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};
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bool cull_enable;
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bool depth_bias_enable;
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bool depth_clamp_enable;
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bool ndc_minus_one_to_one;
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Maxwell::CullFace cull_face;
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Maxwell::FrontFace front_face;
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// TODO(Rodrigo): Move this to push constants
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u32 point_size;
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void Fill(const Maxwell& regs) noexcept;
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std::size_t Hash() const noexcept;
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@ -183,7 +163,20 @@ struct FixedPipelineState {
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bool operator!=(const Rasterizer& rhs) const noexcept {
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return !operator==(rhs);
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}
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constexpr Maxwell::PrimitiveTopology Topology() const noexcept {
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return static_cast<Maxwell::PrimitiveTopology>(topology.Value());
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}
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Maxwell::CullFace CullFace() const noexcept {
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return UnpackCullFace(cull_face.Value());
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}
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Maxwell::FrontFace FrontFace() const noexcept {
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return UnpackFrontFace(front_face.Value());
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}
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};
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static_assert(IsHashable<Rasterizer>);
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struct DepthStencil {
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template <std::size_t Position>
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@ -257,8 +250,6 @@ struct FixedPipelineState {
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};
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VertexInput vertex_input;
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InputAssembly input_assembly;
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Tessellation tessellation;
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Rasterizer rasterizer;
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DepthStencil depth_stencil;
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ColorBlending color_blending;
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||||
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|
@ -273,8 +264,6 @@ struct FixedPipelineState {
|
|||
};
|
||||
static_assert(std::is_trivially_copyable_v<FixedPipelineState::BlendingAttachment>);
|
||||
static_assert(std::is_trivially_copyable_v<FixedPipelineState::VertexInput>);
|
||||
static_assert(std::is_trivially_copyable_v<FixedPipelineState::InputAssembly>);
|
||||
static_assert(std::is_trivially_copyable_v<FixedPipelineState::Tessellation>);
|
||||
static_assert(std::is_trivially_copyable_v<FixedPipelineState::Rasterizer>);
|
||||
static_assert(std::is_trivially_copyable_v<FixedPipelineState::DepthStencil>);
|
||||
static_assert(std::is_trivially_copyable_v<FixedPipelineState::ColorBlending>);
|
||||
|
|
|
|||
|
|
@ -158,10 +158,8 @@ std::vector<vk::ShaderModule> VKGraphicsPipeline::CreateShaderModules(
|
|||
vk::Pipeline VKGraphicsPipeline::CreatePipeline(const RenderPassParams& renderpass_params,
|
||||
const SPIRVProgram& program) const {
|
||||
const auto& vi = fixed_state.vertex_input;
|
||||
const auto& ia = fixed_state.input_assembly;
|
||||
const auto& ds = fixed_state.depth_stencil;
|
||||
const auto& cd = fixed_state.color_blending;
|
||||
const auto& ts = fixed_state.tessellation;
|
||||
const auto& rs = fixed_state.rasterizer;
|
||||
|
||||
std::vector<VkVertexInputBindingDescription> vertex_bindings;
|
||||
|
|
@ -226,15 +224,15 @@ vk::Pipeline VKGraphicsPipeline::CreatePipeline(const RenderPassParams& renderpa
|
|||
input_assembly_ci.sType = VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO;
|
||||
input_assembly_ci.pNext = nullptr;
|
||||
input_assembly_ci.flags = 0;
|
||||
input_assembly_ci.topology = MaxwellToVK::PrimitiveTopology(device, ia.topology);
|
||||
input_assembly_ci.topology = MaxwellToVK::PrimitiveTopology(device, rs.Topology());
|
||||
input_assembly_ci.primitiveRestartEnable =
|
||||
ia.primitive_restart_enable && SupportsPrimitiveRestart(input_assembly_ci.topology);
|
||||
rs.primitive_restart_enable != 0 && SupportsPrimitiveRestart(input_assembly_ci.topology);
|
||||
|
||||
VkPipelineTessellationStateCreateInfo tessellation_ci;
|
||||
tessellation_ci.sType = VK_STRUCTURE_TYPE_PIPELINE_TESSELLATION_STATE_CREATE_INFO;
|
||||
tessellation_ci.pNext = nullptr;
|
||||
tessellation_ci.flags = 0;
|
||||
tessellation_ci.patchControlPoints = ts.patch_control_points;
|
||||
tessellation_ci.patchControlPoints = rs.patch_control_points_minus_one.Value() + 1;
|
||||
|
||||
VkPipelineViewportStateCreateInfo viewport_ci;
|
||||
viewport_ci.sType = VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_STATE_CREATE_INFO;
|
||||
|
|
@ -253,8 +251,8 @@ vk::Pipeline VKGraphicsPipeline::CreatePipeline(const RenderPassParams& renderpa
|
|||
rasterization_ci.rasterizerDiscardEnable = VK_FALSE;
|
||||
rasterization_ci.polygonMode = VK_POLYGON_MODE_FILL;
|
||||
rasterization_ci.cullMode =
|
||||
rs.cull_enable ? MaxwellToVK::CullFace(rs.cull_face) : VK_CULL_MODE_NONE;
|
||||
rasterization_ci.frontFace = MaxwellToVK::FrontFace(rs.front_face);
|
||||
rs.cull_enable ? MaxwellToVK::CullFace(rs.CullFace()) : VK_CULL_MODE_NONE;
|
||||
rasterization_ci.frontFace = MaxwellToVK::FrontFace(rs.FrontFace());
|
||||
rasterization_ci.depthBiasEnable = rs.depth_bias_enable;
|
||||
rasterization_ci.depthBiasConstantFactor = 0.0f;
|
||||
rasterization_ci.depthBiasClamp = 0.0f;
|
||||
|
|
|
|||
|
|
@ -329,9 +329,9 @@ VKPipelineCache::DecompileShaders(const GraphicsPipelineCacheKey& key) {
|
|||
const auto& gpu = system.GPU().Maxwell3D();
|
||||
|
||||
Specialization specialization;
|
||||
if (fixed_state.input_assembly.topology == Maxwell::PrimitiveTopology::Points) {
|
||||
ASSERT(fixed_state.input_assembly.point_size != 0.0f);
|
||||
specialization.point_size = fixed_state.input_assembly.point_size;
|
||||
if (fixed_state.rasterizer.Topology() == Maxwell::PrimitiveTopology::Points) {
|
||||
ASSERT(fixed_state.rasterizer.point_size != 0);
|
||||
std::memcpy(&specialization.point_size, &fixed_state.rasterizer.point_size, sizeof(u32));
|
||||
}
|
||||
for (std::size_t i = 0; i < Maxwell::NumVertexAttributes; ++i) {
|
||||
specialization.attribute_types[i] = fixed_state.vertex_input.attributes[i].Type();
|
||||
|
|
|
|||
Loading…
Reference in a new issue