convert tabs to spaces
This commit is contained in:
bunnei
parent
e05be0145c
commit
4860480c36
10 changed files with 6352 additions and 6352 deletions
|
|
@ -2,101 +2,101 @@
|
|||
#define __ARM_REGFORMAT_H__
|
||||
|
||||
enum arm_regno{
|
||||
R0 = 0,
|
||||
R1,
|
||||
R2,
|
||||
R3,
|
||||
R4,
|
||||
R5,
|
||||
R6,
|
||||
R7,
|
||||
R8,
|
||||
R9,
|
||||
R10,
|
||||
R11,
|
||||
R12,
|
||||
R13,
|
||||
LR,
|
||||
R15, //PC,
|
||||
CPSR_REG,
|
||||
SPSR_REG,
|
||||
R0 = 0,
|
||||
R1,
|
||||
R2,
|
||||
R3,
|
||||
R4,
|
||||
R5,
|
||||
R6,
|
||||
R7,
|
||||
R8,
|
||||
R9,
|
||||
R10,
|
||||
R11,
|
||||
R12,
|
||||
R13,
|
||||
LR,
|
||||
R15, //PC,
|
||||
CPSR_REG,
|
||||
SPSR_REG,
|
||||
#if 1
|
||||
PHYS_PC,
|
||||
R13_USR,
|
||||
R14_USR,
|
||||
R13_SVC,
|
||||
R14_SVC,
|
||||
R13_ABORT,
|
||||
R14_ABORT,
|
||||
R13_UNDEF,
|
||||
R14_UNDEF,
|
||||
R13_IRQ,
|
||||
R14_IRQ,
|
||||
R8_FIRQ,
|
||||
R9_FIRQ,
|
||||
R10_FIRQ,
|
||||
R11_FIRQ,
|
||||
R12_FIRQ,
|
||||
R13_FIRQ,
|
||||
R14_FIRQ,
|
||||
SPSR_INVALID1,
|
||||
SPSR_INVALID2,
|
||||
SPSR_SVC,
|
||||
SPSR_ABORT,
|
||||
SPSR_UNDEF,
|
||||
SPSR_IRQ,
|
||||
SPSR_FIRQ,
|
||||
MODE_REG, /* That is the cpsr[4 : 0], just for calculation easily */
|
||||
BANK_REG,
|
||||
EXCLUSIVE_TAG,
|
||||
EXCLUSIVE_STATE,
|
||||
EXCLUSIVE_RESULT,
|
||||
CP15_BASE,
|
||||
CP15_C0 = CP15_BASE,
|
||||
CP15_C0_C0 = CP15_C0,
|
||||
CP15_MAIN_ID = CP15_C0_C0,
|
||||
CP15_CACHE_TYPE,
|
||||
CP15_TCM_STATUS,
|
||||
CP15_TLB_TYPE,
|
||||
CP15_C0_C1,
|
||||
CP15_PROCESSOR_FEATURE_0 = CP15_C0_C1,
|
||||
CP15_PROCESSOR_FEATURE_1,
|
||||
CP15_DEBUG_FEATURE_0,
|
||||
CP15_AUXILIARY_FEATURE_0,
|
||||
CP15_C1_C0,
|
||||
CP15_CONTROL = CP15_C1_C0,
|
||||
CP15_AUXILIARY_CONTROL,
|
||||
CP15_COPROCESSOR_ACCESS_CONTROL,
|
||||
CP15_C2,
|
||||
CP15_C2_C0 = CP15_C2,
|
||||
CP15_TRANSLATION_BASE = CP15_C2_C0,
|
||||
CP15_TRANSLATION_BASE_TABLE_0 = CP15_TRANSLATION_BASE,
|
||||
CP15_TRANSLATION_BASE_TABLE_1,
|
||||
CP15_TRANSLATION_BASE_CONTROL,
|
||||
CP15_DOMAIN_ACCESS_CONTROL,
|
||||
CP15_RESERVED,
|
||||
/* Fault status */
|
||||
CP15_FAULT_STATUS,
|
||||
CP15_INSTR_FAULT_STATUS,
|
||||
CP15_COMBINED_DATA_FSR = CP15_FAULT_STATUS,
|
||||
CP15_INST_FSR,
|
||||
/* Fault Address register */
|
||||
CP15_FAULT_ADDRESS,
|
||||
CP15_COMBINED_DATA_FAR = CP15_FAULT_ADDRESS,
|
||||
CP15_WFAR,
|
||||
CP15_IFAR,
|
||||
CP15_PID,
|
||||
CP15_CONTEXT_ID,
|
||||
CP15_THREAD_URO,
|
||||
CP15_TLB_FAULT_ADDR, /* defined by SkyEye */
|
||||
CP15_TLB_FAULT_STATUS, /* defined by SkyEye */
|
||||
/* VFP registers */
|
||||
VFP_BASE,
|
||||
VFP_FPSID = VFP_BASE,
|
||||
VFP_FPSCR,
|
||||
VFP_FPEXC,
|
||||
#endif
|
||||
MAX_REG_NUM,
|
||||
PHYS_PC,
|
||||
R13_USR,
|
||||
R14_USR,
|
||||
R13_SVC,
|
||||
R14_SVC,
|
||||
R13_ABORT,
|
||||
R14_ABORT,
|
||||
R13_UNDEF,
|
||||
R14_UNDEF,
|
||||
R13_IRQ,
|
||||
R14_IRQ,
|
||||
R8_FIRQ,
|
||||
R9_FIRQ,
|
||||
R10_FIRQ,
|
||||
R11_FIRQ,
|
||||
R12_FIRQ,
|
||||
R13_FIRQ,
|
||||
R14_FIRQ,
|
||||
SPSR_INVALID1,
|
||||
SPSR_INVALID2,
|
||||
SPSR_SVC,
|
||||
SPSR_ABORT,
|
||||
SPSR_UNDEF,
|
||||
SPSR_IRQ,
|
||||
SPSR_FIRQ,
|
||||
MODE_REG, /* That is the cpsr[4 : 0], just for calculation easily */
|
||||
BANK_REG,
|
||||
EXCLUSIVE_TAG,
|
||||
EXCLUSIVE_STATE,
|
||||
EXCLUSIVE_RESULT,
|
||||
CP15_BASE,
|
||||
CP15_C0 = CP15_BASE,
|
||||
CP15_C0_C0 = CP15_C0,
|
||||
CP15_MAIN_ID = CP15_C0_C0,
|
||||
CP15_CACHE_TYPE,
|
||||
CP15_TCM_STATUS,
|
||||
CP15_TLB_TYPE,
|
||||
CP15_C0_C1,
|
||||
CP15_PROCESSOR_FEATURE_0 = CP15_C0_C1,
|
||||
CP15_PROCESSOR_FEATURE_1,
|
||||
CP15_DEBUG_FEATURE_0,
|
||||
CP15_AUXILIARY_FEATURE_0,
|
||||
CP15_C1_C0,
|
||||
CP15_CONTROL = CP15_C1_C0,
|
||||
CP15_AUXILIARY_CONTROL,
|
||||
CP15_COPROCESSOR_ACCESS_CONTROL,
|
||||
CP15_C2,
|
||||
CP15_C2_C0 = CP15_C2,
|
||||
CP15_TRANSLATION_BASE = CP15_C2_C0,
|
||||
CP15_TRANSLATION_BASE_TABLE_0 = CP15_TRANSLATION_BASE,
|
||||
CP15_TRANSLATION_BASE_TABLE_1,
|
||||
CP15_TRANSLATION_BASE_CONTROL,
|
||||
CP15_DOMAIN_ACCESS_CONTROL,
|
||||
CP15_RESERVED,
|
||||
/* Fault status */
|
||||
CP15_FAULT_STATUS,
|
||||
CP15_INSTR_FAULT_STATUS,
|
||||
CP15_COMBINED_DATA_FSR = CP15_FAULT_STATUS,
|
||||
CP15_INST_FSR,
|
||||
/* Fault Address register */
|
||||
CP15_FAULT_ADDRESS,
|
||||
CP15_COMBINED_DATA_FAR = CP15_FAULT_ADDRESS,
|
||||
CP15_WFAR,
|
||||
CP15_IFAR,
|
||||
CP15_PID,
|
||||
CP15_CONTEXT_ID,
|
||||
CP15_THREAD_URO,
|
||||
CP15_TLB_FAULT_ADDR, /* defined by SkyEye */
|
||||
CP15_TLB_FAULT_STATUS, /* defined by SkyEye */
|
||||
/* VFP registers */
|
||||
VFP_BASE,
|
||||
VFP_FPSID = VFP_BASE,
|
||||
VFP_FPSCR,
|
||||
VFP_FPEXC,
|
||||
#endif
|
||||
MAX_REG_NUM,
|
||||
};
|
||||
|
||||
#define VFP_OFFSET(x) (x - VFP_BASE)
|
||||
|
|
|
|||
|
|
@ -1,21 +1,21 @@
|
|||
/*
|
||||
* arm
|
||||
* armcpu.h
|
||||
* arm
|
||||
* armcpu.h
|
||||
*
|
||||
* Copyright (C) 2003, 2004 Sebastian Biallas (sb@biallas.net)
|
||||
* Copyright (C) 2003, 2004 Sebastian Biallas (sb@biallas.net)
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
|
||||
*/
|
||||
|
||||
#ifndef __ARM_CPU_H__
|
||||
|
|
@ -32,19 +32,19 @@
|
|||
|
||||
|
||||
typedef struct ARM_CPU_State_s {
|
||||
ARMul_State * core;
|
||||
uint32_t core_num;
|
||||
/* The core id that boot from
|
||||
*/
|
||||
uint32_t boot_core_id;
|
||||
ARMul_State * core;
|
||||
uint32_t core_num;
|
||||
/* The core id that boot from
|
||||
*/
|
||||
uint32_t boot_core_id;
|
||||
}ARM_CPU_State;
|
||||
|
||||
//static ARM_CPU_State* get_current_cpu(){
|
||||
// machine_config_t* mach = get_current_mach();
|
||||
// /* Casting a conf_obj_t to ARM_CPU_State type */
|
||||
// ARM_CPU_State* cpu = (ARM_CPU_State*)mach->cpu_data->obj;
|
||||
// machine_config_t* mach = get_current_mach();
|
||||
// /* Casting a conf_obj_t to ARM_CPU_State type */
|
||||
// ARM_CPU_State* cpu = (ARM_CPU_State*)mach->cpu_data->obj;
|
||||
//
|
||||
// return cpu;
|
||||
// return cpu;
|
||||
//}
|
||||
|
||||
/**
|
||||
|
|
@ -53,8 +53,8 @@ typedef struct ARM_CPU_State_s {
|
|||
* @return
|
||||
*/
|
||||
//static ARMul_State* get_boot_core(){
|
||||
// ARM_CPU_State* cpu = get_current_cpu();
|
||||
// return &cpu->core[cpu->boot_core_id];
|
||||
// ARM_CPU_State* cpu = get_current_cpu();
|
||||
// return &cpu->core[cpu->boot_core_id];
|
||||
//}
|
||||
/**
|
||||
* @brief Get the instance of running core
|
||||
|
|
@ -62,19 +62,19 @@ typedef struct ARM_CPU_State_s {
|
|||
* @return the core instance
|
||||
*/
|
||||
//static ARMul_State* get_current_core(){
|
||||
// /* Casting a conf_obj_t to ARM_CPU_State type */
|
||||
// int id = Common::CurrentThreadId();
|
||||
// /* If thread is not in running mode, we should give the boot core */
|
||||
// if(get_thread_state(id) != Running_state){
|
||||
// return get_boot_core();
|
||||
// }
|
||||
// /* Judge if we are running in paralell or sequenial */
|
||||
// if(thread_exist(id)){
|
||||
// conf_object_t* conf_obj = get_current_exec_priv(id);
|
||||
// return (ARMul_State*)get_cast_conf_obj(conf_obj, "arm_core_t");
|
||||
// }
|
||||
// /* Casting a conf_obj_t to ARM_CPU_State type */
|
||||
// int id = Common::CurrentThreadId();
|
||||
// /* If thread is not in running mode, we should give the boot core */
|
||||
// if(get_thread_state(id) != Running_state){
|
||||
// return get_boot_core();
|
||||
// }
|
||||
// /* Judge if we are running in paralell or sequenial */
|
||||
// if(thread_exist(id)){
|
||||
// conf_object_t* conf_obj = get_current_exec_priv(id);
|
||||
// return (ARMul_State*)get_cast_conf_obj(conf_obj, "arm_core_t");
|
||||
// }
|
||||
//
|
||||
// return NULL;
|
||||
// return NULL;
|
||||
//}
|
||||
|
||||
#define CURRENT_CORE get_current_core()
|
||||
|
|
|
|||
|
|
@ -89,7 +89,7 @@
|
|||
#endif
|
||||
|
||||
//#define DBCT_TEST_SPEED
|
||||
#define DBCT_TEST_SPEED_SEC 10
|
||||
#define DBCT_TEST_SPEED_SEC 10
|
||||
//AJ2D--------------------------------------------------------------------------
|
||||
|
||||
//teawater add compile switch for DBCT GDB RSP function 2005.10.21--------------
|
||||
|
|
@ -99,9 +99,9 @@
|
|||
//#include <skyeye_defs.h>
|
||||
//#include <skyeye_types.h>
|
||||
|
||||
#define ARM_BYTE_TYPE 0
|
||||
#define ARM_HALFWORD_TYPE 1
|
||||
#define ARM_WORD_TYPE 2
|
||||
#define ARM_BYTE_TYPE 0
|
||||
#define ARM_HALFWORD_TYPE 1
|
||||
#define ARM_WORD_TYPE 2
|
||||
|
||||
//the define of cachetype
|
||||
#define NONCACHE 0
|
||||
|
|
@ -112,10 +112,10 @@
|
|||
typedef char *VoidStar;
|
||||
#endif
|
||||
|
||||
typedef unsigned long long ARMdword; /* must be 64 bits wide */
|
||||
typedef unsigned int ARMword; /* must be 32 bits wide */
|
||||
typedef unsigned char ARMbyte; /* must be 8 bits wide */
|
||||
typedef unsigned short ARMhword; /* must be 16 bits wide */
|
||||
typedef unsigned long long ARMdword; /* must be 64 bits wide */
|
||||
typedef unsigned int ARMword; /* must be 32 bits wide */
|
||||
typedef unsigned char ARMbyte; /* must be 8 bits wide */
|
||||
typedef unsigned short ARMhword; /* must be 16 bits wide */
|
||||
typedef struct ARMul_State ARMul_State;
|
||||
typedef struct ARMul_io ARMul_io;
|
||||
typedef struct ARMul_Energy ARMul_Energy;
|
||||
|
|
@ -152,59 +152,59 @@ typedef unsigned long long uint64_t;
|
|||
typedef unsigned ARMul_CPInits (ARMul_State * state);
|
||||
typedef unsigned ARMul_CPExits (ARMul_State * state);
|
||||
typedef unsigned ARMul_LDCs (ARMul_State * state, unsigned type,
|
||||
ARMword instr, ARMword value);
|
||||
ARMword instr, ARMword value);
|
||||
typedef unsigned ARMul_STCs (ARMul_State * state, unsigned type,
|
||||
ARMword instr, ARMword * value);
|
||||
ARMword instr, ARMword * value);
|
||||
typedef unsigned ARMul_MRCs (ARMul_State * state, unsigned type,
|
||||
ARMword instr, ARMword * value);
|
||||
ARMword instr, ARMword * value);
|
||||
typedef unsigned ARMul_MCRs (ARMul_State * state, unsigned type,
|
||||
ARMword instr, ARMword value);
|
||||
ARMword instr, ARMword value);
|
||||
typedef unsigned ARMul_MRRCs (ARMul_State * state, unsigned type,
|
||||
ARMword instr, ARMword * value1, ARMword * value2);
|
||||
ARMword instr, ARMword * value1, ARMword * value2);
|
||||
typedef unsigned ARMul_MCRRs (ARMul_State * state, unsigned type,
|
||||
ARMword instr, ARMword value1, ARMword value2);
|
||||
ARMword instr, ARMword value1, ARMword value2);
|
||||
typedef unsigned ARMul_CDPs (ARMul_State * state, unsigned type,
|
||||
ARMword instr);
|
||||
ARMword instr);
|
||||
typedef unsigned ARMul_CPReads (ARMul_State * state, unsigned reg,
|
||||
ARMword * value);
|
||||
ARMword * value);
|
||||
typedef unsigned ARMul_CPWrites (ARMul_State * state, unsigned reg,
|
||||
ARMword value);
|
||||
ARMword value);
|
||||
|
||||
|
||||
//added by ksh,2004-3-5
|
||||
struct ARMul_io
|
||||
{
|
||||
ARMword *instr; //to display the current interrupt state
|
||||
ARMword *net_flag; //to judge if network is enabled
|
||||
ARMword *net_int; //netcard interrupt
|
||||
ARMword *instr; //to display the current interrupt state
|
||||
ARMword *net_flag; //to judge if network is enabled
|
||||
ARMword *net_int; //netcard interrupt
|
||||
|
||||
//ywc,2004-04-01
|
||||
ARMword *ts_int;
|
||||
ARMword *ts_is_enable;
|
||||
ARMword *ts_addr_begin;
|
||||
ARMword *ts_addr_end;
|
||||
ARMword *ts_buffer;
|
||||
//ywc,2004-04-01
|
||||
ARMword *ts_int;
|
||||
ARMword *ts_is_enable;
|
||||
ARMword *ts_addr_begin;
|
||||
ARMword *ts_addr_end;
|
||||
ARMword *ts_buffer;
|
||||
};
|
||||
|
||||
/* added by ksh,2004-11-26,some energy profiling */
|
||||
struct ARMul_Energy
|
||||
{
|
||||
int energy_prof; /* <tktan> BUG200103282109 : for energy profiling */
|
||||
int enable_func_energy; /* <tktan> BUG200105181702 */
|
||||
char *func_energy;
|
||||
int func_display; /* <tktan> BUG200103311509 : for function call display */
|
||||
int func_disp_start; /* <tktan> BUG200104191428 : to start func profiling */
|
||||
char *start_func; /* <tktan> BUG200104191428 */
|
||||
int energy_prof; /* <tktan> BUG200103282109 : for energy profiling */
|
||||
int enable_func_energy; /* <tktan> BUG200105181702 */
|
||||
char *func_energy;
|
||||
int func_display; /* <tktan> BUG200103311509 : for function call display */
|
||||
int func_disp_start; /* <tktan> BUG200104191428 : to start func profiling */
|
||||
char *start_func; /* <tktan> BUG200104191428 */
|
||||
|
||||
FILE *outfile; /* <tktan> BUG200105201531 : direct console to file */
|
||||
long long tcycle, pcycle;
|
||||
float t_energy;
|
||||
void *cur_task; /* <tktan> BUG200103291737 */
|
||||
long long t_mem_cycle, t_idle_cycle, t_uart_cycle;
|
||||
long long p_mem_cycle, p_idle_cycle, p_uart_cycle;
|
||||
long long p_io_update_tcycle;
|
||||
/*record CCCR,to get current core frequency */
|
||||
ARMword cccr;
|
||||
FILE *outfile; /* <tktan> BUG200105201531 : direct console to file */
|
||||
long long tcycle, pcycle;
|
||||
float t_energy;
|
||||
void *cur_task; /* <tktan> BUG200103291737 */
|
||||
long long t_mem_cycle, t_idle_cycle, t_uart_cycle;
|
||||
long long p_mem_cycle, p_idle_cycle, p_uart_cycle;
|
||||
long long p_io_update_tcycle;
|
||||
/*record CCCR,to get current core frequency */
|
||||
ARMword cccr;
|
||||
};
|
||||
#if 0
|
||||
#define MAX_BANK 8
|
||||
|
|
@ -212,119 +212,119 @@ struct ARMul_Energy
|
|||
|
||||
typedef struct mem_bank
|
||||
{
|
||||
ARMword (*read_byte) (ARMul_State * state, ARMword addr);
|
||||
void (*write_byte) (ARMul_State * state, ARMword addr, ARMword data);
|
||||
ARMword (*read_halfword) (ARMul_State * state, ARMword addr);
|
||||
void (*write_halfword) (ARMul_State * state, ARMword addr,
|
||||
ARMword data);
|
||||
ARMword (*read_word) (ARMul_State * state, ARMword addr);
|
||||
void (*write_word) (ARMul_State * state, ARMword addr, ARMword data);
|
||||
unsigned int addr, len;
|
||||
char filename[MAX_STR];
|
||||
unsigned type; //chy 2003-09-21: maybe io,ram,rom
|
||||
ARMword (*read_byte) (ARMul_State * state, ARMword addr);
|
||||
void (*write_byte) (ARMul_State * state, ARMword addr, ARMword data);
|
||||
ARMword (*read_halfword) (ARMul_State * state, ARMword addr);
|
||||
void (*write_halfword) (ARMul_State * state, ARMword addr,
|
||||
ARMword data);
|
||||
ARMword (*read_word) (ARMul_State * state, ARMword addr);
|
||||
void (*write_word) (ARMul_State * state, ARMword addr, ARMword data);
|
||||
unsigned int addr, len;
|
||||
char filename[MAX_STR];
|
||||
unsigned type; //chy 2003-09-21: maybe io,ram,rom
|
||||
} mem_bank_t;
|
||||
typedef struct
|
||||
{
|
||||
int bank_num;
|
||||
int current_num; /*current num of bank */
|
||||
mem_bank_t mem_banks[MAX_BANK];
|
||||
int bank_num;
|
||||
int current_num; /*current num of bank */
|
||||
mem_bank_t mem_banks[MAX_BANK];
|
||||
} mem_config_t;
|
||||
#endif
|
||||
#define VFP_REG_NUM 64
|
||||
struct ARMul_State
|
||||
{
|
||||
ARMword Emulate; /* to start and stop emulation */
|
||||
unsigned EndCondition; /* reason for stopping */
|
||||
unsigned ErrorCode; /* type of illegal instruction */
|
||||
ARMword Emulate; /* to start and stop emulation */
|
||||
unsigned EndCondition; /* reason for stopping */
|
||||
unsigned ErrorCode; /* type of illegal instruction */
|
||||
|
||||
/* Order of the following register should not be modified */
|
||||
ARMword Reg[16]; /* the current register file */
|
||||
ARMword Cpsr; /* the current psr */
|
||||
ARMword Spsr_copy;
|
||||
ARMword phys_pc;
|
||||
ARMword Reg_usr[2];
|
||||
ARMword Reg_svc[2]; /* R13_SVC R14_SVC */
|
||||
ARMword Reg_abort[2]; /* R13_ABORT R14_ABORT */
|
||||
ARMword Reg_undef[2]; /* R13 UNDEF R14 UNDEF */
|
||||
ARMword Reg_irq[2]; /* R13_IRQ R14_IRQ */
|
||||
ARMword Reg_firq[7]; /* R8---R14 FIRQ */
|
||||
ARMword Spsr[7]; /* the exception psr's */
|
||||
ARMword Mode; /* the current mode */
|
||||
ARMword Bank; /* the current register bank */
|
||||
ARMword exclusive_tag;
|
||||
ARMword exclusive_state;
|
||||
ARMword exclusive_result;
|
||||
ARMword CP15[VFP_BASE - CP15_BASE];
|
||||
ARMword VFP[3]; /* FPSID, FPSCR, and FPEXC */
|
||||
/* VFPv2 and VFPv3-D16 has 16 doubleword registers (D0-D16 or S0-S31).
|
||||
VFPv3-D32/ASIMD may have up to 32 doubleword registers (D0-D31),
|
||||
and only 32 singleword registers are accessible (S0-S31). */
|
||||
ARMword ExtReg[VFP_REG_NUM];
|
||||
/* ---- End of the ordered registers ---- */
|
||||
|
||||
ARMword RegBank[7][16]; /* all the registers */
|
||||
//chy:2003-08-19, used in arm xscale
|
||||
/* 40 bit accumulator. We always keep this 64 bits wide,
|
||||
and move only 40 bits out of it in an MRA insn. */
|
||||
ARMdword Accumulator;
|
||||
/* Order of the following register should not be modified */
|
||||
ARMword Reg[16]; /* the current register file */
|
||||
ARMword Cpsr; /* the current psr */
|
||||
ARMword Spsr_copy;
|
||||
ARMword phys_pc;
|
||||
ARMword Reg_usr[2];
|
||||
ARMword Reg_svc[2]; /* R13_SVC R14_SVC */
|
||||
ARMword Reg_abort[2]; /* R13_ABORT R14_ABORT */
|
||||
ARMword Reg_undef[2]; /* R13 UNDEF R14 UNDEF */
|
||||
ARMword Reg_irq[2]; /* R13_IRQ R14_IRQ */
|
||||
ARMword Reg_firq[7]; /* R8---R14 FIRQ */
|
||||
ARMword Spsr[7]; /* the exception psr's */
|
||||
ARMword Mode; /* the current mode */
|
||||
ARMword Bank; /* the current register bank */
|
||||
ARMword exclusive_tag;
|
||||
ARMword exclusive_state;
|
||||
ARMword exclusive_result;
|
||||
ARMword CP15[VFP_BASE - CP15_BASE];
|
||||
ARMword VFP[3]; /* FPSID, FPSCR, and FPEXC */
|
||||
/* VFPv2 and VFPv3-D16 has 16 doubleword registers (D0-D16 or S0-S31).
|
||||
VFPv3-D32/ASIMD may have up to 32 doubleword registers (D0-D31),
|
||||
and only 32 singleword registers are accessible (S0-S31). */
|
||||
ARMword ExtReg[VFP_REG_NUM];
|
||||
/* ---- End of the ordered registers ---- */
|
||||
|
||||
ARMword RegBank[7][16]; /* all the registers */
|
||||
//chy:2003-08-19, used in arm xscale
|
||||
/* 40 bit accumulator. We always keep this 64 bits wide,
|
||||
and move only 40 bits out of it in an MRA insn. */
|
||||
ARMdword Accumulator;
|
||||
|
||||
ARMword NFlag, ZFlag, CFlag, VFlag, IFFlags; /* dummy flags for speed */
|
||||
ARMword NFlag, ZFlag, CFlag, VFlag, IFFlags; /* dummy flags for speed */
|
||||
unsigned long long int icounter, debug_icounter, kernel_icounter;
|
||||
unsigned int shifter_carry_out;
|
||||
//ARMword translate_pc;
|
||||
|
||||
/* add armv6 flags dyf:2010-08-09 */
|
||||
ARMword GEFlag, EFlag, AFlag, QFlags;
|
||||
//chy:2003-08-19, used in arm v5e|xscale
|
||||
ARMword SFlag;
|
||||
/* add armv6 flags dyf:2010-08-09 */
|
||||
ARMword GEFlag, EFlag, AFlag, QFlags;
|
||||
//chy:2003-08-19, used in arm v5e|xscale
|
||||
ARMword SFlag;
|
||||
#ifdef MODET
|
||||
ARMword TFlag; /* Thumb state */
|
||||
ARMword TFlag; /* Thumb state */
|
||||
#endif
|
||||
ARMword instr, pc, temp; /* saved register state */
|
||||
ARMword loaded, decoded; /* saved pipeline state */
|
||||
//chy 2006-04-12 for ICE breakpoint
|
||||
ARMword loaded_addr, decoded_addr; /* saved pipeline state addr*/
|
||||
unsigned int NumScycles, NumNcycles, NumIcycles, NumCcycles, NumFcycles; /* emulated cycles used */
|
||||
unsigned long long NumInstrs; /* the number of instructions executed */
|
||||
unsigned NextInstr;
|
||||
unsigned VectorCatch; /* caught exception mask */
|
||||
unsigned CallDebug; /* set to call the debugger */
|
||||
unsigned CanWatch; /* set by memory interface if its willing to suffer the
|
||||
overhead of checking for watchpoints on each memory
|
||||
access */
|
||||
unsigned int StopHandle;
|
||||
ARMword instr, pc, temp; /* saved register state */
|
||||
ARMword loaded, decoded; /* saved pipeline state */
|
||||
//chy 2006-04-12 for ICE breakpoint
|
||||
ARMword loaded_addr, decoded_addr; /* saved pipeline state addr*/
|
||||
unsigned int NumScycles, NumNcycles, NumIcycles, NumCcycles, NumFcycles; /* emulated cycles used */
|
||||
unsigned long long NumInstrs; /* the number of instructions executed */
|
||||
unsigned NextInstr;
|
||||
unsigned VectorCatch; /* caught exception mask */
|
||||
unsigned CallDebug; /* set to call the debugger */
|
||||
unsigned CanWatch; /* set by memory interface if its willing to suffer the
|
||||
overhead of checking for watchpoints on each memory
|
||||
access */
|
||||
unsigned int StopHandle;
|
||||
|
||||
char *CommandLine; /* Command Line from ARMsd */
|
||||
char *CommandLine; /* Command Line from ARMsd */
|
||||
|
||||
ARMul_CPInits *CPInit[16]; /* coprocessor initialisers */
|
||||
ARMul_CPExits *CPExit[16]; /* coprocessor finalisers */
|
||||
ARMul_LDCs *LDC[16]; /* LDC instruction */
|
||||
ARMul_STCs *STC[16]; /* STC instruction */
|
||||
ARMul_MRCs *MRC[16]; /* MRC instruction */
|
||||
ARMul_MCRs *MCR[16]; /* MCR instruction */
|
||||
ARMul_MRRCs *MRRC[16]; /* MRRC instruction */
|
||||
ARMul_MCRRs *MCRR[16]; /* MCRR instruction */
|
||||
ARMul_CDPs *CDP[16]; /* CDP instruction */
|
||||
ARMul_CPReads *CPRead[16]; /* Read CP register */
|
||||
ARMul_CPWrites *CPWrite[16]; /* Write CP register */
|
||||
unsigned char *CPData[16]; /* Coprocessor data */
|
||||
unsigned char const *CPRegWords[16]; /* map of coprocessor register sizes */
|
||||
ARMul_CPInits *CPInit[16]; /* coprocessor initialisers */
|
||||
ARMul_CPExits *CPExit[16]; /* coprocessor finalisers */
|
||||
ARMul_LDCs *LDC[16]; /* LDC instruction */
|
||||
ARMul_STCs *STC[16]; /* STC instruction */
|
||||
ARMul_MRCs *MRC[16]; /* MRC instruction */
|
||||
ARMul_MCRs *MCR[16]; /* MCR instruction */
|
||||
ARMul_MRRCs *MRRC[16]; /* MRRC instruction */
|
||||
ARMul_MCRRs *MCRR[16]; /* MCRR instruction */
|
||||
ARMul_CDPs *CDP[16]; /* CDP instruction */
|
||||
ARMul_CPReads *CPRead[16]; /* Read CP register */
|
||||
ARMul_CPWrites *CPWrite[16]; /* Write CP register */
|
||||
unsigned char *CPData[16]; /* Coprocessor data */
|
||||
unsigned char const *CPRegWords[16]; /* map of coprocessor register sizes */
|
||||
|
||||
unsigned EventSet; /* the number of events in the queue */
|
||||
unsigned int Now; /* time to the nearest cycle */
|
||||
struct EventNode **EventPtr; /* the event list */
|
||||
unsigned EventSet; /* the number of events in the queue */
|
||||
unsigned int Now; /* time to the nearest cycle */
|
||||
struct EventNode **EventPtr; /* the event list */
|
||||
|
||||
unsigned Debug; /* show instructions as they are executed */
|
||||
unsigned NresetSig; /* reset the processor */
|
||||
unsigned NfiqSig;
|
||||
unsigned NirqSig;
|
||||
unsigned Debug; /* show instructions as they are executed */
|
||||
unsigned NresetSig; /* reset the processor */
|
||||
unsigned NfiqSig;
|
||||
unsigned NirqSig;
|
||||
|
||||
unsigned abortSig;
|
||||
unsigned NtransSig;
|
||||
unsigned bigendSig;
|
||||
unsigned prog32Sig;
|
||||
unsigned data32Sig;
|
||||
unsigned syscallSig;
|
||||
unsigned abortSig;
|
||||
unsigned NtransSig;
|
||||
unsigned bigendSig;
|
||||
unsigned prog32Sig;
|
||||
unsigned data32Sig;
|
||||
unsigned syscallSig;
|
||||
|
||||
/* 2004-05-09 chy
|
||||
----------------------------------------------------------
|
||||
|
|
@ -357,115 +357,115 @@ on later processors, this bit reads as 1 and ignores writes.
|
|||
So, if lateabtSig=1, then it means Late Abort Model(Base Updated Abort Model)
|
||||
if lateabtSig=0, then it means Base Restored Abort Model
|
||||
*/
|
||||
unsigned lateabtSig;
|
||||
unsigned lateabtSig;
|
||||
|
||||
ARMword Vector; /* synthesize aborts in cycle modes */
|
||||
ARMword Aborted; /* sticky flag for aborts */
|
||||
ARMword Reseted; /* sticky flag for Reset */
|
||||
ARMword Inted, LastInted; /* sticky flags for interrupts */
|
||||
ARMword Base; /* extra hand for base writeback */
|
||||
ARMword AbortAddr; /* to keep track of Prefetch aborts */
|
||||
ARMword Vector; /* synthesize aborts in cycle modes */
|
||||
ARMword Aborted; /* sticky flag for aborts */
|
||||
ARMword Reseted; /* sticky flag for Reset */
|
||||
ARMword Inted, LastInted; /* sticky flags for interrupts */
|
||||
ARMword Base; /* extra hand for base writeback */
|
||||
ARMword AbortAddr; /* to keep track of Prefetch aborts */
|
||||
|
||||
const struct Dbg_HostosInterface *hostif;
|
||||
const struct Dbg_HostosInterface *hostif;
|
||||
|
||||
int verbose; /* non-zero means print various messages like the banner */
|
||||
int verbose; /* non-zero means print various messages like the banner */
|
||||
|
||||
mmu_state_t mmu;
|
||||
int mmu_inited;
|
||||
//mem_state_t mem;
|
||||
/*remove io_state to skyeye_mach_*.c files */
|
||||
//io_state_t io;
|
||||
/* point to a interrupt pending register. now for skyeye-ne2k.c
|
||||
* later should move somewhere. e.g machine_config_t*/
|
||||
mmu_state_t mmu;
|
||||
int mmu_inited;
|
||||
//mem_state_t mem;
|
||||
/*remove io_state to skyeye_mach_*.c files */
|
||||
//io_state_t io;
|
||||
/* point to a interrupt pending register. now for skyeye-ne2k.c
|
||||
* later should move somewhere. e.g machine_config_t*/
|
||||
|
||||
|
||||
//chy: 2003-08-11, for different arm core type
|
||||
unsigned is_v4; /* Are we emulating a v4 architecture (or higher) ? */
|
||||
unsigned is_v5; /* Are we emulating a v5 architecture ? */
|
||||
unsigned is_v5e; /* Are we emulating a v5e architecture ? */
|
||||
unsigned is_v6; /* Are we emulating a v6 architecture ? */
|
||||
unsigned is_v7; /* Are we emulating a v7 architecture ? */
|
||||
unsigned is_XScale; /* Are we emulating an XScale architecture ? */
|
||||
unsigned is_iWMMXt; /* Are we emulating an iWMMXt co-processor ? */
|
||||
unsigned is_ep9312; /* Are we emulating a Cirrus Maverick co-processor ? */
|
||||
//chy 2005-09-19
|
||||
unsigned is_pxa27x; /* Are we emulating a Intel PXA27x co-processor ? */
|
||||
//chy: seems only used in xscale's CP14
|
||||
unsigned int LastTime; /* Value of last call to ARMul_Time() */
|
||||
ARMword CP14R0_CCD; /* used to count 64 clock cycles with CP14 R0 bit 3 set */
|
||||
//chy: 2003-08-11, for different arm core type
|
||||
unsigned is_v4; /* Are we emulating a v4 architecture (or higher) ? */
|
||||
unsigned is_v5; /* Are we emulating a v5 architecture ? */
|
||||
unsigned is_v5e; /* Are we emulating a v5e architecture ? */
|
||||
unsigned is_v6; /* Are we emulating a v6 architecture ? */
|
||||
unsigned is_v7; /* Are we emulating a v7 architecture ? */
|
||||
unsigned is_XScale; /* Are we emulating an XScale architecture ? */
|
||||
unsigned is_iWMMXt; /* Are we emulating an iWMMXt co-processor ? */
|
||||
unsigned is_ep9312; /* Are we emulating a Cirrus Maverick co-processor ? */
|
||||
//chy 2005-09-19
|
||||
unsigned is_pxa27x; /* Are we emulating a Intel PXA27x co-processor ? */
|
||||
//chy: seems only used in xscale's CP14
|
||||
unsigned int LastTime; /* Value of last call to ARMul_Time() */
|
||||
ARMword CP14R0_CCD; /* used to count 64 clock cycles with CP14 R0 bit 3 set */
|
||||
|
||||
|
||||
//added by ksh:for handle different machs io 2004-3-5
|
||||
ARMul_io mach_io;
|
||||
ARMul_io mach_io;
|
||||
|
||||
/*added by ksh,2004-11-26,some energy profiling*/
|
||||
ARMul_Energy energy;
|
||||
ARMul_Energy energy;
|
||||
|
||||
//teawater add for next_dis 2004.10.27-----------------------
|
||||
int disassemble;
|
||||
int disassemble;
|
||||
//AJ2D------------------------------------------
|
||||
|
||||
//teawater add for arm2x86 2005.02.15-------------------------------------------
|
||||
u32 trap;
|
||||
u32 tea_break_addr;
|
||||
u32 tea_break_ok;
|
||||
int tea_pc;
|
||||
u32 trap;
|
||||
u32 tea_break_addr;
|
||||
u32 tea_break_ok;
|
||||
int tea_pc;
|
||||
//AJ2D--------------------------------------------------------------------------
|
||||
//teawater add for arm2x86 2005.07.03-------------------------------------------
|
||||
|
||||
/*
|
||||
* 2007-01-24 removed the term-io functions by Anthony Lee,
|
||||
* moved to "device/uart/skyeye_uart_stdio.c".
|
||||
*/
|
||||
/*
|
||||
* 2007-01-24 removed the term-io functions by Anthony Lee,
|
||||
* moved to "device/uart/skyeye_uart_stdio.c".
|
||||
*/
|
||||
|
||||
//AJ2D--------------------------------------------------------------------------
|
||||
//teawater add for arm2x86 2005.07.05-------------------------------------------
|
||||
//arm_arm A2-18
|
||||
int abort_model; //0 Base Restored Abort Model, 1 the Early Abort Model, 2 Base Updated Abort Model
|
||||
//arm_arm A2-18
|
||||
int abort_model; //0 Base Restored Abort Model, 1 the Early Abort Model, 2 Base Updated Abort Model
|
||||
//AJ2D--------------------------------------------------------------------------
|
||||
//teawater change for return if running tb dirty 2005.07.09---------------------
|
||||
void *tb_now;
|
||||
void *tb_now;
|
||||
//AJ2D--------------------------------------------------------------------------
|
||||
|
||||
//teawater add for record reg value to ./reg.txt 2005.07.10---------------------
|
||||
FILE *tea_reg_fd;
|
||||
FILE *tea_reg_fd;
|
||||
//AJ2D--------------------------------------------------------------------------
|
||||
|
||||
/*added by ksh in 2005-10-1*/
|
||||
cpu_config_t *cpu;
|
||||
//mem_config_t *mem_bank;
|
||||
cpu_config_t *cpu;
|
||||
//mem_config_t *mem_bank;
|
||||
|
||||
/* added LPC remap function */
|
||||
int vector_remap_flag;
|
||||
u32 vector_remap_addr;
|
||||
u32 vector_remap_size;
|
||||
int vector_remap_flag;
|
||||
u32 vector_remap_addr;
|
||||
u32 vector_remap_size;
|
||||
|
||||
u32 step;
|
||||
u32 cycle;
|
||||
int stop_simulator;
|
||||
conf_object_t *dyncom_cpu;
|
||||
u32 step;
|
||||
u32 cycle;
|
||||
int stop_simulator;
|
||||
conf_object_t *dyncom_cpu;
|
||||
//teawater add DBCT_TEST_SPEED 2005.10.04---------------------------------------
|
||||
#ifdef DBCT_TEST_SPEED
|
||||
uint64_t instr_count;
|
||||
#endif //DBCT_TEST_SPEED
|
||||
// FILE * state_log;
|
||||
uint64_t instr_count;
|
||||
#endif //DBCT_TEST_SPEED
|
||||
// FILE * state_log;
|
||||
//diff log
|
||||
//#if DIFF_STATE
|
||||
FILE * state_log;
|
||||
FILE * state_log;
|
||||
//#endif
|
||||
/* monitored memory for exclusice access */
|
||||
ARMword exclusive_tag_array[128];
|
||||
/* 1 means exclusive access and 0 means open access */
|
||||
ARMword exclusive_access_state;
|
||||
/* monitored memory for exclusice access */
|
||||
ARMword exclusive_tag_array[128];
|
||||
/* 1 means exclusive access and 0 means open access */
|
||||
ARMword exclusive_access_state;
|
||||
|
||||
memory_space_intf space;
|
||||
u32 CurrInstr;
|
||||
u32 last_pc; /* the last pc executed */
|
||||
u32 last_instr; /* the last inst executed */
|
||||
u32 WriteAddr[17];
|
||||
u32 WriteData[17];
|
||||
u32 WritePc[17];
|
||||
u32 CurrWrite;
|
||||
memory_space_intf space;
|
||||
u32 CurrInstr;
|
||||
u32 last_pc; /* the last pc executed */
|
||||
u32 last_instr; /* the last inst executed */
|
||||
u32 WriteAddr[17];
|
||||
u32 WriteData[17];
|
||||
u32 WritePc[17];
|
||||
u32 CurrWrite;
|
||||
};
|
||||
#define DIFF_WRITE 0
|
||||
|
||||
|
|
@ -510,7 +510,7 @@ typedef ARMul_State arm_core_t;
|
|||
#define ARM61 ARM2
|
||||
#define ARM3 ARM2
|
||||
|
||||
#ifdef ARM60 /* previous definition in armopts.h */
|
||||
#ifdef ARM60 /* previous definition in armopts.h */
|
||||
#undef ARM60
|
||||
#endif
|
||||
|
||||
|
|
@ -526,9 +526,9 @@ typedef ARMul_State arm_core_t;
|
|||
* Macros to extract instruction fields *
|
||||
\***************************************************************************/
|
||||
|
||||
#define BIT(n) ( (ARMword)(instr>>(n))&1) /* bit n of instruction */
|
||||
#define BITS(m,n) ( (ARMword)(instr<<(31-(n))) >> ((31-(n))+(m)) ) /* bits m to n of instr */
|
||||
#define TOPBITS(n) (instr >> (n)) /* bits 31 to n of instr */
|
||||
#define BIT(n) ( (ARMword)(instr>>(n))&1) /* bit n of instruction */
|
||||
#define BITS(m,n) ( (ARMword)(instr<<(31-(n))) >> ((31-(n))+(m)) ) /* bits m to n of instr */
|
||||
#define TOPBITS(n) (instr >> (n)) /* bits 31 to n of instr */
|
||||
|
||||
/***************************************************************************\
|
||||
* The hardware vector addresses *
|
||||
|
|
@ -542,7 +542,7 @@ typedef ARMul_State arm_core_t;
|
|||
#define ARMAddrExceptnV 20L
|
||||
#define ARMIRQV 24L
|
||||
#define ARMFIQV 28L
|
||||
#define ARMErrorV 32L /* This is an offset, not an address ! */
|
||||
#define ARMErrorV 32L /* This is an offset, not an address ! */
|
||||
|
||||
#define ARMul_ResetV ARMResetV
|
||||
#define ARMul_UndefinedInstrV ARMUndefinedInstrV
|
||||
|
|
@ -598,7 +598,7 @@ extern "C" {
|
|||
extern void ARMul_EmulateInit (void);
|
||||
extern void ARMul_Reset (ARMul_State * state);
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
}
|
||||
#endif
|
||||
extern ARMul_State *ARMul_NewState (ARMul_State * state);
|
||||
extern ARMword ARMul_DoProg (ARMul_State * state);
|
||||
|
|
@ -608,7 +608,7 @@ extern ARMword ARMul_DoInstr (ARMul_State * state);
|
|||
\***************************************************************************/
|
||||
|
||||
extern void ARMul_ScheduleEvent (ARMul_State * state, unsigned int delay,
|
||||
unsigned (*func) ());
|
||||
unsigned (*func) ());
|
||||
extern void ARMul_EnvokeEvent (ARMul_State * state);
|
||||
extern unsigned int ARMul_Time (ARMul_State * state);
|
||||
|
||||
|
|
@ -617,9 +617,9 @@ extern unsigned int ARMul_Time (ARMul_State * state);
|
|||
\***************************************************************************/
|
||||
|
||||
extern ARMword ARMul_GetReg (ARMul_State * state, unsigned mode,
|
||||
unsigned reg);
|
||||
unsigned reg);
|
||||
extern void ARMul_SetReg (ARMul_State * state, unsigned mode, unsigned reg,
|
||||
ARMword value);
|
||||
ARMword value);
|
||||
extern ARMword ARMul_GetPC (ARMul_State * state);
|
||||
extern ARMword ARMul_GetNextPC (ARMul_State * state);
|
||||
extern void ARMul_SetPC (ARMul_State * state, ARMword value);
|
||||
|
|
@ -637,11 +637,11 @@ extern void ARMul_SetSPSR (ARMul_State * state, ARMword mode, ARMword value);
|
|||
|
||||
extern void ARMul_Abort (ARMul_State * state, ARMword address);
|
||||
#ifdef MODET
|
||||
#define ARMul_ABORTWORD (state->TFlag ? 0xefffdfff : 0xefffffff) /* SWI -1 */
|
||||
#define ARMul_ABORTWORD (state->TFlag ? 0xefffdfff : 0xefffffff) /* SWI -1 */
|
||||
#define ARMul_PREFETCHABORT(address) if (state->AbortAddr == 1) \
|
||||
state->AbortAddr = (address & (state->TFlag ? ~1L : ~3L))
|
||||
#else
|
||||
#define ARMul_ABORTWORD 0xefffffff /* SWI -1 */
|
||||
#define ARMul_ABORTWORD 0xefffffff /* SWI -1 */
|
||||
#define ARMul_PREFETCHABORT(address) if (state->AbortAddr == 1) \
|
||||
state->AbortAddr = (address & ~3L)
|
||||
#endif
|
||||
|
|
@ -654,20 +654,20 @@ extern void ARMul_Abort (ARMul_State * state, ARMword address);
|
|||
\***************************************************************************/
|
||||
|
||||
extern unsigned ARMul_MemoryInit (ARMul_State * state,
|
||||
unsigned int initmemsize);
|
||||
unsigned int initmemsize);
|
||||
extern void ARMul_MemoryExit (ARMul_State * state);
|
||||
|
||||
extern ARMword ARMul_LoadInstrS (ARMul_State * state, ARMword address,
|
||||
ARMword isize);
|
||||
ARMword isize);
|
||||
extern ARMword ARMul_LoadInstrN (ARMul_State * state, ARMword address,
|
||||
ARMword isize);
|
||||
ARMword isize);
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
extern ARMword ARMul_ReLoadInstr (ARMul_State * state, ARMword address,
|
||||
ARMword isize);
|
||||
ARMword isize);
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
}
|
||||
#endif
|
||||
extern ARMword ARMul_LoadWordS (ARMul_State * state, ARMword address);
|
||||
extern ARMword ARMul_LoadWordN (ARMul_State * state, ARMword address);
|
||||
|
|
@ -675,34 +675,34 @@ extern ARMword ARMul_LoadHalfWord (ARMul_State * state, ARMword address);
|
|||
extern ARMword ARMul_LoadByte (ARMul_State * state, ARMword address);
|
||||
|
||||
extern void ARMul_StoreWordS (ARMul_State * state, ARMword address,
|
||||
ARMword data);
|
||||
ARMword data);
|
||||
extern void ARMul_StoreWordN (ARMul_State * state, ARMword address,
|
||||
ARMword data);
|
||||
ARMword data);
|
||||
extern void ARMul_StoreHalfWord (ARMul_State * state, ARMword address,
|
||||
ARMword data);
|
||||
ARMword data);
|
||||
extern void ARMul_StoreByte (ARMul_State * state, ARMword address,
|
||||
ARMword data);
|
||||
ARMword data);
|
||||
|
||||
extern ARMword ARMul_SwapWord (ARMul_State * state, ARMword address,
|
||||
ARMword data);
|
||||
ARMword data);
|
||||
extern ARMword ARMul_SwapByte (ARMul_State * state, ARMword address,
|
||||
ARMword data);
|
||||
ARMword data);
|
||||
|
||||
extern void ARMul_Icycles (ARMul_State * state, unsigned number,
|
||||
ARMword address);
|
||||
ARMword address);
|
||||
extern void ARMul_Ccycles (ARMul_State * state, unsigned number,
|
||||
ARMword address);
|
||||
ARMword address);
|
||||
|
||||
extern ARMword ARMul_ReadWord (ARMul_State * state, ARMword address);
|
||||
extern ARMword ARMul_ReadByte (ARMul_State * state, ARMword address);
|
||||
extern void ARMul_WriteWord (ARMul_State * state, ARMword address,
|
||||
ARMword data);
|
||||
ARMword data);
|
||||
extern void ARMul_WriteByte (ARMul_State * state, ARMword address,
|
||||
ARMword data);
|
||||
ARMword data);
|
||||
|
||||
extern ARMword ARMul_MemAccess (ARMul_State * state, ARMword, ARMword,
|
||||
ARMword, ARMword, ARMword, ARMword, ARMword,
|
||||
ARMword, ARMword, ARMword);
|
||||
ARMword, ARMword, ARMword, ARMword, ARMword,
|
||||
ARMword, ARMword, ARMword);
|
||||
|
||||
/***************************************************************************\
|
||||
* Definitons of things in the co-processor interface *
|
||||
|
|
@ -746,12 +746,12 @@ extern ARMword ARMul_MemAccess (ARMul_State * state, ARMword, ARMword,
|
|||
extern unsigned ARMul_CoProInit (ARMul_State * state);
|
||||
extern void ARMul_CoProExit (ARMul_State * state);
|
||||
extern void ARMul_CoProAttach (ARMul_State * state, unsigned number,
|
||||
ARMul_CPInits * init, ARMul_CPExits * exit,
|
||||
ARMul_LDCs * ldc, ARMul_STCs * stc,
|
||||
ARMul_MRCs * mrc, ARMul_MCRs * mcr,
|
||||
ARMul_MRRCs * mrrc, ARMul_MCRRs * mcrr,
|
||||
ARMul_CDPs * cdp,
|
||||
ARMul_CPReads * read, ARMul_CPWrites * write);
|
||||
ARMul_CPInits * init, ARMul_CPExits * exit,
|
||||
ARMul_LDCs * ldc, ARMul_STCs * stc,
|
||||
ARMul_MRCs * mrc, ARMul_MCRs * mcr,
|
||||
ARMul_MRRCs * mrrc, ARMul_MCRRs * mcrr,
|
||||
ARMul_CDPs * cdp,
|
||||
ARMul_CPReads * read, ARMul_CPWrites * write);
|
||||
extern void ARMul_CoProDetach (ARMul_State * state, unsigned number);
|
||||
|
||||
/***************************************************************************\
|
||||
|
|
@ -775,7 +775,7 @@ extern ARMword ARMul_OSLastErrorP (ARMul_State * state);
|
|||
|
||||
extern ARMword ARMul_Debug (ARMul_State * state, ARMword pc, ARMword instr);
|
||||
extern unsigned ARMul_OSException (ARMul_State * state, ARMword vector,
|
||||
ARMword pc);
|
||||
ARMword pc);
|
||||
extern int rdi_log;
|
||||
|
||||
/***************************************************************************\
|
||||
|
|
@ -783,9 +783,9 @@ extern int rdi_log;
|
|||
\***************************************************************************/
|
||||
|
||||
#ifdef macintosh
|
||||
pascal void SpinCursor (short increment); /* copied from CursorCtl.h */
|
||||
pascal void SpinCursor (short increment); /* copied from CursorCtl.h */
|
||||
# define HOURGLASS SpinCursor( 1 )
|
||||
# define HOURGLASS_RATE 1023 /* 2^n - 1 */
|
||||
# define HOURGLASS_RATE 1023 /* 2^n - 1 */
|
||||
#endif
|
||||
|
||||
//teawater add for arm2x86 2005.02.14-------------------------------------------
|
||||
|
|
@ -821,38 +821,38 @@ pascal void SpinCursor (short increment); /* copied from CursorCtl.h */
|
|||
#define NV 15
|
||||
|
||||
#ifndef NFLAG
|
||||
#define NFLAG state->NFlag
|
||||
#define NFLAG state->NFlag
|
||||
#endif //NFLAG
|
||||
|
||||
#ifndef ZFLAG
|
||||
#define ZFLAG state->ZFlag
|
||||
#define ZFLAG state->ZFlag
|
||||
#endif //ZFLAG
|
||||
|
||||
#ifndef CFLAG
|
||||
#define CFLAG state->CFlag
|
||||
#define CFLAG state->CFlag
|
||||
#endif //CFLAG
|
||||
|
||||
#ifndef VFLAG
|
||||
#define VFLAG state->VFlag
|
||||
#define VFLAG state->VFlag
|
||||
#endif //VFLAG
|
||||
|
||||
#ifndef IFLAG
|
||||
#define IFLAG (state->IFFlags >> 1)
|
||||
#define IFLAG (state->IFFlags >> 1)
|
||||
#endif //IFLAG
|
||||
|
||||
#ifndef FFLAG
|
||||
#define FFLAG (state->IFFlags & 1)
|
||||
#define FFLAG (state->IFFlags & 1)
|
||||
#endif //FFLAG
|
||||
|
||||
#ifndef IFFLAGS
|
||||
#define IFFLAGS state->IFFlags
|
||||
#define IFFLAGS state->IFFlags
|
||||
#endif //VFLAG
|
||||
|
||||
#define FLAG_MASK 0xf0000000
|
||||
#define NBIT_SHIFT 31
|
||||
#define ZBIT_SHIFT 30
|
||||
#define CBIT_SHIFT 29
|
||||
#define VBIT_SHIFT 28
|
||||
#define FLAG_MASK 0xf0000000
|
||||
#define NBIT_SHIFT 31
|
||||
#define ZBIT_SHIFT 30
|
||||
#define CBIT_SHIFT 29
|
||||
#define VBIT_SHIFT 28
|
||||
#ifdef DBCT
|
||||
//teawater change for local tb branch directly jump 2005.10.18------------------
|
||||
#include "dbct/list.h"
|
||||
|
|
@ -875,10 +875,10 @@ pascal void SpinCursor (short increment); /* copied from CursorCtl.h */
|
|||
state->Reg[4],state->Reg[5],state->Reg[6],state->Reg[7], \
|
||||
state->Reg[8],state->Reg[9],state->Reg[10],state->Reg[11], \
|
||||
state->Reg[12],state->Reg[13],state->Reg[14],state->Reg[15], \
|
||||
state->Cpsr, state->Spsr[0], state->Spsr[1], state->Spsr[2],\
|
||||
state->Cpsr, state->Spsr[0], state->Spsr[1], state->Spsr[2],\
|
||||
state->Spsr[3],state->Spsr[4], state->Spsr[5], state->Spsr[6],\
|
||||
state->Mode,state->Bank,state->ErrorCode,state->instr,state->pc,\
|
||||
state->temp,state->loaded,state->decoded);}
|
||||
state->Mode,state->Bank,state->ErrorCode,state->instr,state->pc,\
|
||||
state->temp,state->loaded,state->decoded);}
|
||||
|
||||
#define SKYEYE_OUTMOREREGS(fd) { fprintf ((fd),"\
|
||||
RUs %x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,\
|
||||
|
|
@ -911,13 +911,13 @@ RUn %x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x\n",\
|
|||
state->RegBank[5][4],state->RegBank[5][5],state->RegBank[5][6],state->RegBank[5][7], \
|
||||
state->RegBank[5][8],state->RegBank[5][9],state->RegBank[5][10],state->RegBank[5][11], \
|
||||
state->RegBank[5][12],state->RegBank[5][13],state->RegBank[5][14],state->RegBank[5][15] \
|
||||
);}
|
||||
);}
|
||||
|
||||
|
||||
#define SA1110 0x6901b110
|
||||
#define SA1100 0x4401a100
|
||||
#define PXA250 0x69052100
|
||||
#define PXA270 0x69054110
|
||||
#define PXA250 0x69052100
|
||||
#define PXA270 0x69054110
|
||||
//#define PXA250 0x69052903
|
||||
// 0x69052903; //PXA250 B1 from intel 278522-001.pdf
|
||||
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -22,12 +22,12 @@
|
|||
#if 0
|
||||
typedef struct arm1176jzf-s_mmu_s
|
||||
{
|
||||
tlb_t i_tlb;
|
||||
cache_t i_cache;
|
||||
tlb_t i_tlb;
|
||||
cache_t i_cache;
|
||||
|
||||
tlb_t d_tlb;
|
||||
cache_t d_cache;
|
||||
wb_t wb_t;
|
||||
tlb_t d_tlb;
|
||||
cache_t d_cache;
|
||||
wb_t wb_t;
|
||||
} arm1176jzf-s_mmu_t;
|
||||
#endif
|
||||
extern mmu_ops_t arm1176jzf_s_mmu_ops;
|
||||
|
|
|
|||
|
|
@ -3,85 +3,85 @@
|
|||
|
||||
typedef struct cache_line_t
|
||||
{
|
||||
ARMword tag; /* cache line align address |
|
||||
bit2: last half dirty
|
||||
bit1: first half dirty
|
||||
bit0: cache valid flag
|
||||
*/
|
||||
ARMword pa; /*physical address */
|
||||
ARMword *data; /*array of cached data */
|
||||
ARMword tag; /* cache line align address |
|
||||
bit2: last half dirty
|
||||
bit1: first half dirty
|
||||
bit0: cache valid flag
|
||||
*/
|
||||
ARMword pa; /*physical address */
|
||||
ARMword *data; /*array of cached data */
|
||||
} cache_line_t;
|
||||
#define TAG_VALID_FLAG 0x00000001
|
||||
#define TAG_FIRST_HALF_DIRTY 0x00000002
|
||||
#define TAG_LAST_HALF_DIRTY 0x00000004
|
||||
#define TAG_LAST_HALF_DIRTY 0x00000004
|
||||
|
||||
/*cache set association*/
|
||||
typedef struct cache_set_s
|
||||
{
|
||||
cache_line_t *lines;
|
||||
int cycle;
|
||||
cache_line_t *lines;
|
||||
int cycle;
|
||||
} cache_set_t;
|
||||
|
||||
enum
|
||||
{
|
||||
CACHE_WRITE_BACK,
|
||||
CACHE_WRITE_THROUGH,
|
||||
CACHE_WRITE_BACK,
|
||||
CACHE_WRITE_THROUGH,
|
||||
};
|
||||
|
||||
typedef struct cache_s
|
||||
{
|
||||
int width; /*bytes in a line */
|
||||
int way; /*way of set asscociate */
|
||||
int set; /*num of set */
|
||||
int w_mode; /*write back or write through */
|
||||
//int a_mode; /*alloc mode: random or round-bin*/
|
||||
cache_set_t *sets;
|
||||
int width; /*bytes in a line */
|
||||
int way; /*way of set asscociate */
|
||||
int set; /*num of set */
|
||||
int w_mode; /*write back or write through */
|
||||
//int a_mode; /*alloc mode: random or round-bin*/
|
||||
cache_set_t *sets;
|
||||
/**/} cache_s;
|
||||
|
||||
typedef struct cache_desc_s
|
||||
{
|
||||
int width;
|
||||
int way;
|
||||
int set;
|
||||
int w_mode;
|
||||
int width;
|
||||
int way;
|
||||
int set;
|
||||
int w_mode;
|
||||
// int a_mode;
|
||||
} cache_desc_t;
|
||||
|
||||
|
||||
/*virtual address to cache set index*/
|
||||
#define va_cache_set(va, cache_t) \
|
||||
(((va) / (cache_t)->width) & ((cache_t)->set - 1))
|
||||
(((va) / (cache_t)->width) & ((cache_t)->set - 1))
|
||||
/*virtual address to cahce line aligned*/
|
||||
#define va_cache_align(va, cache_t) \
|
||||
((va) & ~((cache_t)->width - 1))
|
||||
((va) & ~((cache_t)->width - 1))
|
||||
/*virtaul address to cache line word index*/
|
||||
#define va_cache_index(va, cache_t) \
|
||||
(((va) & ((cache_t)->width - 1)) >> WORD_SHT)
|
||||
(((va) & ((cache_t)->width - 1)) >> WORD_SHT)
|
||||
|
||||
/*see Page 558 in arm manual*/
|
||||
/*set/index format value to cache set value*/
|
||||
#define index_cache_set(index, cache_t) \
|
||||
(((index) / (cache_t)->width) & ((cache_t)->set - 1))
|
||||
(((index) / (cache_t)->width) & ((cache_t)->set - 1))
|
||||
|
||||
/*************************cache********************/
|
||||
/* mmu cache init
|
||||
*
|
||||
* @cache_t :cache_t to init
|
||||
* @width :cache line width in byte
|
||||
* @way :way of each cache set
|
||||
* @set :cache set num
|
||||
* @w_mode :cache w_mode
|
||||
* @width :cache line width in byte
|
||||
* @way :way of each cache set
|
||||
* @set :cache set num
|
||||
* @w_mode :cache w_mode
|
||||
*
|
||||
* $ -1: error
|
||||
* 0: sucess
|
||||
* 0: sucess
|
||||
*/
|
||||
int
|
||||
mmu_cache_init (cache_s * cache_t, int width, int way, int set, int w_mode);
|
||||
|
||||
/* free a cache_t's inner data, the ptr self is not freed,
|
||||
* when needed do like below:
|
||||
* mmu_cache_exit(cache);
|
||||
* free(cache_t);
|
||||
* mmu_cache_exit(cache);
|
||||
* free(cache_t);
|
||||
*
|
||||
* @cache_t : the cache_t to free
|
||||
*/
|
||||
|
|
@ -89,40 +89,40 @@ void mmu_cache_exit (cache_s * cache_t);
|
|||
|
||||
/* mmu cache search
|
||||
*
|
||||
* @state :ARMul_State
|
||||
* @cache_t :cache_t to search
|
||||
* @va :virtual address
|
||||
* @state :ARMul_State
|
||||
* @cache_t :cache_t to search
|
||||
* @va :virtual address
|
||||
*
|
||||
* $ NULL: no cache match
|
||||
* cache :cache matched
|
||||
* $ NULL: no cache match
|
||||
* cache :cache matched
|
||||
* */
|
||||
cache_line_t *mmu_cache_search (ARMul_State * state, cache_s * cache_t,
|
||||
ARMword va);
|
||||
ARMword va);
|
||||
|
||||
/* mmu cache search by set/index
|
||||
*
|
||||
* @state :ARMul_State
|
||||
* @cache_t :cache_t to search
|
||||
* @state :ARMul_State
|
||||
* @cache_t :cache_t to search
|
||||
* @index :set/index value.
|
||||
*
|
||||
* $ NULL: no cache match
|
||||
* cache :cache matched
|
||||
* $ NULL: no cache match
|
||||
* cache :cache matched
|
||||
* */
|
||||
|
||||
cache_line_t *mmu_cache_search_by_index (ARMul_State * state,
|
||||
cache_s * cache_t, ARMword index);
|
||||
cache_s * cache_t, ARMword index);
|
||||
|
||||
/* mmu cache alloc
|
||||
*
|
||||
* @state :ARMul_State
|
||||
* @cache_t :cache_t to alloc from
|
||||
* @va :virtual address that require cache alloc, need not cache aligned
|
||||
* @pa :physical address of va
|
||||
* @cache_t :cache_t to alloc from
|
||||
* @va :virtual address that require cache alloc, need not cache aligned
|
||||
* @pa :physical address of va
|
||||
*
|
||||
* $ cache_alloced, always alloc OK
|
||||
* $ cache_alloced, always alloc OK
|
||||
*/
|
||||
cache_line_t *mmu_cache_alloc (ARMul_State * state, cache_s * cache_t,
|
||||
ARMword va, ARMword pa);
|
||||
ARMword va, ARMword pa);
|
||||
|
||||
/* mmu_cache_write_back write cache data to memory
|
||||
*
|
||||
|
|
@ -132,31 +132,31 @@ cache_line_t *mmu_cache_alloc (ARMul_State * state, cache_s * cache_t,
|
|||
*/
|
||||
void
|
||||
mmu_cache_write_back (ARMul_State * state, cache_s * cache_t,
|
||||
cache_line_t * cache);
|
||||
cache_line_t * cache);
|
||||
|
||||
/* mmu_cache_clean: clean a cache of va in cache_t
|
||||
*
|
||||
* @state :ARMul_State
|
||||
* @cache_t :cache_t to clean
|
||||
* @va :virtaul address
|
||||
* @state :ARMul_State
|
||||
* @cache_t :cache_t to clean
|
||||
* @va :virtaul address
|
||||
*/
|
||||
void mmu_cache_clean (ARMul_State * state, cache_s * cache_t, ARMword va);
|
||||
void
|
||||
mmu_cache_clean_by_index (ARMul_State * state, cache_s * cache_t,
|
||||
ARMword index);
|
||||
ARMword index);
|
||||
|
||||
/* mmu_cache_invalidate : invalidate a cache of va
|
||||
*
|
||||
* @state :ARMul_State
|
||||
* @cache_t :cache_t to invalid
|
||||
* @va :virt_addr to invalid
|
||||
* @state :ARMul_State
|
||||
* @cache_t :cache_t to invalid
|
||||
* @va :virt_addr to invalid
|
||||
*/
|
||||
void
|
||||
mmu_cache_invalidate (ARMul_State * state, cache_s * cache_t, ARMword va);
|
||||
|
||||
void
|
||||
mmu_cache_invalidate_by_index (ARMul_State * state, cache_s * cache_t,
|
||||
ARMword index);
|
||||
ARMword index);
|
||||
|
||||
void mmu_cache_invalidate_all (ARMul_State * state, cache_s * cache_t);
|
||||
|
||||
|
|
|
|||
|
|
@ -3,10 +3,10 @@
|
|||
|
||||
enum rb_type_t
|
||||
{
|
||||
RB_INVALID = 0, //invalid
|
||||
RB_1, //1 word
|
||||
RB_4, //4 word
|
||||
RB_8, //8 word
|
||||
RB_INVALID = 0, //invalid
|
||||
RB_1, //1 word
|
||||
RB_4, //4 word
|
||||
RB_8, //8 word
|
||||
};
|
||||
|
||||
/*bytes of each rb_type*/
|
||||
|
|
@ -15,21 +15,21 @@ extern ARMword rb_masks[];
|
|||
#define RB_WORD_NUM 8
|
||||
typedef struct rb_entry_s
|
||||
{
|
||||
ARMword data[RB_WORD_NUM]; //array to store data
|
||||
ARMword va; //first word va
|
||||
int type; //rb type
|
||||
fault_t fault; //fault set by rb alloc
|
||||
ARMword data[RB_WORD_NUM]; //array to store data
|
||||
ARMword va; //first word va
|
||||
int type; //rb type
|
||||
fault_t fault; //fault set by rb alloc
|
||||
} rb_entry_t;
|
||||
|
||||
typedef struct rb_s
|
||||
{
|
||||
int num;
|
||||
rb_entry_t *entrys;
|
||||
int num;
|
||||
rb_entry_t *entrys;
|
||||
} rb_s;
|
||||
|
||||
/*mmu_rb_init
|
||||
* @rb_t :rb_t to init
|
||||
* @num :number of entry
|
||||
* @rb_t :rb_t to init
|
||||
* @num :number of entry
|
||||
* */
|
||||
int mmu_rb_init (rb_s * rb_t, int num);
|
||||
|
||||
|
|
@ -38,11 +38,11 @@ void mmu_rb_exit (rb_s * rb_t);
|
|||
|
||||
|
||||
/*mmu_rb_search
|
||||
* @rb_t :rb_t to serach
|
||||
* @va :va address to math
|
||||
* @rb_t :rb_t to serach
|
||||
* @va :va address to math
|
||||
*
|
||||
* $ NULL :not match
|
||||
* NO-NULL:
|
||||
* $ NULL :not match
|
||||
* NO-NULL:
|
||||
* */
|
||||
rb_entry_t *mmu_rb_search (rb_s * rb_t, ARMword va);
|
||||
|
||||
|
|
@ -50,6 +50,6 @@ rb_entry_t *mmu_rb_search (rb_s * rb_t, ARMword va);
|
|||
void mmu_rb_invalidate_entry (rb_s * rb_t, int i);
|
||||
void mmu_rb_invalidate_all (rb_s * rb_t);
|
||||
void mmu_rb_load (ARMul_State * state, rb_s * rb_t, int i_rb,
|
||||
int type, ARMword va);
|
||||
int type, ARMword va);
|
||||
|
||||
#endif /*_MMU_RB_H_*/
|
||||
|
|
|
|||
|
|
@ -3,81 +3,81 @@
|
|||
|
||||
typedef enum tlb_mapping_t
|
||||
{
|
||||
TLB_INVALID = 0,
|
||||
TLB_SMALLPAGE = 1,
|
||||
TLB_LARGEPAGE = 2,
|
||||
TLB_SECTION = 3,
|
||||
TLB_ESMALLPAGE = 4,
|
||||
TLB_TINYPAGE = 5
|
||||
TLB_INVALID = 0,
|
||||
TLB_SMALLPAGE = 1,
|
||||
TLB_LARGEPAGE = 2,
|
||||
TLB_SECTION = 3,
|
||||
TLB_ESMALLPAGE = 4,
|
||||
TLB_TINYPAGE = 5
|
||||
} tlb_mapping_t;
|
||||
|
||||
extern ARMword tlb_masks[];
|
||||
|
||||
/* Permissions bits in a TLB entry:
|
||||
*
|
||||
* 31 12 11 10 9 8 7 6 5 4 3 2 1 0
|
||||
* +-------------+-----+-----+-----+-----+---+---+-------+
|
||||
* 31 12 11 10 9 8 7 6 5 4 3 2 1 0
|
||||
* +-------------+-----+-----+-----+-----+---+---+-------+
|
||||
* Page:| | ap3 | ap2 | ap1 | ap0 | C | B | |
|
||||
* +-------------+-----+-----+-----+-----+---+---+-------+
|
||||
* +-------------+-----+-----+-----+-----+---+---+-------+
|
||||
*
|
||||
* 31 12 11 10 9 4 3 2 1 0
|
||||
* +-------------+-----+-----------------+---+---+-------+
|
||||
* Section: | | AP | | C | B | |
|
||||
* +-------------+-----+-----------------+---+---+-------+
|
||||
* 31 12 11 10 9 4 3 2 1 0
|
||||
* +-------------+-----+-----------------+---+---+-------+
|
||||
* Section: | | AP | | C | B | |
|
||||
* +-------------+-----+-----------------+---+---+-------+
|
||||
*/
|
||||
|
||||
/*
|
||||
section:
|
||||
section base address [31:20]
|
||||
AP - table 8-2, page 8-8
|
||||
domain
|
||||
C,B
|
||||
section base address [31:20]
|
||||
AP - table 8-2, page 8-8
|
||||
domain
|
||||
C,B
|
||||
|
||||
page:
|
||||
page base address [31:16] or [31:12]
|
||||
ap[3:0]
|
||||
domain (from L1)
|
||||
C,B
|
||||
page base address [31:16] or [31:12]
|
||||
ap[3:0]
|
||||
domain (from L1)
|
||||
C,B
|
||||
*/
|
||||
|
||||
|
||||
typedef struct tlb_entry_t
|
||||
{
|
||||
ARMword virt_addr;
|
||||
ARMword phys_addr;
|
||||
ARMword perms;
|
||||
ARMword domain;
|
||||
tlb_mapping_t mapping;
|
||||
ARMword virt_addr;
|
||||
ARMword phys_addr;
|
||||
ARMword perms;
|
||||
ARMword domain;
|
||||
tlb_mapping_t mapping;
|
||||
} tlb_entry_t;
|
||||
|
||||
typedef struct tlb_s
|
||||
{
|
||||
int num; /*num of tlb entry */
|
||||
int cycle; /*current tlb cycle */
|
||||
tlb_entry_t *entrys;
|
||||
int num; /*num of tlb entry */
|
||||
int cycle; /*current tlb cycle */
|
||||
tlb_entry_t *entrys;
|
||||
} tlb_s;
|
||||
|
||||
|
||||
#define tlb_c_flag(tlb) \
|
||||
((tlb)->perms & 0x8)
|
||||
((tlb)->perms & 0x8)
|
||||
#define tlb_b_flag(tlb) \
|
||||
((tlb)->perms & 0x4)
|
||||
((tlb)->perms & 0x4)
|
||||
|
||||
#define tlb_va_to_pa(tlb, va) \
|
||||
(\
|
||||
{\
|
||||
ARMword mask = tlb_masks[tlb->mapping]; \
|
||||
(tlb->phys_addr & mask) | (va & ~mask);\
|
||||
ARMword mask = tlb_masks[tlb->mapping]; \
|
||||
(tlb->phys_addr & mask) | (va & ~mask);\
|
||||
}\
|
||||
)
|
||||
|
||||
fault_t
|
||||
check_access (ARMul_State * state, ARMword virt_addr, tlb_entry_t * tlb,
|
||||
int read);
|
||||
int read);
|
||||
|
||||
fault_t
|
||||
translate (ARMul_State * state, ARMword virt_addr, tlb_s * tlb_t,
|
||||
tlb_entry_t ** tlb);
|
||||
tlb_entry_t ** tlb);
|
||||
|
||||
int mmu_tlb_init (tlb_s * tlb_t, int num);
|
||||
|
||||
|
|
@ -89,6 +89,6 @@ void
|
|||
mmu_tlb_invalidate_entry (ARMul_State * state, tlb_s * tlb_t, ARMword addr);
|
||||
|
||||
tlb_entry_t *mmu_tlb_search (ARMul_State * state, tlb_s * tlb_t,
|
||||
ARMword virt_addr);
|
||||
ARMword virt_addr);
|
||||
|
||||
#endif /*_MMU_TLB_H_*/
|
||||
#endif /*_MMU_TLB_H_*/
|
||||
|
|
|
|||
|
|
@ -3,34 +3,34 @@
|
|||
|
||||
typedef struct wb_entry_s
|
||||
{
|
||||
ARMword pa; //phy_addr
|
||||
ARMbyte *data; //data
|
||||
int nb; //number byte to write
|
||||
ARMword pa; //phy_addr
|
||||
ARMbyte *data; //data
|
||||
int nb; //number byte to write
|
||||
} wb_entry_t;
|
||||
|
||||
typedef struct wb_s
|
||||
{
|
||||
int num; //number of wb_entry
|
||||
int nb; //number of byte of each entry
|
||||
int first; //
|
||||
int last; //
|
||||
int used; //
|
||||
wb_entry_t *entrys;
|
||||
int num; //number of wb_entry
|
||||
int nb; //number of byte of each entry
|
||||
int first; //
|
||||
int last; //
|
||||
int used; //
|
||||
wb_entry_t *entrys;
|
||||
} wb_s;
|
||||
|
||||
typedef struct wb_desc_s
|
||||
{
|
||||
int num;
|
||||
int nb;
|
||||
int num;
|
||||
int nb;
|
||||
} wb_desc_t;
|
||||
|
||||
/* wb_init
|
||||
* @wb_t :wb_t to init
|
||||
* @num :num of entrys
|
||||
* @nw :num of word of each entry
|
||||
* @wb_t :wb_t to init
|
||||
* @num :num of entrys
|
||||
* @nw :num of word of each entry
|
||||
*
|
||||
* $ -1:error
|
||||
* 0:ok
|
||||
* $ -1:error
|
||||
* 0:ok
|
||||
* */
|
||||
int mmu_wb_init (wb_s * wb_t, int num, int nb);
|
||||
|
||||
|
|
@ -42,17 +42,17 @@ void mmu_wb_exit (wb_s * wb);
|
|||
|
||||
|
||||
/* wb_write_bytes :put bytess in Write Buffer
|
||||
* @state: ARMul_State
|
||||
* @wb_t: write buffer
|
||||
* @pa: physical address
|
||||
* @data: data ptr
|
||||
* @n number of byte to write
|
||||
* @state: ARMul_State
|
||||
* @wb_t: write buffer
|
||||
* @pa: physical address
|
||||
* @data: data ptr
|
||||
* @n number of byte to write
|
||||
*
|
||||
* Note: write buffer merge is not implemented, can be done late
|
||||
* */
|
||||
void
|
||||
mmu_wb_write_bytess (ARMul_State * state, wb_s * wb_t, ARMword pa,
|
||||
ARMbyte * data, int n);
|
||||
ARMbyte * data, int n);
|
||||
|
||||
|
||||
/* wb_drain_all
|
||||
|
|
|
|||
Loading…
Reference in a new issue