Fix stencil func registers, make clip control equivalent to how it was before, but surely wrong.
This commit is contained in:
parent
c3cae9d992
commit
4496030ea9
8 changed files with 51 additions and 44 deletions
|
@ -61,7 +61,7 @@ void SetupDirtyRenderTargets(Maxwell3D::DirtyState::Tables& tables) {
|
||||||
}
|
}
|
||||||
|
|
||||||
void SetupDirtyShaders(Maxwell3D::DirtyState::Tables& tables) {
|
void SetupDirtyShaders(Maxwell3D::DirtyState::Tables& tables) {
|
||||||
FillBlock(tables[0], OFF(pipelines), NUM(pipelines) * Maxwell3D::Regs::MaxShaderProgram,
|
FillBlock(tables[0], OFF(pipelines), NUM(pipelines[0]) * Maxwell3D::Regs::MaxShaderProgram,
|
||||||
Shaders);
|
Shaders);
|
||||||
}
|
}
|
||||||
} // Anonymous namespace
|
} // Anonymous namespace
|
||||||
|
|
|
@ -74,15 +74,15 @@ void Maxwell3D::InitializeRegisterDefaults() {
|
||||||
regs.stencil_front_op.zfail = Regs::StencilOp::Op::Keep_D3D;
|
regs.stencil_front_op.zfail = Regs::StencilOp::Op::Keep_D3D;
|
||||||
regs.stencil_front_op.zpass = Regs::StencilOp::Op::Keep_D3D;
|
regs.stencil_front_op.zpass = Regs::StencilOp::Op::Keep_D3D;
|
||||||
regs.stencil_front_op.func = Regs::ComparisonOp::Always_GL;
|
regs.stencil_front_op.func = Regs::ComparisonOp::Always_GL;
|
||||||
regs.stencil_front_func.func_mask = 0xFFFFFFFF;
|
regs.stencil_front_func_mask = 0xFFFFFFFF;
|
||||||
regs.stencil_front_func.mask = 0xFFFFFFFF;
|
regs.stencil_front_mask = 0xFFFFFFFF;
|
||||||
regs.stencil_two_side_enable = 1;
|
regs.stencil_two_side_enable = 1;
|
||||||
regs.stencil_back_op.fail = Regs::StencilOp::Op::Keep_D3D;
|
regs.stencil_back_op.fail = Regs::StencilOp::Op::Keep_D3D;
|
||||||
regs.stencil_back_op.zfail = Regs::StencilOp::Op::Keep_D3D;
|
regs.stencil_back_op.zfail = Regs::StencilOp::Op::Keep_D3D;
|
||||||
regs.stencil_back_op.zpass = Regs::StencilOp::Op::Keep_D3D;
|
regs.stencil_back_op.zpass = Regs::StencilOp::Op::Keep_D3D;
|
||||||
regs.stencil_back_op.func = Regs::ComparisonOp::Always_GL;
|
regs.stencil_back_op.func = Regs::ComparisonOp::Always_GL;
|
||||||
regs.stencil_back_func.func_mask = 0xFFFFFFFF;
|
regs.stencil_back_func_mask = 0xFFFFFFFF;
|
||||||
regs.stencil_back_func.mask = 0xFFFFFFFF;
|
regs.stencil_back_mask = 0xFFFFFFFF;
|
||||||
|
|
||||||
regs.depth_test_func = Regs::ComparisonOp::Always_GL;
|
regs.depth_test_func = Regs::ComparisonOp::Always_GL;
|
||||||
regs.gl_front_face = Regs::FrontFace::CounterClockWise;
|
regs.gl_front_face = Regs::FrontFace::CounterClockWise;
|
||||||
|
|
|
@ -1795,12 +1795,6 @@ public:
|
||||||
ComparisonOp func;
|
ComparisonOp func;
|
||||||
};
|
};
|
||||||
|
|
||||||
struct StencilFunc {
|
|
||||||
s32 ref;
|
|
||||||
u32 func_mask;
|
|
||||||
u32 mask;
|
|
||||||
};
|
|
||||||
|
|
||||||
struct PsSaturate {
|
struct PsSaturate {
|
||||||
// Opposite of DepthMode
|
// Opposite of DepthMode
|
||||||
enum class Depth : u32 {
|
enum class Depth : u32 {
|
||||||
|
@ -2737,7 +2731,9 @@ public:
|
||||||
u32 post_z_pixel_imask; ///< 0x0F1C
|
u32 post_z_pixel_imask; ///< 0x0F1C
|
||||||
INSERT_PADDING_BYTES_NOINIT(0x20);
|
INSERT_PADDING_BYTES_NOINIT(0x20);
|
||||||
ConstantColorRendering const_color_rendering; ///< 0x0F40
|
ConstantColorRendering const_color_rendering; ///< 0x0F40
|
||||||
StencilFunc stencil_back_func; ///< 0x0F54
|
s32 stencil_back_ref; ///< 0x0F54
|
||||||
|
u32 stencil_back_mask; ///< 0x0F58
|
||||||
|
u32 stencil_back_func_mask; ///< 0x0F5C
|
||||||
INSERT_PADDING_BYTES_NOINIT(0x24);
|
INSERT_PADDING_BYTES_NOINIT(0x24);
|
||||||
VertexStreamSubstitute vertex_stream_substitute; ///< 0x0F84
|
VertexStreamSubstitute vertex_stream_substitute; ///< 0x0F84
|
||||||
u32 line_mode_clip_generated_edge_do_not_draw; ///< 0x0F8C
|
u32 line_mode_clip_generated_edge_do_not_draw; ///< 0x0F8C
|
||||||
|
@ -2855,7 +2851,9 @@ public:
|
||||||
Blend blend; ///< 0x133C
|
Blend blend; ///< 0x133C
|
||||||
u32 stencil_enable; ///< 0x1380
|
u32 stencil_enable; ///< 0x1380
|
||||||
StencilOp stencil_front_op; ///< 0x1384
|
StencilOp stencil_front_op; ///< 0x1384
|
||||||
StencilFunc stencil_front_func; ///< 0x1394
|
s32 stencil_front_ref; ///< 0x1394
|
||||||
|
s32 stencil_front_func_mask; ///< 0x1398
|
||||||
|
s32 stencil_front_mask; ///< 0x139C
|
||||||
INSERT_PADDING_BYTES_NOINIT(0x4);
|
INSERT_PADDING_BYTES_NOINIT(0x4);
|
||||||
u32 draw_auto_start_byte_count; ///< 0x13A4
|
u32 draw_auto_start_byte_count; ///< 0x13A4
|
||||||
PsSaturate frag_color_clamp; ///< 0x13A8
|
PsSaturate frag_color_clamp; ///< 0x13A8
|
||||||
|
@ -3311,7 +3309,9 @@ ASSERT_REG_POSITION(vpc_perf, 0x0F14);
|
||||||
ASSERT_REG_POSITION(pm_local_trigger, 0x0F18);
|
ASSERT_REG_POSITION(pm_local_trigger, 0x0F18);
|
||||||
ASSERT_REG_POSITION(post_z_pixel_imask, 0x0F1C);
|
ASSERT_REG_POSITION(post_z_pixel_imask, 0x0F1C);
|
||||||
ASSERT_REG_POSITION(const_color_rendering, 0x0F40);
|
ASSERT_REG_POSITION(const_color_rendering, 0x0F40);
|
||||||
ASSERT_REG_POSITION(stencil_back_func, 0x0F54);
|
ASSERT_REG_POSITION(stencil_back_ref, 0x0F54);
|
||||||
|
ASSERT_REG_POSITION(stencil_back_mask, 0x0F58);
|
||||||
|
ASSERT_REG_POSITION(stencil_back_func_mask, 0x0F5C);
|
||||||
ASSERT_REG_POSITION(vertex_stream_substitute, 0x0F84);
|
ASSERT_REG_POSITION(vertex_stream_substitute, 0x0F84);
|
||||||
ASSERT_REG_POSITION(line_mode_clip_generated_edge_do_not_draw, 0x0F8C);
|
ASSERT_REG_POSITION(line_mode_clip_generated_edge_do_not_draw, 0x0F8C);
|
||||||
ASSERT_REG_POSITION(color_mask_common, 0x0F90);
|
ASSERT_REG_POSITION(color_mask_common, 0x0F90);
|
||||||
|
@ -3416,7 +3416,9 @@ ASSERT_REG_POSITION(invalidate_texture_data_cache_lines, 0x1338);
|
||||||
ASSERT_REG_POSITION(blend, 0x133C);
|
ASSERT_REG_POSITION(blend, 0x133C);
|
||||||
ASSERT_REG_POSITION(stencil_enable, 0x1380);
|
ASSERT_REG_POSITION(stencil_enable, 0x1380);
|
||||||
ASSERT_REG_POSITION(stencil_front_op, 0x1384);
|
ASSERT_REG_POSITION(stencil_front_op, 0x1384);
|
||||||
ASSERT_REG_POSITION(stencil_front_func, 0x1394);
|
ASSERT_REG_POSITION(stencil_front_ref, 0x1394);
|
||||||
|
ASSERT_REG_POSITION(stencil_front_func_mask, 0x1398);
|
||||||
|
ASSERT_REG_POSITION(stencil_front_mask, 0x139C);
|
||||||
ASSERT_REG_POSITION(draw_auto_start_byte_count, 0x13A4);
|
ASSERT_REG_POSITION(draw_auto_start_byte_count, 0x13A4);
|
||||||
ASSERT_REG_POSITION(frag_color_clamp, 0x13A8);
|
ASSERT_REG_POSITION(frag_color_clamp, 0x13A8);
|
||||||
ASSERT_REG_POSITION(window_origin, 0x13AC);
|
ASSERT_REG_POSITION(window_origin, 0x13AC);
|
||||||
|
|
|
@ -658,8 +658,13 @@ void RasterizerOpenGL::SyncDepthClamp() {
|
||||||
}
|
}
|
||||||
flags[Dirty::DepthClampEnabled] = false;
|
flags[Dirty::DepthClampEnabled] = false;
|
||||||
|
|
||||||
oglEnable(GL_DEPTH_CLAMP, maxwell3d->regs.viewport_clip_control.geometry_clip !=
|
bool depth_clamp_disabled{maxwell3d->regs.viewport_clip_control.geometry_clip ==
|
||||||
Maxwell::ViewportClipControl::GeometryClip::Passthrough);
|
Maxwell::ViewportClipControl::GeometryClip::Passthrough ||
|
||||||
|
maxwell3d->regs.viewport_clip_control.geometry_clip ==
|
||||||
|
Maxwell::ViewportClipControl::GeometryClip::FrustumXYZ ||
|
||||||
|
maxwell3d->regs.viewport_clip_control.geometry_clip ==
|
||||||
|
Maxwell::ViewportClipControl::GeometryClip::FrustumZ};
|
||||||
|
oglEnable(GL_DEPTH_CLAMP, !depth_clamp_disabled);
|
||||||
}
|
}
|
||||||
|
|
||||||
void RasterizerOpenGL::SyncClipEnabled(u32 clip_mask) {
|
void RasterizerOpenGL::SyncClipEnabled(u32 clip_mask) {
|
||||||
|
@ -746,19 +751,19 @@ void RasterizerOpenGL::SyncStencilTestState() {
|
||||||
oglEnable(GL_STENCIL_TEST, regs.stencil_enable);
|
oglEnable(GL_STENCIL_TEST, regs.stencil_enable);
|
||||||
|
|
||||||
glStencilFuncSeparate(GL_FRONT, MaxwellToGL::ComparisonOp(regs.stencil_front_op.func),
|
glStencilFuncSeparate(GL_FRONT, MaxwellToGL::ComparisonOp(regs.stencil_front_op.func),
|
||||||
regs.stencil_front_func.ref, regs.stencil_front_func.func_mask);
|
regs.stencil_front_ref, regs.stencil_front_func_mask);
|
||||||
glStencilOpSeparate(GL_FRONT, MaxwellToGL::StencilOp(regs.stencil_front_op.fail),
|
glStencilOpSeparate(GL_FRONT, MaxwellToGL::StencilOp(regs.stencil_front_op.fail),
|
||||||
MaxwellToGL::StencilOp(regs.stencil_front_op.zfail),
|
MaxwellToGL::StencilOp(regs.stencil_front_op.zfail),
|
||||||
MaxwellToGL::StencilOp(regs.stencil_front_op.zpass));
|
MaxwellToGL::StencilOp(regs.stencil_front_op.zpass));
|
||||||
glStencilMaskSeparate(GL_FRONT, regs.stencil_front_func.mask);
|
glStencilMaskSeparate(GL_FRONT, regs.stencil_front_mask);
|
||||||
|
|
||||||
if (regs.stencil_two_side_enable) {
|
if (regs.stencil_two_side_enable) {
|
||||||
glStencilFuncSeparate(GL_BACK, MaxwellToGL::ComparisonOp(regs.stencil_back_op.func),
|
glStencilFuncSeparate(GL_BACK, MaxwellToGL::ComparisonOp(regs.stencil_back_op.func),
|
||||||
regs.stencil_back_func.ref, regs.stencil_back_func.mask);
|
regs.stencil_back_ref, regs.stencil_back_mask);
|
||||||
glStencilOpSeparate(GL_BACK, MaxwellToGL::StencilOp(regs.stencil_back_op.fail),
|
glStencilOpSeparate(GL_BACK, MaxwellToGL::StencilOp(regs.stencil_back_op.fail),
|
||||||
MaxwellToGL::StencilOp(regs.stencil_back_op.zfail),
|
MaxwellToGL::StencilOp(regs.stencil_back_op.zfail),
|
||||||
MaxwellToGL::StencilOp(regs.stencil_back_op.zpass));
|
MaxwellToGL::StencilOp(regs.stencil_back_op.zpass));
|
||||||
glStencilMaskSeparate(GL_BACK, regs.stencil_back_func.mask);
|
glStencilMaskSeparate(GL_BACK, regs.stencil_back_mask);
|
||||||
} else {
|
} else {
|
||||||
glStencilFuncSeparate(GL_BACK, GL_ALWAYS, 0, 0xFFFFFFFF);
|
glStencilFuncSeparate(GL_BACK, GL_ALWAYS, 0, 0xFFFFFFFF);
|
||||||
glStencilOpSeparate(GL_BACK, GL_KEEP, GL_KEEP, GL_KEEP);
|
glStencilOpSeparate(GL_BACK, GL_KEEP, GL_KEEP, GL_KEEP);
|
||||||
|
|
|
@ -100,14 +100,12 @@ void SetupDirtyDepthTest(Tables& tables) {
|
||||||
|
|
||||||
void SetupDirtyStencilTest(Tables& tables) {
|
void SetupDirtyStencilTest(Tables& tables) {
|
||||||
static constexpr std::array offsets = {
|
static constexpr std::array offsets = {
|
||||||
OFF(stencil_enable), OFF(stencil_front_op.func),
|
OFF(stencil_enable), OFF(stencil_front_op.func), OFF(stencil_front_ref),
|
||||||
OFF(stencil_front_func.ref), OFF(stencil_front_func.func_mask),
|
OFF(stencil_front_func_mask), OFF(stencil_front_op.fail), OFF(stencil_front_op.zfail),
|
||||||
OFF(stencil_front_op.fail), OFF(stencil_front_op.zfail),
|
OFF(stencil_front_op.zpass), OFF(stencil_front_mask), OFF(stencil_two_side_enable),
|
||||||
OFF(stencil_front_op.zpass), OFF(stencil_front_func.mask),
|
OFF(stencil_back_op.func), OFF(stencil_back_ref), OFF(stencil_back_func_mask),
|
||||||
OFF(stencil_two_side_enable), OFF(stencil_back_op.func),
|
OFF(stencil_back_op.fail), OFF(stencil_back_op.zfail), OFF(stencil_back_op.zpass),
|
||||||
OFF(stencil_back_func.ref), OFF(stencil_back_func.func_mask),
|
OFF(stencil_back_mask)};
|
||||||
OFF(stencil_back_op.fail), OFF(stencil_back_op.zfail),
|
|
||||||
OFF(stencil_back_op.zpass), OFF(stencil_back_func.mask)};
|
|
||||||
for (const auto offset : offsets) {
|
for (const auto offset : offsets) {
|
||||||
tables[0][offset] = StencilTest;
|
tables[0][offset] = StencilTest;
|
||||||
}
|
}
|
||||||
|
|
|
@ -63,7 +63,11 @@ void FixedPipelineState::Refresh(Tegra::Engines::Maxwell3D& maxwell3d,
|
||||||
primitive_restart_enable.Assign(regs.primitive_restart.enabled != 0 ? 1 : 0);
|
primitive_restart_enable.Assign(regs.primitive_restart.enabled != 0 ? 1 : 0);
|
||||||
depth_bias_enable.Assign(enabled_lut[POLYGON_OFFSET_ENABLE_LUT[topology_index]] != 0 ? 1 : 0);
|
depth_bias_enable.Assign(enabled_lut[POLYGON_OFFSET_ENABLE_LUT[topology_index]] != 0 ? 1 : 0);
|
||||||
depth_clamp_disabled.Assign(regs.viewport_clip_control.geometry_clip ==
|
depth_clamp_disabled.Assign(regs.viewport_clip_control.geometry_clip ==
|
||||||
Maxwell::ViewportClipControl::GeometryClip::Passthrough);
|
Maxwell::ViewportClipControl::GeometryClip::Passthrough ||
|
||||||
|
regs.viewport_clip_control.geometry_clip ==
|
||||||
|
Maxwell::ViewportClipControl::GeometryClip::FrustumXYZ ||
|
||||||
|
regs.viewport_clip_control.geometry_clip ==
|
||||||
|
Maxwell::ViewportClipControl::GeometryClip::FrustumZ);
|
||||||
ndc_minus_one_to_one.Assign(regs.depth_mode == Maxwell::DepthMode::MinusOneToOne ? 1 : 0);
|
ndc_minus_one_to_one.Assign(regs.depth_mode == Maxwell::DepthMode::MinusOneToOne ? 1 : 0);
|
||||||
polygon_mode.Assign(PackPolygonMode(regs.polygon_mode_front));
|
polygon_mode.Assign(PackPolygonMode(regs.polygon_mode_front));
|
||||||
patch_control_points_minus_one.Assign(regs.patch_vertices - 1);
|
patch_control_points_minus_one.Assign(regs.patch_vertices - 1);
|
||||||
|
|
|
@ -772,11 +772,10 @@ void RasterizerVulkan::UpdateStencilFaces(Tegra::Engines::Maxwell3D::Regs& regs)
|
||||||
if (regs.stencil_two_side_enable) {
|
if (regs.stencil_two_side_enable) {
|
||||||
// Separate values per face
|
// Separate values per face
|
||||||
scheduler.Record(
|
scheduler.Record(
|
||||||
[front_ref = regs.stencil_front_func.ref,
|
[front_ref = regs.stencil_front_ref, front_write_mask = regs.stencil_front_mask,
|
||||||
front_write_mask = regs.stencil_front_func.mask,
|
front_test_mask = regs.stencil_front_func_mask, back_ref = regs.stencil_back_ref,
|
||||||
front_test_mask = regs.stencil_front_func.func_mask,
|
back_write_mask = regs.stencil_back_mask,
|
||||||
back_ref = regs.stencil_back_func.ref, back_write_mask = regs.stencil_back_func.mask,
|
back_test_mask = regs.stencil_back_func_mask](vk::CommandBuffer cmdbuf) {
|
||||||
back_test_mask = regs.stencil_back_func.func_mask](vk::CommandBuffer cmdbuf) {
|
|
||||||
// Front face
|
// Front face
|
||||||
cmdbuf.SetStencilReference(VK_STENCIL_FACE_FRONT_BIT, front_ref);
|
cmdbuf.SetStencilReference(VK_STENCIL_FACE_FRONT_BIT, front_ref);
|
||||||
cmdbuf.SetStencilWriteMask(VK_STENCIL_FACE_FRONT_BIT, front_write_mask);
|
cmdbuf.SetStencilWriteMask(VK_STENCIL_FACE_FRONT_BIT, front_write_mask);
|
||||||
|
@ -789,9 +788,8 @@ void RasterizerVulkan::UpdateStencilFaces(Tegra::Engines::Maxwell3D::Regs& regs)
|
||||||
});
|
});
|
||||||
} else {
|
} else {
|
||||||
// Front face defines both faces
|
// Front face defines both faces
|
||||||
scheduler.Record([ref = regs.stencil_front_func.ref,
|
scheduler.Record([ref = regs.stencil_front_ref, write_mask = regs.stencil_front_mask,
|
||||||
write_mask = regs.stencil_front_func.mask,
|
test_mask = regs.stencil_front_func_mask](vk::CommandBuffer cmdbuf) {
|
||||||
test_mask = regs.stencil_front_func.func_mask](vk::CommandBuffer cmdbuf) {
|
|
||||||
cmdbuf.SetStencilReference(VK_STENCIL_FACE_FRONT_AND_BACK, ref);
|
cmdbuf.SetStencilReference(VK_STENCIL_FACE_FRONT_AND_BACK, ref);
|
||||||
cmdbuf.SetStencilWriteMask(VK_STENCIL_FACE_FRONT_AND_BACK, write_mask);
|
cmdbuf.SetStencilWriteMask(VK_STENCIL_FACE_FRONT_AND_BACK, write_mask);
|
||||||
cmdbuf.SetStencilCompareMask(VK_STENCIL_FACE_FRONT_AND_BACK, test_mask);
|
cmdbuf.SetStencilCompareMask(VK_STENCIL_FACE_FRONT_AND_BACK, test_mask);
|
||||||
|
|
|
@ -77,12 +77,12 @@ void SetupDirtyDepthBounds(Tables& tables) {
|
||||||
void SetupDirtyStencilProperties(Tables& tables) {
|
void SetupDirtyStencilProperties(Tables& tables) {
|
||||||
auto& table = tables[0];
|
auto& table = tables[0];
|
||||||
table[OFF(stencil_two_side_enable)] = StencilProperties;
|
table[OFF(stencil_two_side_enable)] = StencilProperties;
|
||||||
table[OFF(stencil_front_func.ref)] = StencilProperties;
|
table[OFF(stencil_front_ref)] = StencilProperties;
|
||||||
table[OFF(stencil_front_func.mask)] = StencilProperties;
|
table[OFF(stencil_front_mask)] = StencilProperties;
|
||||||
table[OFF(stencil_front_func.func_mask)] = StencilProperties;
|
table[OFF(stencil_front_func_mask)] = StencilProperties;
|
||||||
table[OFF(stencil_back_func.ref)] = StencilProperties;
|
table[OFF(stencil_back_ref)] = StencilProperties;
|
||||||
table[OFF(stencil_back_func.mask)] = StencilProperties;
|
table[OFF(stencil_back_mask)] = StencilProperties;
|
||||||
table[OFF(stencil_back_func.func_mask)] = StencilProperties;
|
table[OFF(stencil_back_func_mask)] = StencilProperties;
|
||||||
}
|
}
|
||||||
|
|
||||||
void SetupDirtyLineWidth(Tables& tables) {
|
void SetupDirtyLineWidth(Tables& tables) {
|
||||||
|
|
Loading…
Reference in a new issue