mirror of
https://github.com/coop-deluxe/sm64coopdx.git
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101 lines
2.5 KiB
ArmAsm
101 lines
2.5 KiB
ArmAsm
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# assembler directives
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.set noat # allow manual use of $at
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.set noreorder # don't insert nops after branches
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.set gp=64
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.include "macros.inc"
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.section .text, "ax"
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/* -------------------------------------------------------------------------------------- */
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/* need to asm these functions because lib32gcc-7-dev-mips-cross does not exist so we */
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/* cannot naturally link a libgcc variant for this target given this architecture and */
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/* compiler. Until we have a good workaround with a gcc target that doesn't involve */
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/* assuming a 32-bit to 64-bit change, we have to encode these functions as raw assembly */
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/* for it to compile. */
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/* -------------------------------------------------------------------------------------- */
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/* TODO: Is there a non-insane way to fix this hack that doesn't involve the user compiling */
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/* a library themselves? */
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glabel __umoddi3
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sw $a0, ($sp)
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sw $a1, 4($sp)
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sw $a2, 8($sp)
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sw $a3, 0xc($sp)
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ld $t7, 8($sp)
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ld $t6, ($sp)
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ddivu $zero, $t6, $t7
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bnez $t7, .L80324144
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nop
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break 7
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.L80324144:
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mfhi $v0
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dsll32 $v1, $v0, 0
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dsra32 $v1, $v1, 0
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jr $ra
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dsra32 $v0, $v0, 0
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glabel __udivdi3
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sw $a0, ($sp)
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sw $a1, 4($sp)
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sw $a2, 8($sp)
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sw $a3, 0xc($sp)
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ld $t7, 8($sp)
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ld $t6, ($sp)
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ddivu $zero, $t6, $t7
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bnez $t7, .L80324180
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nop
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break 7
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.L80324180:
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mflo $v0
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dsll32 $v1, $v0, 0
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dsra32 $v1, $v1, 0
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jr $ra
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dsra32 $v0, $v0, 0
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glabel __moddi3
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sw $a0, ($sp)
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sw $a1, 4($sp)
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sw $a2, 8($sp)
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sw $a3, 0xc($sp)
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ld $t7, 8($sp)
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ld $t6, ($sp)
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ddivu $zero, $t6, $t7
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bnez $t7, .L803241E8
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nop
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break 7
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.L803241E8:
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mfhi $v0
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dsll32 $v1, $v0, 0
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dsra32 $v1, $v1, 0
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jr $ra
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dsra32 $v0, $v0, 0
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glabel __divdi3
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sw $a0, ($sp)
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sw $a1, 4($sp)
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sw $a2, 8($sp)
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sw $a3, 0xc($sp)
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ld $t7, 8($sp)
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ld $t6, ($sp)
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ddiv $zero, $t6, $t7
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nop
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bnez $t7, .L80324228
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nop
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break 7
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.L80324228:
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daddiu $at, $zero, -1
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bne $t7, $at, .L80324244
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daddiu $at, $zero, 1
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dsll32 $at, $at, 0x1f
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bne $t6, $at, .L80324244
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nop
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break 6
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.L80324244:
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mflo $v0
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dsll32 $v1, $v0, 0
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dsra32 $v1, $v1, 0
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jr $ra
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dsra32 $v0, $v0, 0
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