2019-08-25 04:46:40 +00:00
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#ifndef _ULTRA64_PI_H_
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#define _ULTRA64_PI_H_
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/* Ultra64 Parallel Interface */
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/* Types */
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2020-02-03 05:51:26 +00:00
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typedef struct {
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2020-03-02 03:42:52 +00:00
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#if !defined(VERSION_EU) && !defined(VERSION_SH)
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2019-08-25 04:46:40 +00:00
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u32 errStatus;
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2020-02-03 05:51:26 +00:00
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#endif
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2019-08-25 04:46:40 +00:00
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void *dramAddr;
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void *C2Addr;
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u32 sectorSize;
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u32 C1ErrNum;
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u32 C1ErrSector[4];
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} __OSBlockInfo;
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2020-02-03 05:51:26 +00:00
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typedef struct {
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u32 cmdType; // 0
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u16 transferMode; // 4
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u16 blockNum; // 6
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s32 sectorNum; // 8
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uintptr_t devAddr; // c
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2020-03-02 03:42:52 +00:00
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#if defined(VERSION_EU) || defined(VERSION_SH)
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2020-02-03 05:51:26 +00:00
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u32 unk10; //error status added moved to blockinfo
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#endif
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u32 bmCtlShadow; // 10
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u32 seqCtlShadow; // 14
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__OSBlockInfo block[2]; // 18
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2019-08-25 04:46:40 +00:00
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} __OSTranxInfo;
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2020-02-03 05:51:26 +00:00
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typedef struct OSPiHandle_s {
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2019-08-25 04:46:40 +00:00
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struct OSPiHandle_s *next;
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u8 type;
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u8 latency;
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u8 pageSize;
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u8 relDuration;
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u8 pulse;
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u8 domain;
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u32 baseAddress;
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u32 speed;
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__OSTranxInfo transferInfo;
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} OSPiHandle;
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2020-02-03 05:51:26 +00:00
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typedef struct {
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2019-08-25 04:46:40 +00:00
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u8 type;
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2019-10-05 19:08:05 +00:00
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uintptr_t address;
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2019-08-25 04:46:40 +00:00
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} OSPiInfo;
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2020-02-03 05:51:26 +00:00
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typedef struct {
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2019-08-25 04:46:40 +00:00
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u16 type;
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u8 pri;
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u8 status;
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OSMesgQueue *retQueue;
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} OSIoMesgHdr;
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2020-02-03 05:51:26 +00:00
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typedef struct {
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2019-08-25 04:46:40 +00:00
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/*0x00*/ OSIoMesgHdr hdr;
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/*0x08*/ void *dramAddr;
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2019-10-05 19:08:05 +00:00
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/*0x0C*/ uintptr_t devAddr;
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/*0x10*/ size_t size;
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2020-03-02 03:42:52 +00:00
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#if defined(VERSION_EU) || defined(VERSION_SH)
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2020-02-03 05:51:26 +00:00
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OSPiHandle *piHandle; // from the official definition
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#endif
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2019-08-25 04:46:40 +00:00
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} OSIoMesg;
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/* Definitions */
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#define OS_READ 0 // device -> RDRAM
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#define OS_WRITE 1 // device <- RDRAM
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#define OS_MESG_PRI_NORMAL 0
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#define OS_MESG_PRI_HIGH 1
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/* Functions */
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2020-02-03 05:51:26 +00:00
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s32 osPiStartDma(OSIoMesg *mb, s32 priority, s32 direction, uintptr_t devAddr, void *vAddr,
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size_t nbytes, OSMesgQueue *mq);
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void osCreatePiManager(OSPri pri, OSMesgQueue *cmdQ, OSMesg *cmdBuf, s32 cmdMsgCnt);
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2019-08-25 04:46:40 +00:00
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OSMesgQueue *osPiGetCmdQueue(void);
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2019-10-05 19:08:05 +00:00
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s32 osPiWriteIo(uintptr_t devAddr, u32 data);
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s32 osPiReadIo(uintptr_t devAddr, u32 *data);
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2020-06-20 23:21:46 +00:00
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s32 osPiRawStartDma(s32 dir, u32 cart_addr, void *dram_addr, size_t size);
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s32 osEPiRawStartDma(OSPiHandle *piHandle, s32 dir, u32 cart_addr, void *dram_addr, size_t size);
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2019-08-25 04:46:40 +00:00
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#endif
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