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CryptoHelper.cs
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Use ReadOnlySpan<byte> compiler optimization for static data (#3130)
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2022-02-17 21:38:50 +01:00 |
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InstEmitAlu.cs
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Reduce JIT GC allocations (#2515)
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2021-08-17 15:08:34 -03:00 |
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InstEmitAlu32.cs
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Implement PLD and SUB (imm16) on T32, plus UADD8, SADD8, USUB8 and SSUB8 on both A32 and T32 (#3693)
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2022-09-13 19:51:40 -03:00 |
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InstEmitAluHelper.cs
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T32: Add Vfp instructions (#3690)
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2022-09-10 23:03:14 -03:00 |
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InstEmitBfm.cs
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Reduce JIT GC allocations (#2515)
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2021-08-17 15:08:34 -03:00 |
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InstEmitCcmp.cs
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Reduce JIT GC allocations (#2515)
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2021-08-17 15:08:34 -03:00 |
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InstEmitCsel.cs
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Reduce JIT GC allocations (#2515)
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2021-08-17 15:08:34 -03:00 |
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InstEmitDiv.cs
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Reduce JIT GC allocations (#2515)
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2021-08-17 15:08:34 -03:00 |
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InstEmitException.cs
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Decoder: Exit on trapping instructions, and resume execution at trapping instruction (#3153)
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2022-03-04 23:16:58 +01:00 |
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InstEmitException32.cs
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Removed unused usings. (#3593)
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2022-08-18 18:04:54 +02:00 |
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InstEmitFlow.cs
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Reduce JIT GC allocations (#2515)
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2021-08-17 15:08:34 -03:00 |
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InstEmitFlow32.cs
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T32: Add Vfp instructions (#3690)
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2022-09-10 23:03:14 -03:00 |
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InstEmitFlowHelper.cs
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Fix return type mismatch on 32-bit titles (#3000)
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2022-01-16 08:39:43 -03:00 |
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InstEmitHash.cs
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Add SSE4.2 Path for CRC32, add A32 variant, add tests for non-castagnoli variants. (#1328)
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2020-07-13 20:48:14 +10:00 |
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InstEmitHash32.cs
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Add SSE4.2 Path for CRC32, add A32 variant, add tests for non-castagnoli variants. (#1328)
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2020-07-13 20:48:14 +10:00 |
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InstEmitHashHelper.cs
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Reduce JIT GC allocations (#2515)
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2021-08-17 15:08:34 -03:00 |
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InstEmitHelper.cs
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T32: Implement B, B.cond, BL, BLX (#3155)
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2022-03-04 23:05:08 +01:00 |
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InstEmitMemory.cs
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Fix return type mismatch on 32-bit titles (#3000)
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2022-01-16 08:39:43 -03:00 |
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InstEmitMemory32.cs
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Add ADD (zx imm12), NOP, MOV (rs), LDA, TBB, TBH, MOV (zx imm16) and CLZ thumb instructions (#3683)
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2022-09-09 22:09:11 -03:00 |
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InstEmitMemoryEx.cs
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InstEmitMemoryEx: Barrier after write on ordered store (#3193)
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2022-03-19 10:32:35 -03:00 |
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InstEmitMemoryEx32.cs
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Implement Thumb (32-bit) memory (ordered), multiply, extension and bitfield instructions (#3687)
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2022-09-10 22:51:00 -03:00 |
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InstEmitMemoryExHelper.cs
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Reduce JIT GC allocations (#2515)
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2021-08-17 15:08:34 -03:00 |
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InstEmitMemoryHelper.cs
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Add ADD (zx imm12), NOP, MOV (rs), LDA, TBB, TBH, MOV (zx imm16) and CLZ thumb instructions (#3683)
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2022-09-09 22:09:11 -03:00 |
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InstEmitMove.cs
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Reduce JIT GC allocations (#2515)
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2021-08-17 15:08:34 -03:00 |
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InstEmitMul.cs
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Add a new JIT compiler for CPU code (#693)
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2019-08-08 21:56:22 +03:00 |
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InstEmitMul32.cs
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Implement Thumb (32-bit) memory (ordered), multiply, extension and bitfield instructions (#3687)
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2022-09-10 22:51:00 -03:00 |
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InstEmitSimdArithmetic.cs
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Fix small precision error on CPU reciprocal estimate instructions (#3061)
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2022-01-29 23:59:34 +01:00 |
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InstEmitSimdArithmetic32.cs
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Implement VRSRA, VRSHRN, VQSHRUN, VQMOVN, VQMOVUN, VQADD, VQSUB, VRHADD, VPADDL, VSUBL, VQDMULH and VMLAL Arm32 NEON instructions (#3677)
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2022-09-09 21:47:38 -03:00 |
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InstEmitSimdCmp.cs
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Reduce JIT GC allocations (#2515)
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2021-08-17 15:08:34 -03:00 |
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InstEmitSimdCmp32.cs
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Reduce JIT GC allocations (#2515)
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2021-08-17 15:08:34 -03:00 |
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InstEmitSimdCrypto.cs
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Add Profiled Persistent Translation Cache. (#769)
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2020-06-16 20:28:02 +02:00 |
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InstEmitSimdCrypto32.cs
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Add Profiled Persistent Translation Cache. (#769)
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2020-06-16 20:28:02 +02:00 |
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InstEmitSimdCvt.cs
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Implement CPU FCVT Half <-> Double conversion variants (#3439)
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2022-07-06 13:40:31 +02:00 |
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InstEmitSimdCvt32.cs
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Implement VRINT (vector) Arm32 NEON instructions (#3691)
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2022-09-11 15:44:27 +00:00 |
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InstEmitSimdHash.cs
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ARMeilleure: Hardware accelerate SHA256 (#3585)
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2022-08-25 10:12:13 +00:00 |
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InstEmitSimdHash32.cs
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ARMeilleure: Hardware accelerate SHA256 (#3585)
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2022-08-25 10:12:13 +00:00 |
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InstEmitSimdHashHelper.cs
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ARMeilleure: Hardware accelerate SHA256 (#3585)
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2022-08-25 10:12:13 +00:00 |
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InstEmitSimdHelper.cs
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Implement VRSRA, VRSHRN, VQSHRUN, VQMOVN, VQMOVUN, VQADD, VQSUB, VRHADD, VPADDL, VSUBL, VQDMULH and VMLAL Arm32 NEON instructions (#3677)
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2022-09-09 21:47:38 -03:00 |
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InstEmitSimdHelper32.cs
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Implement VRSRA, VRSHRN, VQSHRUN, VQMOVN, VQMOVUN, VQADD, VQSUB, VRHADD, VPADDL, VSUBL, VQDMULH and VMLAL Arm32 NEON instructions (#3677)
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2022-09-09 21:47:38 -03:00 |
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InstEmitSimdLogical.cs
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Reduce JIT GC allocations (#2515)
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2021-08-17 15:08:34 -03:00 |
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InstEmitSimdLogical32.cs
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Reduce JIT GC allocations (#2515)
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2021-08-17 15:08:34 -03:00 |
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InstEmitSimdMemory.cs
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Reduce JIT GC allocations (#2515)
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2021-08-17 15:08:34 -03:00 |
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InstEmitSimdMemory32.cs
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Fix increment on Arm32 NEON VLDn/VSTn instructions with regs > 1 (#3695)
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2022-09-13 08:24:09 +02:00 |
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InstEmitSimdMove.cs
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Reduce JIT GC allocations (#2515)
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2021-08-17 15:08:34 -03:00 |
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InstEmitSimdMove32.cs
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Reduce JIT GC allocations (#2515)
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2021-08-17 15:08:34 -03:00 |
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InstEmitSimdShift.cs
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Implemented in IR the managed methods of the Saturating region ... (#3665)
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2022-09-08 19:40:41 -03:00 |
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InstEmitSimdShift32.cs
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Implement VRSRA, VRSHRN, VQSHRUN, VQMOVN, VQMOVUN, VQADD, VQSUB, VRHADD, VPADDL, VSUBL, VQDMULH and VMLAL Arm32 NEON instructions (#3677)
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2022-09-09 21:47:38 -03:00 |
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InstEmitSystem.cs
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Refactor CPU interface to allow the implementation of other CPU emulators (#3362)
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2022-05-31 16:29:35 -03:00 |
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InstEmitSystem32.cs
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Implement VRSRA, VRSHRN, VQSHRUN, VQMOVN, VQMOVUN, VQADD, VQSUB, VRHADD, VPADDL, VSUBL, VQDMULH and VMLAL Arm32 NEON instructions (#3677)
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2022-09-09 21:47:38 -03:00 |
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InstName.cs
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Implement PLD and SUB (imm16) on T32, plus UADD8, SADD8, USUB8 and SSUB8 on both A32 and T32 (#3693)
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2022-09-13 19:51:40 -03:00 |
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NativeInterface.cs
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Removed unused usings. (#3593)
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2022-08-18 18:04:54 +02:00 |
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SoftFallback.cs
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Implemented in IR the managed methods of the Saturating region ... (#3665)
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2022-09-08 19:40:41 -03:00 |
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SoftFloat.cs
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Implement CPU FCVT Half <-> Double conversion variants (#3439)
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2022-07-06 13:40:31 +02:00 |
