mirror of
https://github.com/ryujinx-mirror/ryujinx.git
synced 2024-11-23 18:45:11 +00:00
a731ab3a2a
* Start of the ARMeilleure project * Refactoring around the old IRAdapter, now renamed to PreAllocator * Optimize the LowestBitSet method * Add CLZ support and fix CLS implementation * Add missing Equals and GetHashCode overrides on some structs, misc small tweaks * Implement the ByteSwap IR instruction, and some refactoring on the assembler * Implement the DivideUI IR instruction and fix 64-bits IDIV * Correct constant operand type on CSINC * Move division instructions implementation to InstEmitDiv * Fix destination type for the ConditionalSelect IR instruction * Implement UMULH and SMULH, with new IR instructions * Fix some issues with shift instructions * Fix constant types for BFM instructions * Fix up new tests using the new V128 struct * Update tests * Move DIV tests to a separate file * Add support for calls, and some instructions that depends on them * Start adding support for SIMD & FP types, along with some of the related ARM instructions * Fix some typos and the divide instruction with FP operands * Fix wrong method call on Clz_V * Implement ARM FP & SIMD move instructions, Saddlv_V, and misc. fixes * Implement SIMD logical instructions and more misc. fixes * Fix PSRAD x86 instruction encoding, TRN, UABD and UABDL implementations * Implement float conversion instruction, merge in LDj3SNuD fixes, and some other misc. fixes * Implement SIMD shift instruction and fix Dup_V * Add SCVTF and UCVTF (vector, fixed-point) variants to the opcode table * Fix check with tolerance on tester * Implement FP & SIMD comparison instructions, and some fixes * Update FCVT (Scalar) encoding on the table to support the Half-float variants * Support passing V128 structs, some cleanup on the register allocator, merge LDj3SNuD fixes * Use old memory access methods, made a start on SIMD memory insts support, some fixes * Fix float constant passed to functions, save and restore non-volatile XMM registers, other fixes * Fix arguments count with struct return values, other fixes * More instructions * Misc. fixes and integrate LDj3SNuD fixes * Update tests * Add a faster linear scan allocator, unwinding support on windows, and other changes * Update Ryujinx.HLE * Update Ryujinx.Graphics * Fix V128 return pointer passing, RCX is clobbered * Update Ryujinx.Tests * Update ITimeZoneService * Stop using GetFunctionPointer as that can't be called from native code, misc. fixes and tweaks * Use generic GetFunctionPointerForDelegate method and other tweaks * Some refactoring on the code generator, assert on invalid operations and use a separate enum for intrinsics * Remove some unused code on the assembler * Fix REX.W prefix regression on float conversion instructions, add some sort of profiler * Add hardware capability detection * Fix regression on Sha1h and revert Fcm** changes * Add SSE2-only paths on vector extract and insert, some refactoring on the pre-allocator * Fix silly mistake introduced on last commit on CpuId * Generate inline stack probes when the stack allocation is too large * Initial support for the System-V ABI * Support multiple destination operands * Fix SSE2 VectorInsert8 path, and other fixes * Change placement of XMM callee save and restore code to match other compilers * Rename Dest to Destination and Inst to Instruction * Fix a regression related to calls and the V128 type * Add an extra space on comments to match code style * Some refactoring * Fix vector insert FP32 SSE2 path * Port over the ARM32 instructions * Avoid memory protection races on JIT Cache * Another fix on VectorInsert FP32 (thanks to LDj3SNuD * Float operands don't need to use the same register when VEX is supported * Add a new register allocator, higher quality code for hot code (tier up), and other tweaks * Some nits, small improvements on the pre allocator * CpuThreadState is gone * Allow changing CPU emulators with a config entry * Add runtime identifiers on the ARMeilleure project * Allow switching between CPUs through a config entry (pt. 2) * Change win10-x64 to win-x64 on projects * Update the Ryujinx project to use ARMeilleure * Ensure that the selected register is valid on the hybrid allocator * Allow exiting on returns to 0 (should fix test regression) * Remove register assignments for most used variables on the hybrid allocator * Do not use fixed registers as spill temp * Add missing namespace and remove unneeded using * Address PR feedback * Fix types, etc * Enable AssumeStrictAbiCompliance by default * Ensure that Spill and Fill don't load or store any more than necessary
794 lines
No EOL
26 KiB
C#
794 lines
No EOL
26 KiB
C#
using ARMeilleure.Decoders;
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using ARMeilleure.IntermediateRepresentation;
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using ARMeilleure.Translation;
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using System;
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using static ARMeilleure.Instructions.InstEmitHelper;
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using static ARMeilleure.Instructions.InstEmitSimdHelper;
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using static ARMeilleure.IntermediateRepresentation.OperandHelper;
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namespace ARMeilleure.Instructions
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{
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static partial class InstEmit
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{
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#region "Masks"
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private static readonly long[] _masksE0_TrnUzpXtn = new long[]
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{
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14L << 56 | 12L << 48 | 10L << 40 | 08L << 32 | 06L << 24 | 04L << 16 | 02L << 8 | 00L << 0,
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13L << 56 | 12L << 48 | 09L << 40 | 08L << 32 | 05L << 24 | 04L << 16 | 01L << 8 | 00L << 0,
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11L << 56 | 10L << 48 | 09L << 40 | 08L << 32 | 03L << 24 | 02L << 16 | 01L << 8 | 00L << 0
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};
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private static readonly long[] _masksE1_TrnUzp = new long[]
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{
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15L << 56 | 13L << 48 | 11L << 40 | 09L << 32 | 07L << 24 | 05L << 16 | 03L << 8 | 01L << 0,
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15L << 56 | 14L << 48 | 11L << 40 | 10L << 32 | 07L << 24 | 06L << 16 | 03L << 8 | 02L << 0,
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15L << 56 | 14L << 48 | 13L << 40 | 12L << 32 | 07L << 24 | 06L << 16 | 05L << 8 | 04L << 0
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};
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private static readonly long[] _masksE0_Uzp = new long[]
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{
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13L << 56 | 09L << 48 | 05L << 40 | 01L << 32 | 12L << 24 | 08L << 16 | 04L << 8 | 00L << 0,
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11L << 56 | 10L << 48 | 03L << 40 | 02L << 32 | 09L << 24 | 08L << 16 | 01L << 8 | 00L << 0
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};
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private static readonly long[] _masksE1_Uzp = new long[]
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{
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15L << 56 | 11L << 48 | 07L << 40 | 03L << 32 | 14L << 24 | 10L << 16 | 06L << 8 | 02L << 0,
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15L << 56 | 14L << 48 | 07L << 40 | 06L << 32 | 13L << 24 | 12L << 16 | 05L << 8 | 04L << 0
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};
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#endregion
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public static void Dup_Gp(ArmEmitterContext context)
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{
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OpCodeSimdIns op = (OpCodeSimdIns)context.CurrOp;
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Operand n = GetIntOrZR(context, op.Rn);
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if (Optimizations.UseSse2)
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{
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switch (op.Size)
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{
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case 0: n = context.ZeroExtend8 (n.Type, n); n = context.Multiply(n, Const(n.Type, 0x01010101)); break;
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case 1: n = context.ZeroExtend16(n.Type, n); n = context.Multiply(n, Const(n.Type, 0x00010001)); break;
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case 2: n = context.ZeroExtend32(n.Type, n); break;
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}
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Operand res = context.VectorInsert(context.VectorZero(), n, 0);
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if (op.Size < 3)
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{
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if (op.RegisterSize == RegisterSize.Simd64)
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{
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res = context.AddIntrinsic(Intrinsic.X86Shufps, res, res, Const(0xf0));
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}
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else
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{
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res = context.AddIntrinsic(Intrinsic.X86Shufps, res, res, Const(0));
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}
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}
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else
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{
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res = context.AddIntrinsic(Intrinsic.X86Movlhps, res, res);
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}
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context.Copy(GetVec(op.Rd), res);
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}
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else
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{
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Operand res = context.VectorZero();
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int elems = op.GetBytesCount() >> op.Size;
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for (int index = 0; index < elems; index++)
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{
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res = EmitVectorInsert(context, res, n, index, op.Size);
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}
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context.Copy(GetVec(op.Rd), res);
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}
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}
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public static void Dup_S(ArmEmitterContext context)
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{
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OpCodeSimdIns op = (OpCodeSimdIns)context.CurrOp;
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Operand ne = EmitVectorExtractZx(context, op.Rn, op.DstIndex, op.Size);
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context.Copy(GetVec(op.Rd), EmitVectorInsert(context, context.VectorZero(), ne, 0, op.Size));
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}
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public static void Dup_V(ArmEmitterContext context)
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{
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OpCodeSimdIns op = (OpCodeSimdIns)context.CurrOp;
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if (Optimizations.UseSse2)
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{
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Operand res = GetVec(op.Rn);
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if (op.Size == 0)
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{
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if (op.DstIndex != 0)
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{
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res = context.AddIntrinsic(Intrinsic.X86Psrldq, res, Const(op.DstIndex));
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}
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res = context.AddIntrinsic(Intrinsic.X86Punpcklbw, res, res);
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res = context.AddIntrinsic(Intrinsic.X86Punpcklwd, res, res);
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res = context.AddIntrinsic(Intrinsic.X86Shufps, res, res, Const(0));
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}
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else if (op.Size == 1)
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{
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if (op.DstIndex != 0)
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{
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res = context.AddIntrinsic(Intrinsic.X86Psrldq, res, Const(op.DstIndex * 2));
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}
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res = context.AddIntrinsic(Intrinsic.X86Punpcklwd, res, res);
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res = context.AddIntrinsic(Intrinsic.X86Shufps, res, res, Const(0));
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}
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else if (op.Size == 2)
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{
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int mask = op.DstIndex * 0b01010101;
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res = context.AddIntrinsic(Intrinsic.X86Shufps, res, res, Const(mask));
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}
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else if (op.DstIndex == 0 && op.RegisterSize != RegisterSize.Simd64)
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{
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res = context.AddIntrinsic(Intrinsic.X86Movlhps, res, res);
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}
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else if (op.DstIndex == 1)
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{
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res = context.AddIntrinsic(Intrinsic.X86Movhlps, res, res);
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}
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if (op.RegisterSize == RegisterSize.Simd64)
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{
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res = context.VectorZeroUpper64(res);
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}
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context.Copy(GetVec(op.Rd), res);
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}
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else
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{
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Operand ne = EmitVectorExtractZx(context, op.Rn, op.DstIndex, op.Size);
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Operand res = context.VectorZero();
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int elems = op.GetBytesCount() >> op.Size;
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for (int index = 0; index < elems; index++)
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{
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res = EmitVectorInsert(context, res, ne, index, op.Size);
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}
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context.Copy(GetVec(op.Rd), res);
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}
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}
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public static void Ext_V(ArmEmitterContext context)
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{
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OpCodeSimdExt op = (OpCodeSimdExt)context.CurrOp;
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if (Optimizations.UseSse2)
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{
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Operand nShifted = GetVec(op.Rn);
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if (op.RegisterSize == RegisterSize.Simd64)
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{
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nShifted = context.AddIntrinsic(Intrinsic.X86Movlhps, nShifted, context.VectorZero());
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}
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nShifted = context.AddIntrinsic(Intrinsic.X86Psrldq, nShifted, Const(op.Imm4));
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Operand mShifted = GetVec(op.Rm);
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mShifted = context.AddIntrinsic(Intrinsic.X86Pslldq, mShifted, Const(op.GetBytesCount() - op.Imm4));
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if (op.RegisterSize == RegisterSize.Simd64)
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{
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mShifted = context.AddIntrinsic(Intrinsic.X86Movlhps, mShifted, context.VectorZero());
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}
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Operand res = context.AddIntrinsic(Intrinsic.X86Por, nShifted, mShifted);
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context.Copy(GetVec(op.Rd), res);
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}
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else
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{
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Operand res = context.VectorZero();
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int bytes = op.GetBytesCount();
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int position = op.Imm4 & (bytes - 1);
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for (int index = 0; index < bytes; index++)
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{
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int reg = op.Imm4 + index < bytes ? op.Rn : op.Rm;
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Operand e = EmitVectorExtractZx(context, reg, position, 0);
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position = (position + 1) & (bytes - 1);
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res = EmitVectorInsert(context, res, e, index, 0);
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}
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context.Copy(GetVec(op.Rd), res);
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}
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}
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public static void Fcsel_S(ArmEmitterContext context)
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{
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OpCodeSimdFcond op = (OpCodeSimdFcond)context.CurrOp;
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Operand lblTrue = Label();
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Operand lblEnd = Label();
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Operand isTrue = InstEmitFlowHelper.GetCondTrue(context, op.Cond);
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context.BranchIfTrue(lblTrue, isTrue);
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OperandType type = op.Size == 0 ? OperandType.FP32 : OperandType.FP64;
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Operand me = context.VectorExtract(type, GetVec(op.Rm), 0);
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context.Copy(GetVec(op.Rd), context.VectorInsert(context.VectorZero(), me, 0));
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context.Branch(lblEnd);
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context.MarkLabel(lblTrue);
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Operand ne = context.VectorExtract(type, GetVec(op.Rn), 0);
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context.Copy(GetVec(op.Rd), context.VectorInsert(context.VectorZero(), ne, 0));
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context.MarkLabel(lblEnd);
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}
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public static void Fmov_Ftoi(ArmEmitterContext context)
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{
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OpCodeSimd op = (OpCodeSimd)context.CurrOp;
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Operand ne = EmitVectorExtractZx(context, op.Rn, 0, op.Size + 2);
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SetIntOrZR(context, op.Rd, ne);
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}
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public static void Fmov_Ftoi1(ArmEmitterContext context)
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{
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OpCodeSimd op = (OpCodeSimd)context.CurrOp;
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Operand ne = EmitVectorExtractZx(context, op.Rn, 1, 3);
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SetIntOrZR(context, op.Rd, ne);
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}
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public static void Fmov_Itof(ArmEmitterContext context)
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{
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OpCodeSimd op = (OpCodeSimd)context.CurrOp;
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Operand n = GetIntOrZR(context, op.Rn);
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context.Copy(GetVec(op.Rd), EmitVectorInsert(context, context.VectorZero(), n, 0, op.Size + 2));
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}
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public static void Fmov_Itof1(ArmEmitterContext context)
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{
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OpCodeSimd op = (OpCodeSimd)context.CurrOp;
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Operand n = GetIntOrZR(context, op.Rn);
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context.Copy(GetVec(op.Rd), EmitVectorInsert(context, GetVec(op.Rd), n, 1, 3));
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}
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public static void Fmov_S(ArmEmitterContext context)
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{
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OpCodeSimd op = (OpCodeSimd)context.CurrOp;
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OperandType type = op.Size == 0 ? OperandType.FP32 : OperandType.FP64;
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Operand ne = context.VectorExtract(type, GetVec(op.Rn), 0);
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context.Copy(GetVec(op.Rd), context.VectorInsert(context.VectorZero(), ne, 0));
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}
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public static void Fmov_Si(ArmEmitterContext context)
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{
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OpCodeSimdFmov op = (OpCodeSimdFmov)context.CurrOp;
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if (op.Size == 0)
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{
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context.Copy(GetVec(op.Rd), X86GetScalar(context, (int)op.Immediate));
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}
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else
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{
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context.Copy(GetVec(op.Rd), X86GetScalar(context, op.Immediate));
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}
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}
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public static void Fmov_Vi(ArmEmitterContext context)
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{
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OpCodeSimdImm op = (OpCodeSimdImm)context.CurrOp;
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Operand e = Const(op.Immediate);
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Operand res = context.VectorZero();
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int elems = op.RegisterSize == RegisterSize.Simd128 ? 4 : 2;
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for (int index = 0; index < (elems >> op.Size); index++)
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{
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res = EmitVectorInsert(context, res, e, index, op.Size + 2);
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}
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context.Copy(GetVec(op.Rd), res);
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}
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public static void Ins_Gp(ArmEmitterContext context)
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{
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OpCodeSimdIns op = (OpCodeSimdIns)context.CurrOp;
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Operand d = GetVec(op.Rd);
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Operand n = GetIntOrZR(context, op.Rn);
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context.Copy(d, EmitVectorInsert(context, d, n, op.DstIndex, op.Size));
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}
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public static void Ins_V(ArmEmitterContext context)
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{
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OpCodeSimdIns op = (OpCodeSimdIns)context.CurrOp;
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Operand d = GetVec(op.Rd);
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Operand ne = EmitVectorExtractZx(context, op.Rn, op.SrcIndex, op.Size);
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context.Copy(d, EmitVectorInsert(context, d, ne, op.DstIndex, op.Size));
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}
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public static void Movi_V(ArmEmitterContext context)
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{
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if (Optimizations.UseSse2)
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{
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EmitMoviMvni(context, not: false);
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}
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else
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{
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EmitVectorImmUnaryOp(context, (op1) => op1);
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}
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}
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public static void Mvni_V(ArmEmitterContext context)
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{
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if (Optimizations.UseSse2)
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{
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EmitMoviMvni(context, not: true);
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}
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else
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{
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EmitVectorImmUnaryOp(context, (op1) => context.BitwiseNot(op1));
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}
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}
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public static void Smov_S(ArmEmitterContext context)
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{
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OpCodeSimdIns op = (OpCodeSimdIns)context.CurrOp;
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Operand ne = EmitVectorExtractSx(context, op.Rn, op.DstIndex, op.Size);
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if (op.RegisterSize == RegisterSize.Simd64)
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{
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ne = context.ZeroExtend32(OperandType.I64, ne);
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}
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SetIntOrZR(context, op.Rd, ne);
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}
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public static void Tbl_V(ArmEmitterContext context)
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{
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OpCodeSimdTbl op = (OpCodeSimdTbl)context.CurrOp;
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if (Optimizations.UseSsse3)
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{
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Operand n = GetVec(op.Rn);
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Operand m = GetVec(op.Rm);
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Operand mask = X86GetAllElements(context, 0x0F0F0F0F0F0F0F0FL);
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Operand mMask = context.AddIntrinsic(Intrinsic.X86Pcmpgtb, m, mask);
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mMask = context.AddIntrinsic(Intrinsic.X86Por, mMask, m);
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Operand res = context.AddIntrinsic(Intrinsic.X86Pshufb, n, mMask);
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for (int index = 1; index < op.Size; index++)
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{
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Operand ni = GetVec((op.Rn + index) & 0x1f);
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Operand indexMask = X86GetAllElements(context, 0x1010101010101010L * index);
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Operand mMinusMask = context.AddIntrinsic(Intrinsic.X86Psubb, m, indexMask);
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Operand mMask2 = context.AddIntrinsic(Intrinsic.X86Pcmpgtb, mMinusMask, mask);
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mMask2 = context.AddIntrinsic(Intrinsic.X86Por, mMask2, mMinusMask);
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Operand res2 = context.AddIntrinsic(Intrinsic.X86Pshufb, ni, mMask2);
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res = context.AddIntrinsic(Intrinsic.X86Por, res, res2);
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}
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if (op.RegisterSize == RegisterSize.Simd64)
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{
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res = context.VectorZeroUpper64(res);
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}
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context.Copy(GetVec(op.Rd), res);
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}
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else
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{
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Operand[] args = new Operand[1 + op.Size];
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args[0] = GetVec(op.Rm);
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for (int index = 0; index < op.Size; index++)
|
|
{
|
|
args[1 + index] = GetVec((op.Rn + index) & 0x1f);
|
|
}
|
|
|
|
Delegate dlg = null;
|
|
|
|
switch (op.Size)
|
|
{
|
|
case 1: dlg = op.RegisterSize == RegisterSize.Simd64
|
|
? (Delegate)new _V128_V128_V128(SoftFallback.Tbl1_V64)
|
|
: (Delegate)new _V128_V128_V128(SoftFallback.Tbl1_V128); break;
|
|
|
|
case 2: dlg = op.RegisterSize == RegisterSize.Simd64
|
|
? (Delegate)new _V128_V128_V128_V128(SoftFallback.Tbl2_V64)
|
|
: (Delegate)new _V128_V128_V128_V128(SoftFallback.Tbl2_V128); break;
|
|
|
|
case 3: dlg = op.RegisterSize == RegisterSize.Simd64
|
|
? (Delegate)new _V128_V128_V128_V128_V128(SoftFallback.Tbl3_V64)
|
|
: (Delegate)new _V128_V128_V128_V128_V128(SoftFallback.Tbl3_V128); break;
|
|
|
|
case 4: dlg = op.RegisterSize == RegisterSize.Simd64
|
|
? (Delegate)new _V128_V128_V128_V128_V128_V128(SoftFallback.Tbl4_V64)
|
|
: (Delegate)new _V128_V128_V128_V128_V128_V128(SoftFallback.Tbl4_V128); break;
|
|
}
|
|
|
|
context.Copy(GetVec(op.Rd), context.Call(dlg, args));
|
|
}
|
|
}
|
|
|
|
public static void Trn1_V(ArmEmitterContext context)
|
|
{
|
|
EmitVectorTranspose(context, part: 0);
|
|
}
|
|
|
|
public static void Trn2_V(ArmEmitterContext context)
|
|
{
|
|
EmitVectorTranspose(context, part: 1);
|
|
}
|
|
|
|
public static void Umov_S(ArmEmitterContext context)
|
|
{
|
|
OpCodeSimdIns op = (OpCodeSimdIns)context.CurrOp;
|
|
|
|
Operand ne = EmitVectorExtractZx(context, op.Rn, op.DstIndex, op.Size);
|
|
|
|
SetIntOrZR(context, op.Rd, ne);
|
|
}
|
|
|
|
public static void Uzp1_V(ArmEmitterContext context)
|
|
{
|
|
EmitVectorUnzip(context, part: 0);
|
|
}
|
|
|
|
public static void Uzp2_V(ArmEmitterContext context)
|
|
{
|
|
EmitVectorUnzip(context, part: 1);
|
|
}
|
|
|
|
public static void Xtn_V(ArmEmitterContext context)
|
|
{
|
|
OpCodeSimd op = (OpCodeSimd)context.CurrOp;
|
|
|
|
if (Optimizations.UseSsse3)
|
|
{
|
|
Operand d = GetVec(op.Rd);
|
|
|
|
Operand res = context.AddIntrinsic(Intrinsic.X86Movlhps, d, context.VectorZero());
|
|
|
|
Operand n = GetVec(op.Rn);
|
|
|
|
Operand mask = X86GetAllElements(context, _masksE0_TrnUzpXtn[op.Size]);
|
|
|
|
Operand res2 = context.AddIntrinsic(Intrinsic.X86Pshufb, n, mask);
|
|
|
|
Intrinsic movInst = op.RegisterSize == RegisterSize.Simd128
|
|
? Intrinsic.X86Movlhps
|
|
: Intrinsic.X86Movhlps;
|
|
|
|
res = context.AddIntrinsic(movInst, res, res2);
|
|
|
|
context.Copy(GetVec(op.Rd), res);
|
|
}
|
|
else
|
|
{
|
|
int elems = 8 >> op.Size;
|
|
|
|
int part = op.RegisterSize == RegisterSize.Simd128 ? elems : 0;
|
|
|
|
Operand res = part == 0 ? context.VectorZero() : context.Copy(GetVec(op.Rd));
|
|
|
|
for (int index = 0; index < elems; index++)
|
|
{
|
|
Operand ne = EmitVectorExtractZx(context, op.Rn, index, op.Size + 1);
|
|
|
|
res = EmitVectorInsert(context, res, ne, part + index, op.Size);
|
|
}
|
|
|
|
context.Copy(GetVec(op.Rd), res);
|
|
}
|
|
}
|
|
|
|
public static void Zip1_V(ArmEmitterContext context)
|
|
{
|
|
EmitVectorZip(context, part: 0);
|
|
}
|
|
|
|
public static void Zip2_V(ArmEmitterContext context)
|
|
{
|
|
EmitVectorZip(context, part: 1);
|
|
}
|
|
|
|
private static void EmitMoviMvni(ArmEmitterContext context, bool not)
|
|
{
|
|
OpCodeSimdImm op = (OpCodeSimdImm)context.CurrOp;
|
|
|
|
long imm = op.Immediate;
|
|
|
|
switch (op.Size)
|
|
{
|
|
case 0: imm *= 0x01010101; break;
|
|
case 1: imm *= 0x00010001; break;
|
|
}
|
|
|
|
if (not)
|
|
{
|
|
imm = ~imm;
|
|
}
|
|
|
|
Operand mask;
|
|
|
|
if (op.Size < 3)
|
|
{
|
|
mask = X86GetAllElements(context, (int)imm);
|
|
}
|
|
else
|
|
{
|
|
mask = X86GetAllElements(context, imm);
|
|
}
|
|
|
|
if (op.RegisterSize == RegisterSize.Simd64)
|
|
{
|
|
mask = context.VectorZeroUpper64(mask);
|
|
}
|
|
|
|
context.Copy(GetVec(op.Rd), mask);
|
|
}
|
|
|
|
private static void EmitVectorTranspose(ArmEmitterContext context, int part)
|
|
{
|
|
OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp;
|
|
|
|
if (Optimizations.UseSsse3)
|
|
{
|
|
Operand mask = null;
|
|
|
|
if (op.Size < 3)
|
|
{
|
|
long maskE0 = _masksE0_TrnUzpXtn[op.Size];
|
|
long maskE1 = _masksE1_TrnUzp [op.Size];
|
|
|
|
mask = X86GetScalar(context, maskE0);
|
|
|
|
mask = EmitVectorInsert(context, mask, Const(maskE1), 1, 3);
|
|
}
|
|
|
|
Operand n = GetVec(op.Rn);
|
|
|
|
if (op.Size < 3)
|
|
{
|
|
n = context.AddIntrinsic(Intrinsic.X86Pshufb, n, mask);
|
|
}
|
|
|
|
Operand m = GetVec(op.Rm);
|
|
|
|
if (op.Size < 3)
|
|
{
|
|
m = context.AddIntrinsic(Intrinsic.X86Pshufb, m, mask);
|
|
}
|
|
|
|
Intrinsic punpckInst = part == 0
|
|
? X86PunpcklInstruction[op.Size]
|
|
: X86PunpckhInstruction[op.Size];
|
|
|
|
Operand res = context.AddIntrinsic(punpckInst, n, m);
|
|
|
|
if (op.RegisterSize == RegisterSize.Simd64)
|
|
{
|
|
res = context.VectorZeroUpper64(res);
|
|
}
|
|
|
|
context.Copy(GetVec(op.Rd), res);
|
|
}
|
|
else
|
|
{
|
|
Operand res = context.VectorZero();
|
|
|
|
int pairs = op.GetPairsCount() >> op.Size;
|
|
|
|
for (int index = 0; index < pairs; index++)
|
|
{
|
|
int pairIndex = index << 1;
|
|
|
|
Operand ne = EmitVectorExtractZx(context, op.Rn, pairIndex + part, op.Size);
|
|
Operand me = EmitVectorExtractZx(context, op.Rm, pairIndex + part, op.Size);
|
|
|
|
res = EmitVectorInsert(context, res, ne, pairIndex, op.Size);
|
|
res = EmitVectorInsert(context, res, me, pairIndex + 1, op.Size);
|
|
}
|
|
|
|
context.Copy(GetVec(op.Rd), res);
|
|
}
|
|
}
|
|
|
|
private static void EmitVectorUnzip(ArmEmitterContext context, int part)
|
|
{
|
|
OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp;
|
|
|
|
if (Optimizations.UseSsse3)
|
|
{
|
|
if (op.RegisterSize == RegisterSize.Simd128)
|
|
{
|
|
Operand mask = null;
|
|
|
|
if (op.Size < 3)
|
|
{
|
|
long maskE0 = _masksE0_TrnUzpXtn[op.Size];
|
|
long maskE1 = _masksE1_TrnUzp [op.Size];
|
|
|
|
mask = X86GetScalar(context, maskE0);
|
|
|
|
mask = EmitVectorInsert(context, mask, Const(maskE1), 1, 3);
|
|
}
|
|
|
|
Operand n = GetVec(op.Rn);
|
|
|
|
if (op.Size < 3)
|
|
{
|
|
n = context.AddIntrinsic(Intrinsic.X86Pshufb, n, mask);
|
|
}
|
|
|
|
Operand m = GetVec(op.Rm);
|
|
|
|
if (op.Size < 3)
|
|
{
|
|
m = context.AddIntrinsic(Intrinsic.X86Pshufb, m, mask);
|
|
}
|
|
|
|
Intrinsic punpckInst = part == 0
|
|
? Intrinsic.X86Punpcklqdq
|
|
: Intrinsic.X86Punpckhqdq;
|
|
|
|
Operand res = context.AddIntrinsic(punpckInst, n, m);
|
|
|
|
context.Copy(GetVec(op.Rd), res);
|
|
}
|
|
else
|
|
{
|
|
Operand n = GetVec(op.Rn);
|
|
Operand m = GetVec(op.Rm);
|
|
|
|
Intrinsic punpcklInst = X86PunpcklInstruction[op.Size];
|
|
|
|
Operand res = context.AddIntrinsic(punpcklInst, n, m);
|
|
|
|
if (op.Size < 2)
|
|
{
|
|
long maskE0 = _masksE0_Uzp[op.Size];
|
|
long maskE1 = _masksE1_Uzp[op.Size];
|
|
|
|
Operand mask = X86GetScalar(context, maskE0);
|
|
|
|
mask = EmitVectorInsert(context, mask, Const(maskE1), 1, 3);
|
|
|
|
res = context.AddIntrinsic(Intrinsic.X86Pshufb, res, mask);
|
|
}
|
|
|
|
Intrinsic punpckInst = part == 0
|
|
? Intrinsic.X86Punpcklqdq
|
|
: Intrinsic.X86Punpckhqdq;
|
|
|
|
res = context.AddIntrinsic(punpckInst, res, context.VectorZero());
|
|
|
|
context.Copy(GetVec(op.Rd), res);
|
|
}
|
|
}
|
|
else
|
|
{
|
|
Operand res = context.VectorZero();
|
|
|
|
int pairs = op.GetPairsCount() >> op.Size;
|
|
|
|
for (int index = 0; index < pairs; index++)
|
|
{
|
|
int idx = index << 1;
|
|
|
|
Operand ne = EmitVectorExtractZx(context, op.Rn, idx + part, op.Size);
|
|
Operand me = EmitVectorExtractZx(context, op.Rm, idx + part, op.Size);
|
|
|
|
res = EmitVectorInsert(context, res, ne, index, op.Size);
|
|
res = EmitVectorInsert(context, res, me, pairs + index, op.Size);
|
|
}
|
|
|
|
context.Copy(GetVec(op.Rd), res);
|
|
}
|
|
}
|
|
|
|
private static void EmitVectorZip(ArmEmitterContext context, int part)
|
|
{
|
|
OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp;
|
|
|
|
if (Optimizations.UseSse2)
|
|
{
|
|
Operand n = GetVec(op.Rn);
|
|
Operand m = GetVec(op.Rm);
|
|
|
|
if (op.RegisterSize == RegisterSize.Simd128)
|
|
{
|
|
Intrinsic punpckInst = part == 0
|
|
? X86PunpcklInstruction[op.Size]
|
|
: X86PunpckhInstruction[op.Size];
|
|
|
|
Operand res = context.AddIntrinsic(punpckInst, n, m);
|
|
|
|
context.Copy(GetVec(op.Rd), res);
|
|
}
|
|
else
|
|
{
|
|
Operand res = context.AddIntrinsic(X86PunpcklInstruction[op.Size], n, m);
|
|
|
|
Intrinsic punpckInst = part == 0
|
|
? Intrinsic.X86Punpcklqdq
|
|
: Intrinsic.X86Punpckhqdq;
|
|
|
|
res = context.AddIntrinsic(punpckInst, res, context.VectorZero());
|
|
|
|
context.Copy(GetVec(op.Rd), res);
|
|
}
|
|
}
|
|
else
|
|
{
|
|
Operand res = context.VectorZero();
|
|
|
|
int pairs = op.GetPairsCount() >> op.Size;
|
|
|
|
int baseIndex = part != 0 ? pairs : 0;
|
|
|
|
for (int index = 0; index < pairs; index++)
|
|
{
|
|
int pairIndex = index << 1;
|
|
|
|
Operand ne = EmitVectorExtractZx(context, op.Rn, baseIndex + index, op.Size);
|
|
Operand me = EmitVectorExtractZx(context, op.Rm, baseIndex + index, op.Size);
|
|
|
|
res = EmitVectorInsert(context, res, ne, pairIndex, op.Size);
|
|
res = EmitVectorInsert(context, res, me, pairIndex + 1, op.Size);
|
|
}
|
|
|
|
context.Copy(GetVec(op.Rd), res);
|
|
}
|
|
}
|
|
}
|
|
} |